diff options
| author | Chetan C R <cchinnad@qti.qualcomm.com> | 2021-03-19 14:53:45 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2021-03-21 03:15:58 -0700 |
| commit | 8e149080e4dbc8dc960f7dff425c66ae240f60de (patch) | |
| tree | a129b19571f388288f44445e2a9fe60ebd0b1de3 | |
| parent | c081e5409980055d2e6d76aff715c10e7e923f0a (diff) | |
| download | devicetree-8e149080e4dbc8dc960f7dff425c66ae240f60de.tar.gz | |
ARM: dts: msm: Add gcc-mdss clock node for QM215
Add gcc-mdss clock controller support for QM215 target.
Change-Id: Ie668845e436ff128cf01eefbfc96e3a734bf9061
| -rw-r--r-- | qcom/msm8917.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/qcom/msm8917.dtsi b/qcom/msm8917.dtsi index cdbed04b..4c20881b 100644 --- a/qcom/msm8917.dtsi +++ b/qcom/msm8917.dtsi @@ -585,7 +585,7 @@ }; gcc_mdss: qcom,gcc-mdss@1800000 { - compatible = "qcom,gcc-mdss-8917"; + compatible = "qcom,gcc-mdss-qm215"; reg = <0x1800000 0x80000>; clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>; |