diff options
author | Venkata Narendra Kumar Gutta <vgutta@quicinc.com> | 2019-04-24 12:36:05 -0700 |
---|---|---|
committer | Venkata Narendra Kumar Gutta <vgutta@quicinc.com> | 2019-05-02 16:41:24 -0700 |
commit | ed241f132720397b8abac31ca170a274ea6e54e5 (patch) | |
tree | 892aeadc1cc2fc0a47d982a533f8112d96866d37 /bindings/nds32 | |
parent | 1f62b25b429becfcc7d8608f389705b3e6ef0e20 (diff) | |
download | devicetree-ed241f132720397b8abac31ca170a274ea6e54e5.tar.gz |
dt-bindings: Add devicetree bindings to devicetree project
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of
'commit f3dd4aaeb34438c877ccd42f5a48ccd554dd765a (Merge
"platform: qpnp-revid: Add REVID support for PM7250B")' of
the kernel project.
Change-Id: I5e0ec0eae63ff9c071b2924bd84c5b20d3f6554d
Diffstat (limited to 'bindings/nds32')
-rw-r--r-- | bindings/nds32/andestech-boards | 40 | ||||
-rw-r--r-- | bindings/nds32/atl2c.txt | 28 | ||||
-rw-r--r-- | bindings/nds32/cpus.txt | 38 |
3 files changed, 106 insertions, 0 deletions
diff --git a/bindings/nds32/andestech-boards b/bindings/nds32/andestech-boards new file mode 100644 index 00000000..f5d75693 --- /dev/null +++ b/bindings/nds32/andestech-boards @@ -0,0 +1,40 @@ +Andestech(nds32) AE3XX Platform +----------------------------------------------------------------------------- +The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It +is composed of one Andestech(nds32) processor and AE3XX. + +Required properties (in root node): +- compatible = "andestech,ae3xx"; + +Example: +/dts-v1/; +/ { + compatible = "andestech,ae3xx"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; +}; + +Andestech(nds32) AG101P Platform +----------------------------------------------------------------------------- +AG101P is a generic SoC Platform IP that works with any of Andestech(nds32) +processors to provide a cost-effective and high performance solution for +majority of embedded systems in variety of application domains. Users may +simply attach their IP on one of the system buses together with certain glue +logics to complete a SoC solution for a specific application. With +comprehensive simulation and design environments, users may evaluate the +system performance of their applications and track bugs of their designs +efficiently. The optional hardware development platform further provides real +system environment for early prototyping and software/hardware co-development. + +Required properties (in root node): + compatible = "andestech,ag101p"; + +Example: +/dts-v1/; +/ { + compatible = "andestech,ag101p"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; +}; diff --git a/bindings/nds32/atl2c.txt b/bindings/nds32/atl2c.txt new file mode 100644 index 00000000..da8ab8e7 --- /dev/null +++ b/bindings/nds32/atl2c.txt @@ -0,0 +1,28 @@ +* Andestech L2 cache Controller + +The level-2 cache controller plays an important role in reducing memory latency +for high performance systems, such as thoese designs with AndesCore processors. +Level-2 cache controller in general enhances overall system performance +signigicantly and the system power consumption might be reduced as well by +reducing DRAM accesses. + +This binding specifies what properties must be available in the device tree +representation of an Andestech L2 cache controller. + +Required properties: + - compatible: + Usage: required + Value type: <string> + Definition: "andestech,atl2c" + - reg : Physical base address and size of cache controller's memory mapped + - cache-unified : Specifies the cache is a unified cache. + - cache-level : Should be set to 2 for a level 2 cache. + +* Example + + cache-controller@e0500000 { + compatible = "andestech,atl2c"; + reg = <0xe0500000 0x1000>; + cache-unified; + cache-level = <2>; + }; diff --git a/bindings/nds32/cpus.txt b/bindings/nds32/cpus.txt new file mode 100644 index 00000000..6f9e311b --- /dev/null +++ b/bindings/nds32/cpus.txt @@ -0,0 +1,38 @@ +* Andestech Processor Binding + +This binding specifies what properties must be available in the device tree +representation of a Andestech Processor Core, which is the root node in the +tree. + +Required properties: + + - compatible: + Usage: required + Value type: <string> + Definition: Should be "andestech,<core_name>", "andestech,nds32v3" as fallback. + Must contain "andestech,nds32v3" as the most generic value, in addition to + one of the following identifiers for a particular CPU core: + "andestech,n13" + "andestech,n15" + "andestech,d15" + "andestech,n10" + "andestech,d10" + - device_type + Usage: required + Value type: <string> + Definition: must be "cpu" + - reg: Contains CPU index. + - clock-frequency: Contains the clock frequency for CPU, in Hz. + +* Examples + +/ { + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + reg = <0x0>; + clock-frequency = <60000000> + }; + }; +}; |