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author | Venkata Narendra Kumar Gutta <vgutta@quicinc.com> | 2019-04-24 12:36:05 -0700 |
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committer | Venkata Narendra Kumar Gutta <vgutta@quicinc.com> | 2019-05-02 16:41:24 -0700 |
commit | ed241f132720397b8abac31ca170a274ea6e54e5 (patch) | |
tree | 892aeadc1cc2fc0a47d982a533f8112d96866d37 /bindings/openrisc | |
parent | 1f62b25b429becfcc7d8608f389705b3e6ef0e20 (diff) | |
download | devicetree-ed241f132720397b8abac31ca170a274ea6e54e5.tar.gz |
dt-bindings: Add devicetree bindings to devicetree project
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of
'commit f3dd4aaeb34438c877ccd42f5a48ccd554dd765a (Merge
"platform: qpnp-revid: Add REVID support for PM7250B")' of
the kernel project.
Change-Id: I5e0ec0eae63ff9c071b2924bd84c5b20d3f6554d
Diffstat (limited to 'bindings/openrisc')
-rw-r--r-- | bindings/openrisc/opencores/or1ksim.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/bindings/openrisc/opencores/or1ksim.txt b/bindings/openrisc/opencores/or1ksim.txt new file mode 100644 index 00000000..4950c794 --- /dev/null +++ b/bindings/openrisc/opencores/or1ksim.txt @@ -0,0 +1,39 @@ +OpenRISC Generic SoC +==================== + +Boards and FPGA SoC's which support the OpenRISC standard platform. The +platform essentially follows the conventions of the OpenRISC architecture +specification, however some aspects, such as the boot protocol have been defined +by the Linux port. + +Required properties +------------------- + - compatible: Must include "opencores,or1ksim" + +CPU nodes: +---------- +A "cpus" node is required. Required properties: + - #address-cells: Must be 1. + - #size-cells: Must be 0. +A CPU sub-node is also required for at least CPU 0. Since the topology may +be probed via CPS, it is not necessary to specify secondary CPUs. Required +properties: + - compatible: Must be "opencores,or1200-rtlsvn481". + - reg: CPU number. + - clock-frequency: The CPU clock frequency in Hz. +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + +Boot protocol +------------- +The bootloader may pass the following arguments to the kernel: + - r3: address of a flattened device-tree blob or 0x0. |