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| author | Vatsal Bucha <vbucha@qti.qualcomm.com> | 2019-09-26 14:36:49 +0530 |
|---|---|---|
| committer | Vatsal Bucha <vbucha@qti.qualcomm.com> | 2019-09-27 13:54:32 +0530 |
| commit | e1ee9f79d239f14e470b994412db539481493773 (patch) | |
| tree | 5bb9ccdf9cf652ef62e2277fff0d0a1758447b3c /bindings/pinctrl | |
| parent | b027e55304d08e9bbfab1f3b5042b9966b2f28f1 (diff) | |
| download | devicetree-e1ee9f79d239f14e470b994412db539481493773.tar.gz | |
ARM: dts: qcom: Add slew base table for lito v2
Add slew base table to enable tx data3 for lito v2.
Change-Id: Ic9723141b6977ef189fde385c47793805413c8fc
Diffstat (limited to 'bindings/pinctrl')
| -rw-r--r-- | bindings/pinctrl/qcom,lpi-pinctrl.txt | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/bindings/pinctrl/qcom,lpi-pinctrl.txt b/bindings/pinctrl/qcom,lpi-pinctrl.txt index 13f9628f..fd60bfb2 100644 --- a/bindings/pinctrl/qcom,lpi-pinctrl.txt +++ b/bindings/pinctrl/qcom,lpi-pinctrl.txt @@ -49,20 +49,11 @@ Following properties are for LPI GPIO controller device main node. position in bits in the slew register base for slew settings. -- #qcom,tx_data3_enabled: +- #qcom,lpi-slew-base-tbl: Usage: optional - Value type: <u32> - Definition: Check if gpio is present for swr tx3 line. - -- #qcom,tx_data3_addr: - Usage: optional - Value type: <u32> - Definition: Used to define address for tx data3 slew rate gpio. - -- #qcom,swr_tx_data3_val: - Usage: optional - Value type: <u32> - Definition: Used to enable tx data3 slew rate if present. + Value type: <u32-array> + Definition: Table points to physical address for corresponding + slew registers. Please refer to ../gpio/gpio.txt for general description of GPIO bindings. |