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| author | Archana Sriram <c_apsrir@qti.qualcomm.com> | 2021-06-24 16:30:07 +0530 |
|---|---|---|
| committer | Archana Sriram <c_apsrir@qti.qualcomm.com> | 2021-06-24 16:30:07 +0530 |
| commit | fbd324ee41a7196a47a69895d2ccdbdc8056f502 (patch) | |
| tree | 97e1c5a31cfd0e386968c89d266827904c7af0e8 /bindings | |
| parent | 43ebf4552c85798967ed48271635896f1a7a3433 (diff) | |
| download | devicetree-fbd324ee41a7196a47a69895d2ccdbdc8056f502.tar.gz | |
dt-bindings: adreno: Add property for multiple fuses based speed bin
This change adds documentation for GPU property
"qcom,gpu-speed-bin-vectors" which helps to add multiple fuses
based speed bin. This enables support for different GPU Fmax
frequencies based on speed bin value.
Change-Id: Ibbd405aa50ba296ce22a57cdf0fbfa020f63eaef
Diffstat (limited to 'bindings')
| -rw-r--r-- | bindings/gpu/adreno.txt | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 390b44c4..0858c6c0 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -140,6 +140,19 @@ Optional Properties: mask - mask for the relevant bits in the efuse register. shift - number of bits to right shift to get the speed bin value. + +- qcom,gpu-speed-bin-vectors: + GPU speed bin vectors property is the series of all the vectors + in format specified below. Values from individual fuses are read, + masked and shifted to form a value. At the end all fuse values + are ordered together to form final speed bin value. + <offset mask shift> + <offset mask shift> + < .. .. .. > + offset - offset of the efuse register from the base. + mask - mask for the relevant bits in the efuse register. + shift - number of bits to right shift. + - qcom,gpu-disable-fuse: GPU disable fuse <offset mask shift> offset - offset of the efuse register from the base. |