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| author | Shadab Naseem <snaseem@qti.qualcomm.com> | 2019-10-03 11:21:27 +0530 |
|---|---|---|
| committer | Shadab Naseem <snaseem@qti.qualcomm.com> | 2019-10-03 12:52:44 +0530 |
| commit | 50ac34ac675c79e1c8060d6fd9d4c9fe23841781 (patch) | |
| tree | 82280da5f96818b5f7a460b922547ca4c1094564 /qcom/bengal-gpu.dtsi | |
| parent | f701f554c26cf253090bbd44b8f200776ff16fab (diff) | |
| download | devicetree-50ac34ac675c79e1c8060d6fd9d4c9fe23841781.tar.gz | |
ARM: dts: msm: Add the phandle of crypto core for PIL's on Bengal
Add the phandle entry of bus master crypto core for PIL's like
(lpass, turing, mss, venus, gpu) for Bengal.
Also update Documentation for mas-crypto entry.
Change-Id: I535d523cd96bd82764e8b1875c31b52523f625c4
Diffstat (limited to 'qcom/bengal-gpu.dtsi')
| -rw-r--r-- | qcom/bengal-gpu.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/qcom/bengal-gpu.dtsi b/qcom/bengal-gpu.dtsi index ef21c5ff..58dfd07e 100644 --- a/qcom/bengal-gpu.dtsi +++ b/qcom/bengal-gpu.dtsi @@ -3,6 +3,7 @@ compatible = "qcom,pil-tz-generic"; qcom,pas-id = <13>; qcom,firmware-name = "a610_zap"; + qcom,mas-crypto = <&mas_crypto_c0>; }; gpu_opp_table: gpu-opp-table { |