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| author | Harshitha Sai Neelati <c_hsaine@qti.qualcomm.com> | 2020-12-07 21:41:47 +0530 |
|---|---|---|
| committer | Harshitha Sai Neelati <c_hsaine@qti.qualcomm.com> | 2020-12-07 21:48:42 +0530 |
| commit | 63aaf7ab7df03bf9947526c79a8a0364c9ceef09 (patch) | |
| tree | e172b05e0ab476c80f3b13a58de86c418d5986c8 /qcom/bengal-gpu.dtsi | |
| parent | 0ec154a07c51aeb8a418c02e59ce488afa98534f (diff) | |
| download | devicetree-63aaf7ab7df03bf9947526c79a8a0364c9ceef09.tar.gz | |
ARM: dts: msm: Add apb_pclk to GPU clock list for Bengal
KGSL needs to enable apb_pclk for QDSS register access.
Hence add apb_pclk to the GPU clock list for Bengal.
Change-Id: I26eb27340b845e0ff4df4032acb65a657668b18e
Diffstat (limited to 'qcom/bengal-gpu.dtsi')
| -rw-r--r-- | qcom/bengal-gpu.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/qcom/bengal-gpu.dtsi b/qcom/bengal-gpu.dtsi index 0797453a..b1082070 100644 --- a/qcom/bengal-gpu.dtsi +++ b/qcom/bengal-gpu.dtsi @@ -126,11 +126,12 @@ <&gpucc GPU_CC_AHB_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk", "rbbmtimer_clk", "iface_clk", "ahb_clk", "mem_clk", "gmu_clk", - "smmu_vote"; + "smmu_vote", "apb_pclk"; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; |