diff options
| author | qctecmdr <qctecmdr@localhost> | 2019-10-01 16:17:32 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2019-10-01 16:17:32 -0700 |
| commit | 0bc89fcbcff9d483cd86755c64be6ba0acf0e472 (patch) | |
| tree | c381eb19466a0b4457a5672d0fd699b9e231780f /qcom/kona-usb.dtsi | |
| parent | c8ce280a16cb5cae4abd01032cf2f46d269c91f6 (diff) | |
| parent | b4e4f15af1f05dcf36a7ea6a6afbe33d4f785a05 (diff) | |
| download | devicetree-0bc89fcbcff9d483cd86755c64be6ba0acf0e472.tar.gz | |
Merge "ARM: dts: msm: Update the QMP PHY init Sequence for Kona"
Diffstat (limited to 'qcom/kona-usb.dtsi')
| -rw-r--r-- | qcom/kona-usb.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/qcom/kona-usb.dtsi b/qcom/kona-usb.dtsi index cd237c42..68a69be1 100644 --- a/qcom/kona-usb.dtsi +++ b/qcom/kona-usb.dtsi @@ -231,13 +231,13 @@ USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0 - USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xFF 0 + USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0 USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0 - USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0B 0 - USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB3 0 + USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0 + USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0 USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0 USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0 @@ -274,13 +274,13 @@ USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x7F 0 - USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xFF 0 + USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x97 0 USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0 - USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0B 0 - USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB3 0 + USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0 + USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0 USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0 USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0 @@ -529,7 +529,7 @@ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 @@ -543,7 +543,7 @@ USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0 USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 - USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 |