diff options
| author | Hemant Kumar <hemantk@quicinc.com> | 2019-05-21 13:45:29 -0700 |
|---|---|---|
| committer | Hemant Kumar <hemantk@quicinc.com> | 2019-07-02 18:43:50 -0700 |
| commit | be64b4989b5460002680dbb8b310e1b30f69689a (patch) | |
| tree | 7440586d6d1caadd140724e17a39900e18126871 /qcom/kona-usb.dtsi | |
| parent | c6023b76be8ab114a0bb21f144ac356be4156d5f (diff) | |
| download | devicetree-be64b4989b5460002680dbb8b310e1b30f69689a.tar.gz | |
ARM: dts: msm: Add usb pipe clock source clk on kona
USB SS phy driver needs to toggle between bi_tcxo
and phy pipe clock as part of its CX collapse sequence,
add pipe_clk_src which would be set to parent as
ref_clk_src or pipe_clk.
Change-Id: I78624b559df51063761773606e6e636a65e740e4
Diffstat (limited to 'qcom/kona-usb.dtsi')
| -rw-r--r-- | qcom/kona-usb.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/qcom/kona-usb.dtsi b/qcom/kona-usb.dtsi index 50b12a96..c1c7b174 100644 --- a/qcom/kona-usb.dtsi +++ b/qcom/kona-usb.dtsi @@ -322,9 +322,12 @@ clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", "com_aux_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, @@ -573,10 +576,13 @@ clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, + <&clock_gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_SEC_CLKREF_EN>, <&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>, |