Commit label r00005.1b - ES1 0.0.005.1b

TRACKING-ID:8cd85703-ff04-47aa-9967-c43e5c9f377d

1 files changed, 0 insertions, 1199 deletions

diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi
deleted file mode 100755
index 3e3765e3..00000000
--- a/qcom/qcs405.dtsi
+++ /dev/null
@@ -1,1199 +0,0 @@
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
-#include <dt-bindings/clock/qcom,cmn-blk-pll.h>
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
-#include <dt-bindings/clock/qcom,rpmcc.h>
-#include <dt-bindings/interconnect/qcom,icc.h>
-#include <dt-bindings/interconnect/qcom,qcs405.h>
-#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
-#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
-
-/ {
-	model = "Qualcomm Technologies, Inc. QCS405";
-	compatible = "qcom,qcs405";
-	qcom,msm-id = <352 0x0>, <452 0x0>;
-	interrupt-parent = <&intc>;
-
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases: aliases {
-		serial0 = &blsp1_uart2_console;
-		sdhc0 = &sdhc_1;
-		sdhc1 = &sdhc_2;
-		pci-domain0 = &pcie0; /* PCIe0 domain */
-		qpic_nand1 = &qnand_1;
-	};
-
-	chosen {
-	};
-
-	memory { device_type = "memory"; reg = <0 0 0 0>; };
-
-	firmware: firmware {
-	};
-
-	reserved_mem: reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		removed_region0: removed_region@85900000 {
-			no-map;
-			reg = <0x0 0x85900000 0x0 0x600000>;
-		};
-
-		smem_region: smem@85f00000 {
-			no-map;
-			reg = <0x0 0x85f00000 0x0 0x200000>;
-		};
-
-		removed_region1: removed_region@86100000 {
-			no-map;
-			reg = <0x0 0x86100000 0x0 0x300000>;
-		};
-
-		wlan_fw_mem: wlan_fw_mem@86400000 {
-			no-map;
-			reg = <0x0 0x86400000 0x0 0x1000000>;
-		};
-
-		adsp_fw_mem: adsp_fw_mem@87400000 {
-			no-map;
-			reg = <0x0 0x87400000 0x0 0x1400000>;
-		};
-
-		cdsp_fw_mem: cdsp_fw_mem@88800000 {
-			no-map;
-			reg = <0x0 0x88800000 0x0 0x800000>;
-		};
-
-		wlan_msa_mem: wlan_msa_region@88E00000 {
-			no-map;
-			reg = <0x0 0x89000000 0x0 0x100000>;
-		};
-
-		secure_mem: secure_region {
-			status = "disabled";
-			compatible = "shared-dma-pool";
-			reusable;
-			alignment = <0 0x400000>;
-			size = <0 0x7000000>;
-		};
-
-		mdf_mem: mdf_region {
-			compatible = "shared-dma-pool";
-			alloc-ranges = <0 0x00000000 0 0xffffffff>;
-			reusable;
-			alignment = <0 0x400000>;
-			size = <0 0x800000>;
-		};
-
-		qseecom_mem: qseecom_region {
-			compatible = "shared-dma-pool";
-			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
-			reusable;
-			alignment = <0x0 0x400000>;
-			size = <0x0 0x1000000>;
-		};
-
-		qseecom_ta_mem: qseecom_ta_region {
-			compatible = "shared-dma-pool";
-			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
-			reusable;
-			alignment = <0x0 0x400000>;
-			size = <0x0 0x400000>;
-		};
-
-		adsp_mem: adsp_region {
-			compatible = "shared-dma-pool";
-			reusable;
-			alignment = <0 0x400000>;
-			size = <0 0x800000>;
-		};
-
-		dump_mem: mem_dump_region {
-			compatible = "shared-dma-pool";
-			reusable;
-			size = <0 0x400000>;
-		};
-		/* global autoconfigured region for contiguous allocations */
-		linux,cma {
-			compatible = "shared-dma-pool";
-			alloc-ranges = <0 0x00000000 0 0xffffffff>;
-			reusable;
-			alignment = <0 0x400000>;
-			size = <0 0x1000000>;
-			linux,cma-default;
-		};
-	};
-
-	soc: soc { };
-
-};
-#include "qcs405-ion.dtsi"
-&soc {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0 0 0 0xffffffff>;
-	compatible = "simple-bus";
-
-	intc: interrupt-controller@b000000 {
-		compatible = "qcom,msm-qgic2";
-		interrupt-controller;
-		interrupt-parent = <&intc>;
-		#interrupt-cells = <3>;
-		reg = <0x0b000000 0x1000>,
-		      <0x0b002000 0x1000>;
-	};
-
-	wakegic: wake-gic {
-		compatible = "qcom,mpm-gic-qcs405", "qcom,mpm";
-		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
-		reg = <0x601b8 0x1000>,
-			<0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
-		reg-names = "vmpm", "ipc";
-		qcom,num-mpm-irqs = <96>;
-		interrupt-controller;
-		interrupt-parent = <&intc>;
-		#interrupt-cells = <2>;
-	};
-
-	system_pm_rpm {
-		compatible = "qcom,system-pm-rpm";
-	};
-
-	arch_timer: timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-		clock-frequency = <19200000>;
-	};
-
-	timer@b120000 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		compatible = "arm,armv7-timer-mem";
-		reg = <0xb120000 0x1000>;
-		clock-frequency = <19200000>;
-
-		frame@b121000 {
-			frame-number = <0>;
-			interrupts = <0 8 0x4>,
-				     <0 7 0x4>;
-			reg = <0xb121000 0x1000>,
-			      <0xb122000 0x1000>;
-		};
-
-		frame@b123000 {
-			frame-number = <1>;
-			interrupts = <0 9 0x4>;
-			reg = <0xb123000 0x1000>;
-			status = "disabled";
-		};
-
-		frame@b124000 {
-			frame-number = <2>;
-			interrupts = <0 10 0x4>;
-			reg = <0xb124000 0x1000>;
-			status = "disabled";
-		};
-
-		frame@b125000 {
-			frame-number = <3>;
-			interrupts = <0 11 0x4>;
-			reg = <0xb125000 0x1000>;
-			status = "disabled";
-		};
-
-		frame@b126000 {
-			frame-number = <4>;
-			interrupts = <0 12 0x4>;
-			reg = <0xb126000 0x1000>;
-			status = "disabled";
-		};
-
-		frame@b127000 {
-			frame-number = <5>;
-			interrupts = <0 13 0x4>;
-			reg = <0xb127000 0x1000>;
-			status = "disabled";
-		};
-
-		frame@b128000 {
-			frame-number = <6>;
-			interrupts = <0 14 0x4>;
-			reg = <0xb128000 0x1000>;
-			status = "disabled";
-		};
-	};
-
-	clocks {
-		xo_board {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <19200000>;
-			clock-output-names = "xo_board";
-		};
-	};
-
-	restart@4ab000 {
-		compatible = "qcom,pshold";
-		reg = <0x4ab000 0x4>,
-			<0x193d100 0x4>;
-		reg-names = "pshold-base", "tcsr-boot-misc-detect";
-	};
-
-	qcom,msm-rtb {
-		compatible = "qcom,msm-rtb";
-		qcom,rtb-size = <0x100000>;
-	};
-
-	qcom,mpm2-sleep-counter@4a3000 {
-		compatible = "qcom,mpm2-sleep-counter";
-		reg = <0x4a3000 0x1000>;
-		clock-frequency = <32768>;
-	};
-
-	pil_scm_pas {
-		compatible = "qcom,pil-tz-scm-pas";
-		interconnects = <&pc_noc MASTER_CRYPTO_CORE0
-				&bimc SLAVE_EBI_CH0>;
-	};
-
-	rpmcc: qcom,rpmcc {
-		compatible = "qcom,rpmcc-qcs404";
-		#clock-cells = <1>;
-	};
-
-	gcc: clock-controller@1800000 {
-		compatible = "qcom,gcc-qcs404", "syscon";
-		reg = <0x1800000 0x80000>;
-		reg-names = "cc_base";
-		vdd_cx-supply = <&VDD_CX_LEVEL>;
-		vdd_sr_pll-supply = <&VDD_SR_PLL_LEVEL>;
-		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
-		clock-names = "bi_tcxo";
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	apsscc: clock-controller@0b011050 {
-		compatible = "qcom,qcs404-apsscc";
-		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
-			<&gcc GCC_GPLL0_AO_OUT_MAIN>;
-		clock-names = "bi_tcxo_ao", "gpll0_out_even";
-		reg = <0xb011050 0x16>, <0xb016000 0x34>;
-		reg-names = "apcs_cmd" , "apcs_pll";
-		cpu-vdd-supply = <&apc_vreg_corner>;
-		vdd_dig_ao-supply = <&pms405_s1_level_ao>;
-		vdd_hf_pll-supply = <&pms405_l5_ao>;
-		qcom,speed0-bin-v0 =
-			< 0         0>,
-			< 1094400000 1>,
-			< 1248000000 2>,
-			< 1401600000 3>;
-		#clock-cells = <1>;
-	};
-
-	cmn_blk_pll: qcom,cmn_blk_pll@2f780 {
-		compatible = "qcom,cmn_blk_pll";
-		reg = <0x2f780 0x4>;
-		reg-names = "cmn_blk";
-		clocks = <&gcc GCC_BIAS_PLL_MISC_RESET_CLK>,
-			<&gcc GCC_BIAS_PLL_AHB_CLK>,
-			<&gcc GCC_BIAS_PLL_AON_CLK>;
-		clock-names = "misc_reset_clk",
-			"ahb_clk",
-			"aon_clk";
-		resets = <&gcc GCC_BIAS_PLL_BCR>;
-		reset-names = "cmn_blk_pll_reset";
-		#clock-cells = <1>;
-	};
-
-	cpucc: syscon@b01101c {
-		compatible = "syscon";
-		reg = <0xb01101c 0x4>;
-	};
-
-	debugcc: debug-clock-controller@0 {
-		compatible = "qcom,qcs404-debugcc";
-		qcom,gcc = <&gcc>;
-		qcom,cpucc = <&cpucc>;
-		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
-		clock-names = "xo_clk_src";
-		#clock-cells = <1>;
-	};
-
-	bimc: interconnect@400000 {
-		reg = <0x400000 0x80000>;
-		compatible = "qcom,qcs405-bimc";
-		qcom,util-factor = <153>;
-		qcom,keepalive;
-		#interconnect-cells = <1>;
-		clock-names = "bus", "bus_a";
-		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
-			<&rpmcc RPM_SMD_BIMC_A_CLK>;
-	};
-
-	pc_noc: interconnect@500000 {
-		reg = <0x500000 0x15080>;
-		compatible = "qcom,qcs405-pcnoc";
-		qcom,keepalive;
-		#interconnect-cells = <1>;
-		clock-names = "bus", "bus_a";
-		clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
-			<&rpmcc RPM_SMD_PNOC_A_CLK>;
-	};
-
-	system_noc: interconnect@580000 {
-		reg = <0x580000 0x23080>;
-		compatible = "qcom,qcs405-snoc";
-		qcom,keepalive;
-		#interconnect-cells = <1>;
-		clock-names = "bus", "bus_a";
-		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
-			<&rpmcc RPM_SMD_SNOC_A_CLK>,
-			<&gcc GCC_SYS_NOC_USB3_CLK>;
-	};
-
-	qcom,sps {
-		compatible = "qcom,msm-sps-4k";
-		qcom,pipe-attr-ee;
-	};
-
-	spmi_bus: qcom,spmi@200f000 {
-		compatible = "qcom,spmi-pmic-arb";
-		reg = <0x200f000 0x1000>,
-			<0x2400000 0x800000>,
-			<0x2c00000 0x800000>,
-			<0x3800000 0x200000>,
-			<0x200a000 0x2100>;
-		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
-		interrupt-names = "periph_irq";
-		interrupts-extended = <&wakegic 62 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,ee = <0>;
-		qcom,channel = <0>;
-		#address-cells = <2>;
-		#size-cells = <0>;
-		interrupt-controller;
-		#interrupt-cells = <4>;
-		cell-index = <0>;
-	};
-
-	thermal_zones: thermal-zones {};
-
-	cpu-pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	blsp1_uart2_console: serial@78b1000 {
-		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-		reg = <0x078b1000 0x200>;
-		interrupts = <0 118 0>;
-		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-			<&gcc GCC_BLSP1_AHB_CLK>;
-		clock-names = "core", "iface";
-		pinctrl-names = "default";
-		pinctrl-0 = <&blsp1_uart2_default>;
-		status = "okay";
-	};
-
-	rpm_bus: qcom,rpm-smd {
-		compatible = "qcom,rpm-smd";
-		rpm-channel-name = "rpm_requests";
-		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-		rpm-channel-type = <15>; /* SMD_APPS_RPM */
-	};
-
-	qcom,msm-imem@8600000 {
-		compatible = "qcom,msm-imem";
-		reg = <0x08600000 0x1000>; /* Address and size of IMEM */
-		ranges = <0x0 0x08600000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		mem_dump_table@10 {
-			compatible = "qcom,msm-imem-mem_dump_table";
-			reg = <0x10 0x8>;
-		};
-
-		dload_type@18 {
-			compatible = "qcom,msm-imem-dload-type";
-			reg = <0x18 0x4>;
-		};
-
-		restart_reason@65c {
-			compatible = "qcom,msm-imem-restart_reason";
-			reg = <0x65c 0x4>;
-		};
-
-		boot_stats@6b0 {
-			compatible = "qcom,msm-imem-boot_stats";
-			reg = <0x6b0 0x20>;
-		};
-
-		pil@94c {
-			compatible = "qcom,msm-imem-pil";
-			reg = <0x94c 0xc8>;
-		};
-
-		diag_dload@c8 {
-			compatible = "qcom,msm-imem-diag-dload";
-			reg = <0xc8 0xc8>;
-		};
-
-		kaslr_offset@6d0 {
-			compatible = "qcom,msm-imem-kaslr_offset";
-			reg = <0x6d0 0xc>;
-		};
-	};
-
-	qcom,lpass@c000000 {
-		compatible = "qcom,pil-tz-generic";
-		reg = <0xc000000 0x00100>;
-
-		vdd_cx-supply = <&pms405_s2_level>;
-		qcom,proxy-reg-names = "vdd_cx";
-		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
-
-		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
-		clock-names = "xo";
-		qcom,proxy-clock-names = "xo";
-
-		qcom,pas-id = <1>;
-		qcom,complete-ramdump;
-		qcom,proxy-timeout-ms = <10000>;
-		qcom,smem-id = <423>;
-		qcom,sysmon-id = <1>;
-		qcom,ssctl-instance-id = <0x14>;
-		qcom,firmware-name = "adsp";
-
-		/* GPIO inputs from lpass */
-		interrupts-extended = <&intc 0 293 1>,
-				<&adsp_smp2p_in 0 0>,
-				<&adsp_smp2p_in 2 0>,
-				<&adsp_smp2p_in 1 0>,
-				<&adsp_smp2p_in 3 0>;
-
-		interrupt-names = "qcom,wdog",
-				"qcom,err-fatal",
-				"qcom,proxy-unvote",
-				"qcom,err-ready",
-				"qcom,stop-ack";
-		/* GPIO output to lpass */
-		qcom,smem-states = <&adsp_smp2p_out 0>;
-		qcom,smem-state-names = "qcom,force-stop";
-		memory-region = <&adsp_fw_mem>;
-	};
-
-	qcom,turing@800000 {
-		compatible = "qcom,pil-tz-generic";
-		reg = <0x800000 0x00100>;
-
-		vdd_cx-supply = <&pms405_s1_level>;
-		qcom,proxy-reg-names = "vdd_cx";
-		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
-
-		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
-		clock-names = "xo";
-		qcom,proxy-clock-names = "xo";
-
-		qcom,pas-id = <18>;
-		/*qcom,mas-crypto = <&mas_crypto>;*/
-		qcom,complete-ramdump;
-		qcom,proxy-timeout-ms = <10000>;
-		qcom,smem-id = <601>;
-		qcom,sysmon-id = <7>;
-		qcom,ssctl-instance-id = <0x17>;
-		qcom,firmware-name = "cdsp";
-		memory-region = <&cdsp_fw_mem>;
-
-		/* GPIO inputs from turing */
-		interrupts-extended = <&intc 0 229 1>,
-				<&cdsp_smp2p_in 0 0>,
-				<&cdsp_smp2p_in 2 0>,
-				<&cdsp_smp2p_in 1 0>,
-				<&cdsp_smp2p_in 3 0>;
-
-		interrupt-names = "qcom,wdog",
-				"qcom,err-fatal",
-				"qcom,proxy-unvote",
-				"qcom,err-ready",
-				"qcom,stop-ack";
-		/* GPIO output to turing */
-		qcom,smem-states = <&cdsp_smp2p_out 0>;
-		qcom,smem-state-names = "qcom,force-stop";
-		status = "ok";
-	};
-
-	tcsr_mutex_block: syscon@1905000 {
-		compatible = "syscon";
-		reg = <0x1905000 0x20000>;
-	};
-
-	tcsr_mutex: hwlock {
-		compatible = "qcom,tcsr-mutex";
-		syscon = <&tcsr_mutex_block 0 0x1000>;
-		#hwlock-cells = <1>;
-	};
-
-	smem: qcom,smem {
-		compatible = "qcom,smem";
-		memory-region = <&smem_region>;
-		hwlocks = <&tcsr_mutex 3>;
-	};
-
-	apcs: syscon@b011008 {
-		compatible = "syscon";
-		reg = <0xb011008 0x4>;
-	};
-
-	apcs_glb: mailbox@b011000 {
-		compatible = "qcom,msm8916-apcs-kpss-global";
-		reg = <0xb011000 0x10>;
-
-		#mbox-cells = <1>;
-	};
-
-	smp2p_sleepstate: qcom,smp2p_sleepstate {
-		compatible = "qcom,smp2p-sleepstate";
-		qcom,smem-states = <&sleepstate_smp2p_out 0>;
-	};
-
-	rpm_msg_ram: memory@60000 {
-		compatible = "qcom,rpm-msg-ram";
-		reg = <0x60000 0x6000>;
-	};
-
-	rpm-glink {
-		compatible = "qcom,glink-rpm";
-		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-		qcom,rpm-msg-ram = <&rpm_msg_ram>;
-		mboxes = <&apcs_glb 0>;
-
-		qcom,rpm_glink_ssr {
-			qcom,glink-channels = "glink_ssr";
-			qcom,notify-edges = <&glink_adsp>,
-					    <&glink_cdsp>;
-		};
-	};
-
-	qcom,msm-cdsp-loader {
-		compatible = "qcom,cdsp-loader";
-		qcom,proc-img-to-load = "cdsp";
-	};
-
-	adsp_loader: qcom,msm-adsp-loader {
-		status = "ok";
-		compatible = "qcom,adsp-loader";
-		qcom,adsp-state = <0>;
-	};
-
-	qcom,glink {
-		compatible = "qcom,glink";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		glink_adsp: adsp {
-			qcom,remote-pid = <2>;
-			transport = "smem";
-			mboxes = <&apcs_glb 8>;
-			mbox-names = "adsp_smem";
-			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
-
-			label = "adsp";
-			qcom,glink-label = "lpass";
-
-			qcom,adsp_qrtr {
-				qcom,glink-channels = "IPCRTR";
-				qcom,intents = <0x800  5
-						0x2000 3
-						0x4400 2>;
-			};
-
-			qcom,apr_tal_rpmsg {
-				qcom,glink-channels = "apr_audio_svc";
-				qcom,intents = <0x200 20>;
-			};
-
-			qcom,msm_fastrpc_rpmsg {
-				compatible = "qcom,msm-fastrpc-rpmsg";
-				qcom,glink-channels = "fastrpcglink-apps-dsp";
-				qcom,intents = <0x64 64>;
-			};
-
-			qcom,adsp_glink_ssr {
-				qcom,glink-channels = "glink_ssr";
-				qcom,notify-edges = <&glink_cdsp>;
-			};
-		};
-
-		glink_cdsp: cdsp {
-			qcom,remote-pid = <5>;
-			transport = "smem";
-			mboxes = <&apcs_glb 12>;
-			mbox-names = "cdsp_smem";
-			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
-
-			label = "cdsp";
-			qcom,glink-label = "cdsp";
-
-			qcom,cdsp_qrtr {
-				qcom,glink-channels = "IPCRTR";
-				qcom,intents = <0x800  5
-						0x2000 3
-						0x4400 2>;
-			};
-
-			qcom,msm_fastrpc_rpmsg {
-				compatible = "qcom,msm-fastrpc-rpmsg";
-				qcom,glink-channels = "fastrpcglink-apps-dsp";
-				qcom,intents = <0x64 64>;
-			};
-
-			qcom,cdsp_glink_ssr {
-				qcom,glink-channels = "glink_ssr";
-				qcom,notify-edges = <&glink_adsp>;
-			};
-		};
-	};
-
-	qcom,glinkpkt {
-		compatible = "qcom,glinkpkt";
-
-		qcom,glinkpkt-apr-apps2 {
-			qcom,glinkpkt-edge = "adsp";
-			qcom,glinkpkt-ch-name = "apr_apps2";
-			qcom,glinkpkt-dev-name = "apr_apps2";
-		};
-	};
-
-	qcom,smp2p-adsp {
-		compatible = "qcom,smp2p";
-		qcom,smem = <443>, <429>;
-		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
-		qcom,ipc = <&apcs 0 10>;
-		qcom,local-pid = <0>;
-		qcom,remote-pid = <2>;
-
-		adsp_smp2p_out: master-kernel {
-			qcom,entry-name = "master-kernel";
-			#qcom,smem-state-cells = <1>;
-		};
-
-		adsp_smp2p_in: slave-kernel {
-			qcom,entry-name = "slave-kernel";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		sleepstate_smp2p_out: sleepstate-out {
-			qcom,entry-name = "sleepstate";
-			#qcom,smem-state-cells = <1>;
-		};
-	};
-
-	qcom,smp2p-cdsp {
-		compatible = "qcom,smp2p";
-		qcom,smem = <94>, <432>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
-		qcom,ipc = <&apcs 0 14>;
-		qcom,local-pid = <0>;
-		qcom,remote-pid = <5>;
-
-		cdsp_smp2p_out: master-kernel {
-			qcom,entry-name = "master-kernel";
-			#qcom,smem-state-cells = <1>;
-		};
-
-		cdsp_smp2p_in: slave-kernel {
-			qcom,entry-name = "slave-kernel";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-	};
-
-	wdog: qcom,wdt@b017000 {
-		compatible = "qcom,msm-watchdog";
-		reg = <0xb017000 0x1000>;
-		reg-names = "wdt-base";
-		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,bark-time = <11000>;
-		qcom,pet-time = <9744>;
-		qcom,ipi-ping;
-		qcom,wakeup-enable;
-		status = "okay";
-	};
-	qcom_crypto: qcrypto@720000 {
-		 compatible = "qcom,qcrypto";
-		 reg = <0x720000 0x20000>,
-		     <0x704000 0x20000>;
-		 reg-names = "crypto-base","crypto-bam-base";
-		 interrupts = <0 206 0>;
-		 qcom,bam-pipe-pair = <2>;
-		 qcom,ce-hw-instance = <0>;
-		 qcom,ce-device = <0>;
-		 qcom,bam-ee = <0>;
-		 qcom,ce-hw-shared;
-		 qcom,clk-mgmt-sus-res;
-		 qcom,msm-bus,name = "qcrypto-noc";
-		 qcom,msm-bus,num-cases = <2>;
-		 qcom,msm-bus,num-paths = <1>;
-		 qcom,msm-bus,vectors-KBps =
-			 <55 512 0 0>,
-			 <55 512 393600 393600>;
-		clock-names =
-			"core_clk_src", "core_clk",
-			"iface_clk", "bus_clk";
-		clocks = <&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>;
-		 qcom,use-sw-aes-cbc-ecb-ctr-algo;
-		 qcom,use-sw-aes-xts-algo;
-		 qcom,use-sw-aes-ccm-algo;
-		 qcom,use-sw-ahash-algo;
-		 qcom,use-sw-hmac-algo;
-		 qcom,use-sw-aead-algo;
-		 qcom,smmu-s1-enable;
-		 iommus = <&apps_smmu 0x0064 0x0011>,
-			<&apps_smmu 0x0074 0x0011>;
-	};
-
-	qcom_cedev: qcedev@720000 {
-		compatible = "qcom,qcedev";
-		reg = <0x720000 0x20000>,
-		    <0x704000 0x20000>;
-		reg-names = "crypto-base","crypto-bam-base";
-		interrupts = <0 206 0>;
-		qcom,ce-device = <0>;
-		qcom,bam-ee = <0>;
-		qcom,ce-hw-shared;
-		qcom,clk-mgmt-sus-res;
-		qcom,bam-pipe-pair = <3>;
-		qcom,ce-hw-instance = <0>;
-		qcom,msm-bus,name = "qcedev-noc";
-		qcom,msm-bus,num-cases = <2>;
-		qcom,msm-bus,num-paths = <1>;
-		qcom,msm-bus,vectors-KBps =
-			<55 512 0 0>,
-			<55 512 393600 393600>;
-		clock-names =
-			"core_clk_src", "core_clk",
-			"iface_clk", "bus_clk";
-		clocks =
-			<&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>,
-			<&rpmcc RPM_SMD_CE1_CLK>;
-		qcom,smmu-s1-enable;
-		iommus = <&apps_smmu 0x0066 0x0011>,
-				<&apps_smmu 0x0076 0x0011>;
-	};
-
-	qtee_shmbridge {
-		compatible = "qcom,tee-shared-memory-bridge";
-	};
-
-	qcom_qseecom: qseecom@85900000 {
-		compatible = "qcom,qseecom";
-		reg = <0x85900000 0x500000>;
-		reg-names = "secapp-region";
-		memory-region = <&qseecom_mem>;
-		qcom,hlos-num-ce-hw-instances = <1>;
-		qcom,hlos-ce-hw-instance = <0>;
-		qcom,qsee-ce-hw-instance = <0>;
-		qcom,disk-encrypt-pipe-pair = <2>;
-		qcom,support-fde;
-		qcom,fde-key-size;
-		qcom,no-clock-support;
-		qcom,appsbl-qseecom-support;
-		qcom,msm-bus,name = "qseecom-noc";
-		qcom,msm-bus,num-cases = <4>;
-		qcom,msm-bus,num-paths = <1>;
-		qcom,ce-opp-freq = <171430000>;
-		qcom,qsee-reentrancy-support = <2>;
-	};
-
-	qcom_smcinvoke: smcinvoke@85900000 {
-		compatible = "qcom,smcinvoke";
-		reg = <0x85900000 0x500000>;
-		reg-names = "secapp-region";
-	};
-
-	qcom_rng: qrng@e3000 {
-		compatible = "qcom,msm-rng";
-		reg = <0xe3000 0x1000>;
-		qcom,msm-rng-iface-clk;
-		qcom,no-qrng-config;
-		qcom,msm-bus,name = "msm-rng-noc";
-		qcom,msm-bus,num-cases = <2>;
-		qcom,msm-bus,num-paths = <1>;
-		qcom,msm-bus,vectors-KBps =
-			<1 618 0 0>,            /* No vote */
-			<1 618 0 800>;          /* 100 MB/s */
-		clocks = <&gcc GCC_PRNG_AHB_CLK>;
-		clock-names = "km_clk_src";
-	};
-
-	qcom_tzlog: tz-log@8600720 {
-		compatible = "qcom,tz-log";
-		reg = <0x08600720 0x2000>;
-	};
-
-	mem_dump {
-		compatible = "qcom,mem-dump";
-		memory-region = <&dump_mem>;
-
-		rpm_sw_dump {
-			qcom,dump-size = <0x28000>;
-			qcom,dump-id = <0xea>;
-		};
-
-		pmic_dump {
-			qcom,dump-size = <0x10000>;
-			qcom,dump-id = <0xe4>;
-		};
-
-		misc_data_dump {
-			qcom,dump-size = <0x1000>;
-			qcom,dump-id = <0xe8>;
-		};
-
-		vsense_dump {
-			qcom,dump-size = <0x10000>;
-			qcom,dump-id = <0xe9>;
-		};
-
-		tmc_etf_dump {
-			qcom,dump-size = <0x10000>;
-			qcom,dump-id = <0xf0>;
-		};
-
-		tmc_etr_reg_dump {
-			qcom,dump-size = <0x1000>;
-			qcom,dump-id = <0x100>;
-		};
-
-		tmc_etf_reg_dump {
-			qcom,dump-size = <0x1000>;
-			qcom,dump-id = <0x101>;
-		};
-
-		l2_dump1 {
-			qcom,dump-size = <0x0>;
-			qcom,dump-id = <0xC1>;
-		};
-
-		l1_i_cache100 {
-			qcom,dump-size = <0x8800>;
-			qcom,dump-id = <0x60>;
-		};
-
-		l1_i_cache101 {
-			qcom,dump-size = <0x8800>;
-			qcom,dump-id = <0x61>;
-		};
-
-		l1_i_cache102 {
-			qcom,dump-size = <0x8800>;
-			qcom,dump-id = <0x62>;
-		};
-
-		l1_i_cache103 {
-			qcom,dump-size = <0x8800>;
-			qcom,dump-id = <0x63>;
-		};
-
-		l1_d_cache100 {
-			qcom,dump-size = <0x9000>;
-			qcom,dump-id = <0x80>;
-		};
-
-		l1_d_cache101 {
-			qcom,dump-size = <0x9000>;
-			qcom,dump-id = <0x81>;
-		};
-
-		l1_d_cache102 {
-			qcom,dump-size = <0x9000>;
-			qcom,dump-id = <0x82>;
-		};
-
-		l1_d_cache103 {
-			qcom,dump-size = <0x9000>;
-			qcom,dump-id = <0x83>;
-		};
-	};
-
-	sdhc_1: sdhci@7804000 {
-		compatible = "qcom,sdhci-msm-v5";
-		reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
-		reg-names = "hc_mem", "cqhci_mem";
-
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "hc_irq", "pwr_irq";
-
-		iommus = <&apps_smmu 0x80 0x0>;
-		qcom,iommu-dma = "bypass";
-
-		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
-			<&gcc GCC_SDCC1_APPS_CLK>,
-			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
-		clock-names = "iface", "core", "ice_core";
-
-		qcom,ice-clk-rates = <266666667 160000000>;
-
-		qcom,devfreq,freq-table = <50000000 200000000>;
-		qcom,scaling-lower-bus-speed-mode = "DDR52";
-
-		bus-width = <8>;
-		qcom,restore-after-cx-collapse;
-		supports-cqe;
-
-		mmc-ddr-1_8v;
-		mmc-hs200-1_8v;
-		mmc-hs400-1_8v;
-		mmc-hs400-enhanced-strobe;
-		non-removable;
-
-		interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
-		interconnect-names = "sdhc-ddr";
-
-		qcom,msm-bus,name = "sdhc1";
-		qcom,msm-bus,num-cases = <8>;
-		qcom,msm-bus,num-paths = <1>;
-		qcom,msm-bus,vectors-KBps =
-			/* No vote */
-			<0 0>,
-			/* 400 KB/s*/
-			<1046 3200>,
-			/* 25 MB/s */
-			<65360 200000>,
-			/* 50 MB/s */
-			<130718 400000>,
-			/* 100 MB/s */
-			<130718 400000>,
-			/* 200 MB/s */
-			<261438 800000>,
-			/* 400 MB/s */
-			<261438 2718822>,
-			/* Max. bandwidth */
-			<1338562 4096000>;
-		qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
-			100000000 200000000 400000000 4294967295>;
-
-		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
-		qcom,dll-hsr-list = <0x000F6400 0x0 0x0 0x0 0x80240874>;
-
-		/* VDD external regulator is enabled/disabled by pms405_l6 */
-		vdd-io-supply = <&pms405_l6>;
-		qcom,vdd-io-always-on;
-		qcom,vdd-io-lpm-sup;
-		qcom,vdd-io-voltage-level = <1800000 1800000>;
-		qcom,vdd-io-current-level = <0 325000>;
-
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&sdc1_on>;
-		pinctrl-1 = <&sdc1_off>;
-
-		status = "ok";
-
-		qos0 {
-			mask = <0x0f>;
-			vote = <13>;
-		};
-	};
-
-	sdhc_2: sdhci@7844000 {
-		compatible = "qcom,sdhci-msm-v5";
-		reg = <0x7844000 0x1000>;
-		reg-names = "hc_mem";
-
-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "hc_irq", "pwr_irq";
-
-		iommus = <&apps_smmu 0xa0 0x0>;
-		qcom,iommu-dma = "bypass";
-
-		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
-			<&gcc GCC_SDCC2_APPS_CLK>;
-		clock-names = "iface", "core";
-
-		qcom,devfreq,freq-table = <50000000 200000000>;
-
-		bus-width = <4>;
-
-		interconnects = <&pc_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>;
-		interconnect-names = "sdhc-ddr";
-
-		qcom,msm-bus,name = "sdhc2";
-		qcom,msm-bus,num-cases = <7>;
-		qcom,msm-bus,num-paths = <1>;
-		qcom,msm-bus,vectors-KBps =
-			/* No vote */
-			<0 0>,
-			/* 400 KB/s*/
-			<1046 3200>,
-			/* 25 MB/s */
-			<65360 200000>,
-			/* 50 MB/s */
-			<130718 400000>,
-			/* 100 MB/s */
-			<261438 800000>,
-			/* 200 MB/s */
-			<261438 800000>,
-			/* Max. bandwidth */
-			<1338562 4096000>;
-		qcom,bus-bw-vectors-bps = <0 4000000 25000000 50000000
-		100750000 200000000 4294967295>;
-
-		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
-		qcom,dll-hsr-list = <0x000F6400 0x0 0x0 0x0 0x00040874>;
-
-		/* VDD is an external regulator eLDO5 */
-		vdd-io-supply = <&pms405_l11>;
-		qcom,vdd-io-voltage-level = <1800000 2950000>;
-		qcom,vdd-io-current-level = <0 24200>;
-
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&sdc2_on>;
-		pinctrl-1 = <&sdc2_off>;
-
-		status = "ok";
-
-		qos0 {
-			mask = <0x0f>;
-			vote = <13>;
-		};
-	};
-
-	qnand_1: nand@4c0000 {
-		compatible = "qcom,msm-nand";
-		reg = <0x004c0000 0x1000>,
-		      <0x004c4000 0x1a000>;
-		reg-names = "nand_phys", "bam_phys";
-		qcom,reg-adjustment-offset = <0x4000>;
-
-		interrupts = <0 49 0>;
-		interrupt-names = "bam_irq";
-
-		interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>;
-		interconnect-names = "nand-ddr";
-		qcom,msm-bus,name = "qpic_nand";
-		qcom,msm-bus,num-cases = <2>;
-		qcom,msm-bus,num-paths = <1>;
-
-		qcom,msm-bus,vectors-KBps =
-			<0 0>,
-			/* Voting for max b/w on PNOC bus for now */
-			<400000 400000>;
-
-		clock-names = "core_clk";
-		clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
-
-		status = "disabled";
-	};
-
-	msm_cpufreq: qcom,msm-cpufreq {
-		compatible = "qcom,msm-cpufreq";
-		clock-names = "cpu0_clk";
-		clocks = <&apsscc APCS_MUX_CLK>;
-
-		qcom,cpufreq-table =
-			 < 1094400 >,
-			 < 1248000 >,
-			 < 1401600 >;
-	};
-
-	ddr_bw_opp_table: ddr-bw-opp-table {
-		compatible = "operating-points-v2";
-		BW_OPP_ENTRY( 297, 8); /* 2265 MB/s */
-		BW_OPP_ENTRY( 595, 8); /* 4539 MB/s */
-		BW_OPP_ENTRY( 710, 8); /* 5416 MB/s */
-	};
-
-	cpubw: qcom,cpubw {
-		compatible = "qcom,devfreq-icc";
-		governor = "performance";
-		interconnects = <&bimc MASTER_AMPSS_M0
-				&bimc SLAVE_EBI_CH0>;
-		qcom,active-only;
-		operating-points-v2 = <&ddr_bw_opp_table>;
-	};
-
-	cpu_bwmon: qcom,cpu-bwmon {
-		compatible = "qcom,bimc-bwmon2";
-		reg = <0x408000 0x300>, <0x401000 0x200>;
-		reg-names = "base", "global_base";
-		interrupts = <0 183 4>;
-		qcom,mport = <0>;
-		qcom,target-dev = <&cpubw>;
-	};
-
-	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
-		compatible = "qcom,devfreq-icc";
-		governor = "compute";
-		interconnects = <&bimc MASTER_AMPSS_M0
-				&bimc SLAVE_EBI_CH0>;
-		qcom,active-only;
-		operating-points-v2 = <&ddr_bw_opp_table>;
-		status = "ok";
-	};
-
-	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
-		compatible = "qcom,arm-memlat-cpugrp";
-		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
-
-		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
-			compatible = "qcom,arm-compute-mon";
-			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
-			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
-			qcom,core-dev-table =
-				< 1094400 MHZ_TO_MBPS( 297, 8) >,
-				< 1248000 MHZ_TO_MBPS( 597, 8) >,
-				< 1401600 MHZ_TO_MBPS( 710, 8) >;
-		};
-	};
-};
-
-&firmware {
-	scm {
-		compatible = "qcom,scm";
-	};
-};
-
-#include "qcs405-pinctrl.dtsi"
-#include "qcs405-pm.dtsi"
-#include "qcs405-cpu.dtsi"
-#include "pms405-rpm-regulator.dtsi"
-#include "qcs405-regulator.dtsi"
-#include "qcs405-ion.dtsi"
-#include "qcs405-gdsc.dtsi"
-#include "msm-arm-smmu-qcs405.dtsi"
-#include "pms405.dtsi"
-#include "qcs405-thermal.dtsi"
-#include "qcs405-pcie.dtsi"
-#include "qcs405-usb.dtsi"
-#include "qcs405-blsp.dtsi"
-
-&gdsc_mdss {
-	status = "ok";
-};
-
-&gdsc_oxili_gx {
-	status = "ok";
-};