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author | QC Publisher <qcpublisher@qti.qualcomm.com> | 2021-11-15 17:38:42 -0800 |
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committer | Andrew Evans <andrewevans@google.com> | 2022-02-15 14:56:20 -0800 |
commit | 64ceabbe9f67bb1111bd838e3fe3e2cec069fad4 (patch) | |
tree | 54059832688e7490f2fcbfdc58f41d0c4fee03ab /qcom/sa410m-usb.dtsi | |
parent | ae3d046330003c3bea902480d8f0b523970a9b9a (diff) | |
download | devicetree-64ceabbe9f67bb1111bd838e3fe3e2cec069fad4.tar.gz |
Commit label r00100.1 - ES3 0.0.100.1
TRACKING-ID:abf84bf7-a84d-4dce-b5ff-27ddc33fe0cb
Diffstat (limited to 'qcom/sa410m-usb.dtsi')
-rwxr-xr-x | qcom/sa410m-usb.dtsi | 159 |
1 files changed, 159 insertions, 0 deletions
diff --git a/qcom/sa410m-usb.dtsi b/qcom/sa410m-usb.dtsi new file mode 100755 index 00000000..4ab9290e --- /dev/null +++ b/qcom/sa410m-usb.dtsi @@ -0,0 +1,159 @@ +#include <dt-bindings/clock/qcom,gcc-scuba.h> +#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h> + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0120 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 90 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,bus-suspend-enable; + snps,usb2-gadget-lpm-disable; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@1613000 { + compatible = "qcom,qusb2phy"; + reg = <0x01613000 0x180>, + <0x003cb250 0x4>, + <0x01b40258 0x4>, + <0x01612000 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "eud_enable_reg"; + + vdd-supply = <&pm2250_l12>; + vdda18-supply = <&pm2250_l13>; + vdda33-supply = <&pm2250_l21>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; |