diff options
| author | Archana Sriram <c_apsrir@qti.qualcomm.com> | 2021-01-08 15:06:40 +0530 |
|---|---|---|
| committer | Archana Sriram <c_apsrir@qti.qualcomm.com> | 2021-02-23 23:21:39 +0530 |
| commit | 3e514a912cd6499b048fed972330ffe2cb670cf7 (patch) | |
| tree | 0c7027d6d3416ecd991e7b36faab4323d62a8639 /qcom | |
| parent | a77287c06a8a169fb2ac8926684659de5b94aa20 (diff) | |
| download | devicetree-3e514a912cd6499b048fed972330ffe2cb670cf7.tar.gz | |
ARM: dts: qcom: Update bw table and iommu properties on msm8937 GPU
Following changes are made:
1. Update gpu_bw_tbl in terms of operating point for gpubw.
2. GPU takes care of creating desired dma mapping by itself,
so disable iommu-dma.
3. Remove unsupported properties "qcom,protect" and
"qcom,micro-mmu-control".
Change-Id: Ic2d6616ee8097ac6d7e608b6be36808080a126a2
Diffstat (limited to 'qcom')
| -rw-r--r-- | qcom/msm8937-gpu.dtsi | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/qcom/msm8937-gpu.dtsi b/qcom/msm8937-gpu.dtsi index 0571cc1a..5a2716bf 100644 --- a/qcom/msm8937-gpu.dtsi +++ b/qcom/msm8937-gpu.dtsi @@ -4,28 +4,42 @@ compatible = "qcom,kgsl-busmon"; }; + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + + opp-201 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 201 MHz */ + + opp-422 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 422 MHz */ + + opp-557 { opp-hz = /bits/ 64 < 2124 >; }; /* 3. 557 MHz */ + + opp-768 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 768 MHz */ + + opp-1075 { opp-hz = /bits/ 64 < 4101 >; }; /* 5. 1075 MHz */ + + opp-1113 { opp-hz = /bits/ 64 < 4248 >; }; /* 6. 1113 MHz */ + + opp-1401 { opp-hz = /bits/ 64 < 5346 >; }; /* 7. 1401 MHz */ + + opp-1497 { opp-hz = /bits/ 64 < 5712 >; }; /* 8. 1497 MHz */ + + opp-1613 { opp-hz = /bits/ 64 < 6152 >; }; /* 9. 1613 MHz */ + + opp-1843 { opp-hz = /bits/ 64 < 7031 >; }; /* 10. 1843 MHz */ + }; + gpubw: qcom,gpubw { compatible = "qcom,devbw"; governor = "bw_vbif"; qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; /* * active-only flag is used while registering the bus * governor.It helps release the bus vote when the CPU * subsystem is inactiv3 */ qcom,active-only; - qcom,bw-tbl = - < 0 >, /* off */ - < 769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */ - < 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */ - < 2124 >, /* 3. DDR:278.40 MHz BIMC: 139.20 MHz */ - < 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */ - < 4101 >, /* 5. DDR:537.60 MHz BIMC: 268.80 MHz */ - < 4248 >, /* 6. DDR:556.80 MHz BIMC: 278.40 MHz */ - < 5346 >, /* 7. DDR:662.40 MHz BIMC: 331.20 MHz */ - < 5712 >, /* 8. DDR:748.80 MHz BIMC: 374.40 MHz */ - < 6152 >, /* 9. DDR:806.40 MHz BIMC: 403.20 MHz */ - < 7031 >; /* 10. DDR:921.60 MHz BIMC: 460.80 MHz */ }; msm_gpu: qcom,kgsl-3d0@1c00000 { @@ -214,8 +228,6 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x1c40000 0x10000>; - qcom,protect = <0x40000 0x10000>; - qcom,micro-mmu-control = <0x6000>; clocks = <&gcc GCC_OXILI_AHB_CLK>, <&gcc GCC_BIMC_GFX_CLK>; @@ -228,6 +240,7 @@ compatible = "qcom,smmu-kgsl-cb"; label = "gfx3d_user"; iommus = <&kgsl_smmu 0>; + qcom,iommu-dma = "disabled"; qcom,gpu-offset = <0x48000>; }; }; |