diff options
| author | QC Publisher <qcpublisher@qti.qualcomm.com> | 2021-11-15 17:38:42 -0800 |
|---|---|---|
| committer | Andrew Evans <andrewevans@google.com> | 2022-02-15 14:56:20 -0800 |
| commit | 64ceabbe9f67bb1111bd838e3fe3e2cec069fad4 (patch) | |
| tree | 54059832688e7490f2fcbfdc58f41d0c4fee03ab /qcom | |
| parent | ae3d046330003c3bea902480d8f0b523970a9b9a (diff) | |
| download | devicetree-64ceabbe9f67bb1111bd838e3fe3e2cec069fad4.tar.gz | |
Commit label r00100.1 - ES3 0.0.100.1
TRACKING-ID:abf84bf7-a84d-4dce-b5ff-27ddc33fe0cb
Diffstat (limited to 'qcom')
81 files changed, 1940 insertions, 315 deletions
diff --git a/qcom/Makefile b/qcom/Makefile index 6305b269..abf0748f 100755 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -282,11 +282,11 @@ dtbo-$(CONFIG_ARCH_MONACO) += \ monaco-wdp-v1.1-overlay.dtbo monaco-rumi-overlay.dtbo-base := monaco.dtb -monaco-standalone-idp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb -monaco-standalone-idp-v2-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb -monaco-standalone-idp-v3-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb -monacop-standalone-idp-v1-overlay.dtbo-base := monaco-1gb.dtb -monaco-standalone-atp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb +monaco-standalone-idp-v1-overlay.dtbo-base := monaco-standalone.dtb monacop-standalone.dtb +monaco-standalone-idp-v2-overlay.dtbo-base := monaco-standalone.dtb monacop-standalone.dtb +monaco-standalone-idp-v3-overlay.dtbo-base := monaco-standalone.dtb monacop-standalone.dtb +monacop-standalone-idp-v1-overlay.dtbo-base := monaco-standalone.dtb +monaco-standalone-atp-v1-overlay.dtbo-base := monaco-standalone.dtb monacop-standalone.dtb monaco-idp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v2-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v3-overlay.dtbo-base := monaco.dtb monacop.dtb @@ -294,7 +294,7 @@ monaco-idp-v1.1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v2.1-overlay.dtbo-base := monaco.dtb monaco-idp-v3.1-overlay.dtbo-base := monaco.dtb monaco-atp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb -monaco-standalone-wdp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb +monaco-standalone-wdp-v1-overlay.dtbo-base := monaco-standalone.dtb monacop-standalone.dtb monaco-wdp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-wdp-v1.1-overlay.dtbo-base := monaco.dtb monacop.dtb diff --git a/qcom/direwolf-audio.dtsi b/qcom/direwolf-audio.dtsi index 93d92ff5..e1e59c1a 100755 --- a/qcom/direwolf-audio.dtsi +++ b/qcom/direwolf-audio.dtsi @@ -1125,9 +1125,12 @@ "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -1203,7 +1206,10 @@ asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/direwolf-gdsc.dtsi b/qcom/direwolf-gdsc.dtsi index ed4b03e8..5081c048 100755 --- a/qcom/direwolf-gdsc.dtsi +++ b/qcom/direwolf-gdsc.dtsi @@ -23,6 +23,12 @@ status = "disabled"; }; + gcc_pcie_0_gdsc: qcom,gdsc@1a9004 { + compatible = "regulator-fixed"; + regulator-name = "gcc_pcie_0_gdsc"; + status = "disabled"; + }; + gcc_pcie_0_tunnel_gdsc: qcom,gdsc@1a4004 { compatible = "qcom,gdsc"; reg = <0x1a4004 0x4>; @@ -35,6 +41,12 @@ status = "disabled"; }; + gcc_pcie_1_gdsc: qcom,gdsc@177004 { + compatible = "regulator-fixed"; + regulator-name = "gcc_pcie_1_gdsc"; + status = "disabled"; + }; + gcc_pcie_1_tunnel_gdsc: qcom,gdsc@18d004 { compatible = "qcom,gdsc"; reg = <0x18d004 0x4>; @@ -123,6 +135,12 @@ status = "disabled"; }; + gcc_usb20_prim_gdsc: qcom,gdsc@11c004 { + compatible = "regulator-fixed"; + regulator-name = "gcc_usb20_prim_gdsc"; + status = "disabled"; + }; + gcc_usb30_mp_gdsc: qcom,gdsc@1ab004 { compatible = "qcom,gdsc"; reg = <0x1ab004 0x4>; diff --git a/qcom/direwolf-ivi-v2.dtsi b/qcom/direwolf-ivi-v2.dtsi index c1cfdc42..6a2881ba 100755 --- a/qcom/direwolf-ivi-v2.dtsi +++ b/qcom/direwolf-ivi-v2.dtsi @@ -7,3 +7,11 @@ compatible = "qcom,direwolf-ivi", "qcom,direwolf"; qcom,msm-id = <460 0x20000>; }; + +&gpucc { + compatible = "qcom,direwolf-gpucc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,direwolf-videocc-v2", "syscon"; +}; diff --git a/qcom/direwolf-vm-audio.dtsi b/qcom/direwolf-vm-audio.dtsi index 82610cc3..56bc00b7 100755 --- a/qcom/direwolf-vm-audio.dtsi +++ b/qcom/direwolf-vm-audio.dtsi @@ -1092,9 +1092,12 @@ "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -1170,7 +1173,10 @@ asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi index 5330dc99..185d9311 100755 --- a/qcom/direwolf-vm-lv.dtsi +++ b/qcom/direwolf-vm-lv.dtsi @@ -67,3 +67,12 @@ &usb2_phy5 { status = "okay"; }; + +&ufs2phy_mem { + status = "okay"; +}; + +&ufshc2_mem { + status = "okay"; +}; + diff --git a/qcom/direwolf-vm-ufs.dtsi b/qcom/direwolf-vm-ufs.dtsi new file mode 100755 index 00000000..bdc633a2 --- /dev/null +++ b/qcom/direwolf-vm-ufs.dtsi @@ -0,0 +1,190 @@ +®ulator { + L8G0: pm8540_g0_l8: regulator-pm8540_g0-l8 { + regulator-name = "ldog8"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + }; + + L3G0: pm8540_g0_l3: regulator-pm8540_g0-l3 { + regulator-name = "ldog3"; + regulator-min-microvolt = <1130000>; + regulator-max-microvolt = <1260000>; + }; + + gcc_ufs_card_gdsc: gcc_ufs_card_gdsc { + regulator-name = "gcc_ufs_card_gdsc"; + }; + + L10C0: pm8540_c0_l10: regulator-pm8540_c0-l10 { + regulator-name = "ldoc10"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2960000>; + }; + + L3C0: pm8540_c0_l3: regulator-pm8540_c0-l3 { + regulator-name = "ldoc3"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; +}; + +&soc { + aliases { + ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */ + }; + + ufs2phy_mem: ufsphy_mem@1da7000 { + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + + reg = <0x1da7000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + vdda-phy-supply = <&L8G0>; + vdda-pll-supply = <&L3G0>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk", + "ref_clk_parent"; + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>; + resets = <&ufshc2_mem 0>; + status = "disabled"; + }; + + ufshc2_mem: ufshc@1da4000 { + compatible = "qcom,ufshc"; + reg = <0x1da4000 0x3000>, + <0x1da8000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs2phy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + vdd-hba-supply = <&gcc_ufs_card_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L10C0>; + vcc-voltage-level = <2504000 2504000>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L3C0>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L3C0>; + qcom,vddp-ref-clk-max-microamp = <100>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_UFS_CARD_AHB_CLK>, + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_CARD_ICE_CORE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_CARD_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + secondary-storage; + status = "disabled"; + }; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index cabf6936..5551e507 100755 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -14,17 +14,6 @@ pci-domain3 = &pcie3; /* PCIe3 domain */ pci-domain4 = &pcie4; /* PCIe4 domain */ }; - - firmware:firmware { - android { - /delete-property/ boot_devices; - fstab { - vendor { - fsmgr_flags = "wait"; - }; - }; - }; - }; }; &soc { @@ -190,10 +179,6 @@ clock-names = "km_clk_src"; }; - cpu_pmu: cpu-pmu { - compatible = "arm,armv8-pmuv3"; - }; - qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; /*Boolean property to disable shmbridge*/ @@ -496,6 +481,7 @@ #include "direwolf-vm-usb.dtsi" #include "direwolf-vm-pcie.dtsi" #include "direwolf-cnss.dtsi" +#include "direwolf-vm-ufs.dtsi" &qupv3_0 { /delete-property/ qcom,msm-bus,num-paths; @@ -511,3 +497,7 @@ /delete-property/ qcom,msm-bus,num-paths; /delete-property/ qcom,msm-bus,vectors-bus-ids; }; + +&cpu_pmu { + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/qcom/holi-audio.dtsi b/qcom/holi-audio.dtsi index 4014574b..a0c2b967 100755 --- a/qcom/holi-audio.dtsi +++ b/qcom/holi-audio.dtsi @@ -153,8 +153,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -181,6 +183,8 @@ <&rx_cdc_dma_7_rx>,<&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 4909413f..3be69a50 100755 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -1,6 +1,7 @@ #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/iio/qti_power_supply_iio.h> +#include <dt-bindings/clock/qcom,rpmcc.h> #include "pm6350.dtsi" #include "pm7250b.dtsi" @@ -192,6 +193,17 @@ qcom,hw-settle-time = <200>; }; }; + + pm6150l_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6150l_div_clk1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + status = "disabled"; + }; }; }; diff --git a/qcom/lahaina-audio.dtsi b/qcom/lahaina-audio.dtsi index c891c458..86444648 100755 --- a/qcom/lahaina-audio.dtsi +++ b/qcom/lahaina-audio.dtsi @@ -112,9 +112,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -149,6 +153,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 09f3e780..ac72c22b 100755 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -1,3 +1,9 @@ +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,camcc-lemans.h> +#include <dt-bindings/clock/qcom,dispcc-lemans.h> +#include <dt-bindings/clock/qcom,gcc-lemans.h> +#include <dt-bindings/clock/qcom,gpucc-lemans.h> +#include <dt-bindings/clock/qcom,videocc-lemans.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -286,4 +292,334 @@ status = "disabled"; }; }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + clock-output-names = "bi_tcxo"; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <1>; + clocks = <&xo_board>; + clock-output-names = "bi_tcxo_ao"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_phy_aux_clk: pcie_phy_aux_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_phy_aux_clk"; + #clock-cells = <0>; + }; + + ufs_card_rx_symbol_0_clk: ufs_card_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_card_rx_symbol_1_clk: ufs_card_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_card_tx_symbol_0_clk: ufs_card_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_card_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_sec_pipe_clk: usb3_phy_wrapper_gcc_usb30_sec_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk"; + #clock-cells = <0>; + }; + }; + + rpmhcc: qcom,rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc0_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc1: clock-controller@22100000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc1_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + +#include "direwolf-gdsc.dtsi" + +&cam_cc_titan_top_gdsc { + compatible = "regulator-fixed"; + reg = <0xadf31bc 0x4>; + status = "ok"; +}; + +&disp0_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + reg = <0xaf09000 0x4>; + status = "ok"; +}; + +&disp0_cc_mdss_core_int2_gdsc { + compatible = "regulator-fixed"; + reg = <0xaf0d000 0x4>; + status = "ok"; +}; + +&disp1_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + reg = <0x22109000 0x4>; + status = "ok"; +}; + +&disp1_cc_mdss_core_int2_gdsc { + compatible = "regulator-fixed"; + reg = <0x2210d000 0x4>; + status = "ok"; +}; + +&gcc_emac0_gdsc { + compatible = "regulator-fixed"; + reg = <0x1b6004 0x4>; + status = "ok"; +}; + +&gcc_emac1_gdsc { + compatible = "regulator-fixed"; + reg = <0x1b4004 0x4>; + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + status = "ok"; +}; + +&gcc_ufs_card_gdsc { + compatible = "regulator-fixed"; + reg = <0x181004 0x4>; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + compatible = "regulator-fixed"; + reg = <0x183004 0x4>; + status = "ok"; +}; + +&gcc_usb20_prim_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + compatible = "regulator-fixed"; + reg = <0x11b004 0x4>; + status = "ok"; +}; + +&gcc_usb30_sec_gdsc { + compatible = "regulator-fixed"; + reg = <0x12f004 0x4>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d050 0x4>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d058 0x4>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d054 0x4>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d06c 0x4>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + compatible = "regulator-fixed"; + reg = <0x17d05c 0x4>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d060 0x4>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu2_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d090 0x4>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu3_gdsc { + compatible = "regulator-fixed"; + reg = <0x18d0a4 0x4>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc_hw_ctrl { + compatible = "syscon"; + reg = <0x3d9953c 0x4>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + compatible = "regulator-fixed"; + reg = <0x3d99108 0x4>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + compatible = "regulator-fixed"; + reg = <0x3d9905c 0x4>; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + compatible = "regulator-fixed"; + reg = <0xabf809c 0x4>; + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + compatible = "regulator-fixed"; + reg = <0xabf804c 0x4>; + status = "ok"; +}; + +&video_cc_mvs1_gdsc { + compatible = "regulator-fixed"; + reg = <0xabf80c0 0x4>; + status = "ok"; +}; + +&video_cc_mvs1c_gdsc { + compatible = "regulator-fixed"; + reg = <0xabf8074 0x4>; + status = "ok"; }; diff --git a/qcom/monaco-1gb.dts b/qcom/monaco-1gb.dts deleted file mode 100755 index 96af2949..00000000 --- a/qcom/monaco-1gb.dts +++ /dev/null @@ -1,9 +0,0 @@ -/dts-v1/; - -#include "monaco-1gb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Monaco 1 GB SoC "; - compatible = "qcom,monaco"; - qcom,board-id = <0 0x300>; -}; diff --git a/qcom/monaco-1gb.dtsi b/qcom/monaco-1gb.dtsi deleted file mode 100755 index 7c26c724..00000000 --- a/qcom/monaco-1gb.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -#include "monaco.dtsi" - -/ { - reserved-memory { - /delete-node/deepsleep_region@45700000; - }; -}; - -&removed_region { - reg = <0x0 0x61000000 0x0 0x0B00000>; -}; diff --git a/qcom/monaco-atp-v1-overlay.dts b/qcom/monaco-atp-v1-overlay.dts index acea30f5..5329fc12 100755 --- a/qcom/monaco-atp-v1-overlay.dts +++ b/qcom/monaco-atp-v1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-atp-v1.dtsi" +#include "monaco-slate-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco ATP V1.0"; diff --git a/qcom/monaco-camera-v1.1.dtsi b/qcom/monaco-camera-v1.1.dtsi new file mode 100755 index 00000000..08f68058 --- /dev/null +++ b/qcom/monaco-camera-v1.1.dtsi @@ -0,0 +1,8 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-monaco.h> +#include <dt-bindings/interconnect/qcom,monaco.h> +#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> +#include "camera/monaco-camera.dtsi" +#include "camera/monaco-camera-sensor-idp.dtsi" + + diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi index f643efea..2d5226a7 100755 --- a/qcom/monaco-idp-v1-common.dtsi +++ b/qcom/monaco-idp-v1-common.dtsi @@ -2,9 +2,8 @@ #include "monaco-haptics-fifo-data.dtsi" &dsi_rm69090_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_nolab_amoled>; qcom,platform-reset-gpio = <&pm5100_gpios 2 0>; - qcom,platform-reset-gpio-always-on; qcom,platform-en-gpio = <&pm5100_gpios 1 0>; }; diff --git a/qcom/monaco-idp-v1-overlay.dts b/qcom/monaco-idp-v1-overlay.dts index 2d46bdbd..d75494c7 100755 --- a/qcom/monaco-idp-v1-overlay.dts +++ b/qcom/monaco-idp-v1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-idp-v1.dtsi" +#include "monaco-slate-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco IDP V1.0"; diff --git a/qcom/monaco-idp-v1.1-overlay.dts b/qcom/monaco-idp-v1.1-overlay.dts index 42a50cb6..ad26d489 100755 --- a/qcom/monaco-idp-v1.1-overlay.dts +++ b/qcom/monaco-idp-v1.1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-idp-v1.1.dtsi" +#include "monaco-slate-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco Aon IDP V1.1"; diff --git a/qcom/monaco-idp-v1.1.dtsi b/qcom/monaco-idp-v1.1.dtsi index 9c1f29e7..2ae9cb82 100755 --- a/qcom/monaco-idp-v1.1.dtsi +++ b/qcom/monaco-idp-v1.1.dtsi @@ -1,9 +1,4 @@ -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/qcom,gcc-monaco.h> -#include <dt-bindings/interconnect/qcom,monaco.h> -#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> -#include "camera/monaco-camera.dtsi" -#include "camera/monaco-camera-sensor-idp.dtsi" +#include "monaco-camera-v1.1.dtsi" #include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index 6aa7602c..bff6b46b 100755 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -1,8 +1,8 @@ #include "monaco-idp-v1-common.dtsi" #include "slate.dtsi" -#include "monaco-slate-audio-overlay.dtsi" #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h> #include <dt-bindings/iio/qti_power_supply_iio.h> +#include <dt-bindings/clock/qcom,rpmcc.h> &sdhc_1 { status = "ok"; @@ -32,6 +32,10 @@ }; }; +&icnss { + qcom,is_slate_rfa = <1>; +}; + &qupv3_se5_4uart { status = "ok"; }; @@ -66,3 +70,35 @@ }; }; }; + +&pm5100_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio4"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&qupv3_se0_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 7 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&pm5100_gpios 4 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "LNBBCLK3"; + interrupts = <7 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK3_PIN>; + clock-names = "ref_clk"; + }; +}; diff --git a/qcom/monaco-idp-v2-overlay.dts b/qcom/monaco-idp-v2-overlay.dts index 24f7976e..644f3a5e 100755 --- a/qcom/monaco-idp-v2-overlay.dts +++ b/qcom/monaco-idp-v2-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-idp-v2.dtsi" +#include "monaco-slate-amic-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco IDP V2.0"; diff --git a/qcom/monaco-idp-v2.1-overlay.dts b/qcom/monaco-idp-v2.1-overlay.dts index bfa936d1..12613af3 100755 --- a/qcom/monaco-idp-v2.1-overlay.dts +++ b/qcom/monaco-idp-v2.1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-idp-v2.1.dtsi" +#include "monaco-slate-amic-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco Aon IDP V2.1"; diff --git a/qcom/monaco-idp-v3-overlay.dts b/qcom/monaco-idp-v3-overlay.dts index 8dd05c6e..47e79913 100755 --- a/qcom/monaco-idp-v3-overlay.dts +++ b/qcom/monaco-idp-v3-overlay.dts @@ -2,7 +2,7 @@ /plugin/; #include "monaco-idp-v3.dtsi" - +#include "monaco-slate-wsa-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco IDP V3.0"; qcom,board-id = <0x030022 0x0>; diff --git a/qcom/monaco-idp-v3.1-overlay.dts b/qcom/monaco-idp-v3.1-overlay.dts index 95617ef8..dd132c90 100755 --- a/qcom/monaco-idp-v3.1-overlay.dts +++ b/qcom/monaco-idp-v3.1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-idp-v3.1.dtsi" +#include "monaco-slate-wsa-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco Aon IDP V3.1"; diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi index fcedc97a..24c37805 100755 --- a/qcom/monaco-pmic.dtsi +++ b/qcom/monaco-pmic.dtsi @@ -17,7 +17,7 @@ sde_dsi_active: sde_dsi_active { pinconf { pins = "gpio1", "gpio2"; - function = "PMIC_GPIO_FUNC_NORMAL"; + function = "normal"; qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; bias-disable; output-high; @@ -27,7 +27,7 @@ sde_dsi_suspend: sde_dsi_suspend { pinconf { pins = "gpio1", "gpio2"; - function = "PMIC_GPIO_FUNC_NORMAL"; + function = "normal"; qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; bias-pull-down; output-low; diff --git a/qcom/monaco-slate-audio-overlay.dtsi b/qcom/monaco-slate-audio-overlay.dtsi index 36bbdf3d..080e4d76 100755 --- a/qcom/monaco-slate-audio-overlay.dtsi +++ b/qcom/monaco-slate-audio-overlay.dtsi @@ -13,5 +13,5 @@ asoc-codec-names = "cc_codec"; qcom,quat-mi2s-gpios = <&cc_quat_mi2s_gpios>; qcom,pri-mi2s-gpios = <&cc_pri_mi2s_gpios>; - qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>, <&audio_cc_ipc_platform>, <&cc_codec>; }; diff --git a/qcom/monaco-standalone-atp-v1.dts b/qcom/monaco-standalone-atp-v1.dts index 86a39057..458ad616 100755 --- a/qcom/monaco-standalone-atp-v1.dts +++ b/qcom/monaco-standalone-atp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" #include "monaco-standalone-atp-v1.dtsi" / { diff --git a/qcom/monaco-standalone-idp-v1.dts b/qcom/monaco-standalone-idp-v1.dts index 82389ca5..d5e81502 100755 --- a/qcom/monaco-standalone-idp-v1.dts +++ b/qcom/monaco-standalone-idp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" #include "monaco-standalone-idp-v1.dtsi" / { diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index 6cd284d9..0f55fa6f 100755 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -62,13 +62,21 @@ qcom,battery-data = <&monaco_batterydata>; #io-channel-cells = <1>; io-channels = <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>, - <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>; + <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>, + <&pm5100_charger PSY_IIO_CHARGE_DONE>, + <&pm5100_charger PSY_IIO_RECHARGE_SOC>, + <&pm5100_charger PSY_IIO_FORCE_RECHARGE>, + <&pm5100_charger PSY_IIO_SYS_SOC>; io-channel-names = "batt-temp", - "batt-id"; + "batt-id", + "charge_done", + "recharge_soc", + "force_recharge", + "sys_soc"; qcom,vbat-cutoff-mv = <3100>; - qcom,ibat-cutoff-ma = <150>; + qcom,ibat-cutoff-ma = <10>; qcom,vph-min-mv = <2500>; - qcom,iterm-ma = <100>; + qcom,iterm-ma = <20>; }; &pm5100_charger { diff --git a/qcom/monaco-standalone-idp-v2.dts b/qcom/monaco-standalone-idp-v2.dts index 29115945..0a036163 100755 --- a/qcom/monaco-standalone-idp-v2.dts +++ b/qcom/monaco-standalone-idp-v2.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" #include "monaco-standalone-idp-v2.dtsi" / { diff --git a/qcom/monaco-standalone-idp-v3.dts b/qcom/monaco-standalone-idp-v3.dts index 4eeccc2b..67f6c84c 100755 --- a/qcom/monaco-standalone-idp-v3.dts +++ b/qcom/monaco-standalone-idp-v3.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" #include "monaco-standalone-idp-v3.dtsi" / { diff --git a/qcom/monaco-standalone-wdp-v1.dts b/qcom/monaco-standalone-wdp-v1.dts index d9e1c068..38fcfed0 100755 --- a/qcom/monaco-standalone-wdp-v1.dts +++ b/qcom/monaco-standalone-wdp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" #include "monaco-standalone-wdp-v1.dtsi" / { diff --git a/qcom/monaco-standalone.dts b/qcom/monaco-standalone.dts new file mode 100755 index 00000000..e1a96ed9 --- /dev/null +++ b/qcom/monaco-standalone.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "monaco-standalone.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco SoC "; + compatible = "qcom,monaco"; + qcom,board-id = <0 0x1>; +}; diff --git a/qcom/monaco-standalone.dtsi b/qcom/monaco-standalone.dtsi new file mode 100755 index 00000000..79a11e94 --- /dev/null +++ b/qcom/monaco-standalone.dtsi @@ -0,0 +1,15 @@ +#include "monaco.dtsi" + +/ { + reserved-memory { + /delete-node/oda_region@45700000; + }; +}; + +&removed_region { + reg = <0x0 0x60e00000 0x0 0x01100000>; +}; + +&xbl_aop_mem { + reg = <0x0 0x45e00000 0x0 0x110000>; +}; diff --git a/qcom/monaco-wdp-v1-overlay.dts b/qcom/monaco-wdp-v1-overlay.dts index f146b0b7..a8ccb59a 100755 --- a/qcom/monaco-wdp-v1-overlay.dts +++ b/qcom/monaco-wdp-v1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-wdp-v1.dtsi" +#include "monaco-slate-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco WDP V1.0"; diff --git a/qcom/monaco-wdp-v1.1-overlay.dts b/qcom/monaco-wdp-v1.1-overlay.dts index b8036d66..c7586341 100755 --- a/qcom/monaco-wdp-v1.1-overlay.dts +++ b/qcom/monaco-wdp-v1.1-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include "monaco-wdp-v1.1.dtsi" +#include "monaco-slate-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco WDP V1.1"; diff --git a/qcom/monaco-wdp-v1.1.dtsi b/qcom/monaco-wdp-v1.1.dtsi index c41375f6..fd2d3400 100755 --- a/qcom/monaco-wdp-v1.1.dtsi +++ b/qcom/monaco-wdp-v1.1.dtsi @@ -1,2 +1,2 @@ -#include "monaco-idp-v1.1.dtsi" -#include "monaco-wdp.dtsi" +#include "monaco-camera-v1.1.dtsi" +#include "monaco-wdp-v1.dtsi" diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi index 3473a563..f02b4f40 100755 --- a/qcom/monaco-wdp-v1.dtsi +++ b/qcom/monaco-wdp-v1.dtsi @@ -1,2 +1,12 @@ #include "monaco-idp-v1.dtsi" #include "monaco-wdp.dtsi" + +&dsi_rm6d030_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_nolab_amoled>; + qcom,platform-reset-gpio = <&pm5100_gpios 2 0>; + qcom,platform-en-gpio = <&pm5100_gpios 1 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_rm6d030_amoled_cmd>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 166939dd..88188d53 100755 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -167,9 +167,14 @@ #size-cells = <2>; ranges; - deepsleep_region: deepsleep_region@45700000 { + oda_region: oda_region@45700000 { no-map; - reg = <0x0 0x45700000 0x0 0x400000>; + reg = <0x0 0x45700000 0x0 0x300000>; + }; + + deepsleep_region: deepsleep_region@45A00000 { + no-map; + reg = <0x0 0x45A00000 0x0 0x100000>; }; hyp_region: hyp_region@45B00000 { @@ -179,7 +184,7 @@ xbl_aop_mem: xbl_aop_mem@45e00000 { no-map; - reg = <0x0 0x45e00000 0x0 0x110000>; + reg = <0x0 0x45e00000 0x0 0x11A000>; }; sec_apps_mem: sec_apps_region@45fff000 { @@ -852,13 +857,15 @@ <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 9 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", - "qcom,stop-ack"; + "qcom,stop-ack", + "qcom,dsentry-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -895,14 +902,16 @@ <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 3 0>, - <&modem_smp2p_in 7 0>; + <&modem_smp2p_in 7 0>, + <&modem_smp2p_in 9 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", - "qcom,shutdown-ack"; + "qcom,shutdown-ack", + "qcom,dsentry-ack"; /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; @@ -933,12 +942,12 @@ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; qcom,iommu-geometry = <0xa0000000 0x10010000>; vdd-cx-mx-supply = <&L8A>; - qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-cx-mx-config = <640000 640000 1>; vdd-1.8-xo-supply = <&L14A>; vdd-1.3-rfa-supply = <&L13A>; - qcom,vdd-1.3-rfa-config = <1304000 1304000>; + qcom,vdd-1.3-rfa-config = <1304000 1304000 1>; vdd-3.3-ch0-supply = <&L26A>; - qcom,vdd-3.3-ch0-config = <3304000 3304000>; + qcom,vdd-3.3-ch0-config = <3304000 3304000 1>; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; @@ -1061,16 +1070,16 @@ ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ /* Low SVS */ - /* BW_OPP_ENTRY( 300, 4); */ /* 1144 MB/s */ /* Low SVS */ - /* BW_OPP_ENTRY( 451, 4); */ /* 1720 MB/s */ /* Low SVS */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ /* Low SVS */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ /* Low SVS */ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ /* Low SVS */ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ /* Low SVS */ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ /* SVS */ BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ /* SVS */ BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ /* SVS */ - /* BW_OPP_ENTRY( 1555, 4); */ /* 5931 MB/s */ /* Nominal */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ /* Nominal */ BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ /* Nominal */ - /* BW_OPP_ENTRY( 2092, 4); */ /* 7980 MB/s */ /* Turbo */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ /* Turbo */ }; cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { @@ -1900,6 +1909,7 @@ qcom,msm-adsprpc-mem { qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + qcom,restore-after-cx-collapse; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -2187,7 +2197,7 @@ qcom,msm-adsprpc-mem { parade,core { parade,name = "pt_core"; - parade,irq_gpio = <&tlmm 13 0x00>; + parade,irq_gpio = <&tlmm 13 0x2008>; parade,rst_gpio = <&tlmm 12 0x00>; parade,hid_desc_register = <1>; /* @@ -2201,11 +2211,14 @@ qcom,msm-adsprpc-mem { */ parade,flags = <6>; /* PT_CORE_EWG_NONE */ - parade,easy_wakeup_gesture = <0>; + parade,easy_wakeup_gesture = <1>; /* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/ parade,config_dut_generation = <1>; /* 0:False 1:True*/ parade,watchdog_force_stop = <0>; + panel = <&dsi_rm69090_amoled_cmd + &dsi_rm69090_amoled_vid + &dsi_rm6d030_amoled_cmd>; /* * PT_PANEL_ID_DISABLE = 0x00 * PT_PANEL_ID_BY_BL = 0x01 diff --git a/qcom/monacop-1gb.dts b/qcom/monacop-1gb.dts deleted file mode 100755 index 75c194e1..00000000 --- a/qcom/monacop-1gb.dts +++ /dev/null @@ -1,9 +0,0 @@ -/dts-v1/; - -#include "monacop-1gb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MonacoP 1GB SoC"; - compatible = "qcom,monacop"; - qcom,board-id = <0 0x300>; -}; diff --git a/qcom/monacop-standalone-atp-v1.dts b/qcom/monacop-standalone-atp-v1.dts index f9487ae0..7e04dd90 100755 --- a/qcom/monacop-standalone-atp-v1.dts +++ b/qcom/monacop-standalone-atp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monacop-1gb.dtsi" +#include "monacop-standalone.dtsi" #include "monaco-standalone-atp-v1.dtsi" / { diff --git a/qcom/monacop-standalone-idp-v1.dts b/qcom/monacop-standalone-idp-v1.dts index 299beb67..8fbb8631 100755 --- a/qcom/monacop-standalone-idp-v1.dts +++ b/qcom/monacop-standalone-idp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monacop-1gb.dtsi" +#include "monacop-standalone.dtsi" #include "monaco-standalone-idp-v1.dtsi" / { diff --git a/qcom/monacop-standalone-idp-v2.dts b/qcom/monacop-standalone-idp-v2.dts index 3d225a4a..241b8963 100755 --- a/qcom/monacop-standalone-idp-v2.dts +++ b/qcom/monacop-standalone-idp-v2.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monacop-1gb.dtsi" +#include "monacop-standalone.dtsi" #include "monaco-standalone-idp-v2.dtsi" / { diff --git a/qcom/monacop-standalone-idp-v3.dts b/qcom/monacop-standalone-idp-v3.dts index 87825579..8dd1428f 100755 --- a/qcom/monacop-standalone-idp-v3.dts +++ b/qcom/monacop-standalone-idp-v3.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monacop-1gb.dtsi" +#include "monacop-standalone.dtsi" #include "monaco-standalone-idp-v3.dtsi" / { diff --git a/qcom/monacop-standalone-wdp-v1.dts b/qcom/monacop-standalone-wdp-v1.dts index dd3bdd64..feef1ab2 100755 --- a/qcom/monacop-standalone-wdp-v1.dts +++ b/qcom/monacop-standalone-wdp-v1.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "monacop-1gb.dtsi" +#include "monacop-standalone.dtsi" #include "monaco-standalone-wdp-v1.dtsi" / { diff --git a/qcom/monacop-standalone.dts b/qcom/monacop-standalone.dts new file mode 100755 index 00000000..954206fb --- /dev/null +++ b/qcom/monacop-standalone.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "monacop-standalone.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MonacoP SoC"; + compatible = "qcom,monacop"; + qcom,board-id = <0 1>; +}; diff --git a/qcom/monacop-1gb.dtsi b/qcom/monacop-standalone.dtsi index eb34fbc7..b2b69b8d 100755 --- a/qcom/monacop-1gb.dtsi +++ b/qcom/monacop-standalone.dtsi @@ -1,4 +1,4 @@ -#include "monaco-1gb.dtsi" +#include "monaco-standalone.dtsi" / { model = "Qualcomm Technologies, Inc. MonacoP"; diff --git a/qcom/monacop.dtsi b/qcom/monacop.dtsi index cb40c32a..3bdf63d1 100755 --- a/qcom/monacop.dtsi +++ b/qcom/monacop.dtsi @@ -15,27 +15,3 @@ &ipa_hw { status = "disabled"; }; - -&pil_modem_mem { - reg = <0x0 0x4ab00000 0x0 0x3600000>; -}; - -&pil_video_mem { - reg = <0x0 0x4E100000 0x0 0x500000>; -}; - -&pil_adsp_mem { - reg = <0x0 0x4E600000 0x0 0x1900000>; -}; - -&pil_ipa_fw_mem { - reg = <0x0 0x4FF00000 0x0 0x10000>; -}; - -&pil_ipa_gsi_mem { - reg = <0x0 0x4FF10000 0x0 0x5000>; -}; - -&pil_gpu_mem { - reg = <0x0 0x4FF15000 0x0 0x2000>; -}; diff --git a/qcom/msm-audio-lpass.dtsi b/qcom/msm-audio-lpass.dtsi index 2b4eb0ef..a8e23ba3 100755 --- a/qcom/msm-audio-lpass.dtsi +++ b/qcom/msm-audio-lpass.dtsi @@ -91,46 +91,76 @@ msm_dai_mi2s: qcom,msm-dai-mi2s { compatible = "qcom,msm-dai-mi2s"; - dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + dai_mi2s0_rx: qcom,msm-dai-q6-mi2s-prim-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <0>; - qcom,msm-mi2s-rx-lines = <3>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <3>; }; - dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + dai_mi2s0_tx: qcom,msm-dai-q6-mi2s-prim-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <1>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + dai_mi2s1_rx: qcom,msm-dai-q6-mi2s-sec-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <2>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <1>; }; - dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + dai_mi2s1_tx: qcom,msm-dai-q6-mi2s-sec-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <3>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + dai_mi2s2_rx: qcom,msm-dai-q6-mi2s-tert-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <4>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + dai_mi2s2_tx: qcom,msm-dai-q6-mi2s-tert-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <5>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <3>; + }; + + dai_mi2s3_rx: qcom,msm-dai-q6-mi2s-quat-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s3_tx: qcom,msm-dai-q6-mi2s-quat-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <7>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s4_rx: qcom,msm-dai-q6-mi2s-quin-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <8>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s4_tx: qcom,msm-dai-q6-mi2s-quin-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <9>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s5_rx: qcom,msm-dai-q6-mi2s-senary-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <10>; + qcom,msm-mi2s-lines = <0>; + }; + + dai_mi2s5_tx: qcom,msm-dai-q6-mi2s-senary-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <11>; + qcom,msm-mi2s-lines = <3>; }; }; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 3043ea33..893337c7 100755 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -61,11 +61,13 @@ qcom,dcdc@2700 { reg = <0x2700>; interrupts = + <0x0 0x27 0x1 IRQ_TYPE_EDGE_BOTH>, <0x0 0x27 0x4 IRQ_TYPE_EDGE_RISING>, <0x0 0x27 0x6 IRQ_TYPE_EDGE_RISING>, <0x0 0x27 0x7 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "skip-mode", + interrupt-names = "boost-mode-active", + "skip-mode", "input-current-limiting", "switcher-power-ok"; }; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index 428097af..eae1be6f 100755 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -1,4 +1,3 @@ -#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/iio/qcom,spmi-vadc.h> #include <dt-bindings/spmi/spmi.h> @@ -93,17 +92,6 @@ #thermal-sensor-cells = <1>; }; - pm6150l_clkdiv: clock-controller@5b00 { - compatible = "qcom,spmi-clkdiv"; - reg = <0x5b00>; - #clock-cells = <1>; - qcom,num-clkdivs = <1>; - clock-output-names = "pm6150l_div_clk1"; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - status = "disabled"; - }; - pm6150l_gpios: pinctrl@c000 { compatible = "qcom,pm6150l-gpio"; reg = <0xc000>; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index e423f53f..93bf13c3 100755 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -360,9 +360,9 @@ pm7250b_bcl: bcl@1d00 { compatible = "qcom,bcl-v5"; reg = <0x1d00>; - interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, - <0x2 0x1d 0x1 IRQ_TYPE_NONE>, - <0x2 0x1d 0x2 IRQ_TYPE_NONE>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x1d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x1d 0x2 IRQ_TYPE_EDGE_RISING>; interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; diff --git a/qcom/qrb2210-rb1-audio.dtsi b/qcom/qrb2210-rb1-audio.dtsi index ac264b7e..df51a6aa 100755 --- a/qcom/qrb2210-rb1-audio.dtsi +++ b/qcom/qrb2210-rb1-audio.dtsi @@ -116,8 +116,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -143,6 +145,8 @@ <&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", diff --git a/qcom/qrb2210-rb1-msm-audio-lpass.dtsi b/qcom/qrb2210-rb1-msm-audio-lpass.dtsi index 360e984a..88d39d56 100755 --- a/qcom/qrb2210-rb1-msm-audio-lpass.dtsi +++ b/qcom/qrb2210-rb1-msm-audio-lpass.dtsi @@ -91,46 +91,76 @@ msm_dai_mi2s: qcom,msm-dai-mi2s { compatible = "qcom,msm-dai-mi2s"; - dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + dai_mi2s0_rx: qcom,msm-dai-q6-mi2s-prim-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <0>; - qcom,msm-mi2s-rx-lines = <3>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <3>; }; - dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + dai_mi2s0_tx: qcom,msm-dai-q6-mi2s-prim-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <1>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + dai_mi2s1_rx: qcom,msm-dai-q6-mi2s-sec-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <2>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <1>; }; - dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + dai_mi2s1_tx: qcom,msm-dai-q6-mi2s-sec-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <3>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + dai_mi2s2_rx: qcom,msm-dai-q6-mi2s-tert-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <4>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + dai_mi2s2_tx: qcom,msm-dai-q6-mi2s-tert-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <5>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <3>; + }; + + dai_mi2s3_rx: qcom,msm-dai-q6-mi2s-quat-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s3_tx: qcom,msm-dai-q6-mi2s-quat-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <7>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s4_rx: qcom,msm-dai-q6-mi2s-quin-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <8>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s4_tx: qcom,msm-dai-q6-mi2s-quin-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <9>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s5_rx: qcom,msm-dai-q6-mi2s-senary-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <10>; + qcom,msm-mi2s-lines = <0>; + }; + + dai_mi2s5_tx: qcom,msm-dai-q6-mi2s-senary-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <11>; + qcom,msm-mi2s-lines = <3>; }; }; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 96782138..167854b2 100755 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1661,3 +1661,6 @@ &qupv3_se3_4uart { status = "ok"; }; + +#include "camera/qrb2210-rb1-camera.dtsi" +#include "camera/qrb2210-rb1-camera-sensor-idp.dtsi" diff --git a/qcom/qrb4210-rb2-audio.dtsi b/qcom/qrb4210-rb2-audio.dtsi index 371150c8..d2cf3960 100755 --- a/qcom/qrb4210-rb2-audio.dtsi +++ b/qcom/qrb4210-rb2-audio.dtsi @@ -116,8 +116,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -143,6 +145,8 @@ <&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", diff --git a/qcom/qrb4210-rb2-msm-audio-lpass.dtsi b/qcom/qrb4210-rb2-msm-audio-lpass.dtsi index 360e984a..88d39d56 100755 --- a/qcom/qrb4210-rb2-msm-audio-lpass.dtsi +++ b/qcom/qrb4210-rb2-msm-audio-lpass.dtsi @@ -91,46 +91,76 @@ msm_dai_mi2s: qcom,msm-dai-mi2s { compatible = "qcom,msm-dai-mi2s"; - dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + dai_mi2s0_rx: qcom,msm-dai-q6-mi2s-prim-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <0>; - qcom,msm-mi2s-rx-lines = <3>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <3>; }; - dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + dai_mi2s0_tx: qcom,msm-dai-q6-mi2s-prim-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <1>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <0>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + dai_mi2s1_rx: qcom,msm-dai-q6-mi2s-sec-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <2>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <1>; }; - dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + dai_mi2s1_tx: qcom,msm-dai-q6-mi2s-sec-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <3>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + dai_mi2s2_rx: qcom,msm-dai-q6-mi2s-tert-rx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <4>; - qcom,msm-mi2s-rx-lines = <1>; - qcom,msm-mi2s-tx-lines = <2>; + qcom,msm-mi2s-lines = <0>; }; - dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + dai_mi2s2_tx: qcom,msm-dai-q6-mi2s-tert-tx { compatible = "qcom,msm-dai-q6-mi2s"; qcom,msm-dai-q6-mi2s-dev-id = <5>; - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <3>; + qcom,msm-mi2s-lines = <3>; + }; + + dai_mi2s3_rx: qcom,msm-dai-q6-mi2s-quat-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s3_tx: qcom,msm-dai-q6-mi2s-quat-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <7>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s4_rx: qcom,msm-dai-q6-mi2s-quin-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <8>; + qcom,msm-mi2s-lines = <1>; + }; + + dai_mi2s4_tx: qcom,msm-dai-q6-mi2s-quin-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <9>; + qcom,msm-mi2s-lines = <2>; + }; + + dai_mi2s5_rx: qcom,msm-dai-q6-mi2s-senary-rx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <10>; + qcom,msm-mi2s-lines = <0>; + }; + + dai_mi2s5_tx: qcom,msm-dai-q6-mi2s-senary-tx { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <11>; + qcom,msm-mi2s-lines = <3>; }; }; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 6ad519ce..6d7b9570 100755 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -328,5 +328,11 @@ qcom,dump-id = <0xe8>; }; }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; }; diff --git a/qcom/sa410m-pmic.dtsi b/qcom/sa410m-pmic.dtsi new file mode 100755 index 00000000..cc2e8bc4 --- /dev/null +++ b/qcom/sa410m-pmic.dtsi @@ -0,0 +1,164 @@ +#include "pm2250.dtsi" + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = <ADC5_XO_THERM_100K_PU>; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = <ADC5_AMUX_THM2_100K_PU>; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = <ADC5_AMUX_THM3_100K_PU>; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = <ADC5_GPIO3_100K_PU>; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = <ADC5_GPIO4_100K_PU>; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + /delete-node/ vbat_sns; + /delete-node/ usb_in_v_div_16; + /delete-node/ chg_temp; + /delete-node/ bat_therm; + /delete-node/ bat_therm_30k; + /delete-node/ bat_therm_400k; + /delete-node/ i_parallel; + /delete-node/ bat_id; + /delete-node/ die_temp_s3; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm2250_vadc ADC5_GPIO3_100K_PU>, + <&pm2250_vadc ADC5_GPIO4_100K_PU>; + + xo_therm { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = <ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + msm_therm { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = <ADC5_GPIO3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = <ADC5_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + /delete-node/ pm2250_qg; + /delete-node/ pm2250_charger; + }; + + qcom,pm2250@1 { + /delete-node/ pm2250_vib; + /delete-node/ pm2250_pwm1; + /delete-node/ pm2250_pwm2; + /delete-node/ pm2250_pwm3; + }; +}; + +&thermal_zones { + pm2250_tz { + trips { + trip0 { + temperature = <105000>; + }; + + trip1 { + temperature = <125000>; + }; + + trip2 { + temperature = <155000>; + }; + }; + }; +}; diff --git a/qcom/sa410m-qupv3.dtsi b/qcom/sa410m-qupv3.dtsi new file mode 100755 index 00000000..39004985 --- /dev/null +++ b/qcom/sa410m-qupv3.dtsi @@ -0,0 +1,212 @@ +#include <dt-bindings/interconnect/qcom,scuba.h> + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4ac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + <MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>, + <MASTER_QUP_0 SLAVE_EBI_CH0>; + qcom,vote-for-bw; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se4_2uart: qcom,qup_uart@4a90000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4a90000 0x4000>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@4a80000 { + reg = <0x4a80000 0x4000>; + compatible = "qcom,i2c-geni"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@4a8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a8c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@4a94000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + +}; diff --git a/qcom/sa410m-usb.dtsi b/qcom/sa410m-usb.dtsi new file mode 100755 index 00000000..4ab9290e --- /dev/null +++ b/qcom/sa410m-usb.dtsi @@ -0,0 +1,159 @@ +#include <dt-bindings/clock/qcom,gcc-scuba.h> +#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h> + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x0120 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>, + <&wakegic 90 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,bus-suspend-enable; + snps,usb2-gadget-lpm-disable; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@1613000 { + compatible = "qcom,qusb2phy"; + reg = <0x01613000 0x180>, + <0x003cb250 0x4>, + <0x01b40258 0x4>, + <0x01612000 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "eud_enable_reg"; + + vdd-supply = <&pm2250_l12>; + vdda18-supply = <&pm2250_l13>; + vdda33-supply = <&pm2250_l21>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/sa410m.dts b/qcom/sa410m.dts index d8abae26..b988a0c8 100755 --- a/qcom/sa410m.dts +++ b/qcom/sa410m.dts @@ -9,3 +9,22 @@ qcom,msm-id = <441 0x10000>, <471 0x10000>; qcom,board-id = <34 0>; }; + + +&sdhc_1 { + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index f8212a93..d30a4d7a 100755 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,scuba.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> / { #address-cells = <2>; @@ -24,7 +25,10 @@ granule = <512>; }; - aliases {}; + aliases { + serial0 = &qupv3_se4_2uart; + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + }; firmware: firmware {}; @@ -389,6 +393,11 @@ #address-cells = <1>; #size-cells = <1>; + download_mode@0 { + compatible = "qcom,msm-imem-download_mode"; + reg = <0x0 0x8>; + }; + mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 0x8>; @@ -423,6 +432,16 @@ compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; }; + + emergency_download_mode@fe0 { + compatible = "qcom,msm-imem-emergency_download_mode"; + reg = <0xfe0 0xc>; + }; + + ss_mdump@b88 { + compatible = "qcom,msm-imem-minidump"; + reg = <0xb88 0x1c>; + }; }; dload_mode { @@ -468,6 +487,22 @@ 0x0f1a80b8 0x0f1b80b8>; }; + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + status = "okay"; + + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; + + }; + eud: qcom,msm-eud@1610000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; @@ -480,8 +515,8 @@ qcom,secure-eud-en; qcom,eud-tcsr-check-enable; qcom,eud-clock-vote-req; - //clocks = <&gcc GCC_AHB2PHY_USB_CLK>; - //clock-names = "eud_ahb2phy_clk"; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; status = "disabled"; }; @@ -697,6 +732,27 @@ status = "ok"; }; + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones { }; + clk_virt: interconnect@0 { compatible = "qcom,scuba-clk_virt"; qcom,keepalive; @@ -707,7 +763,7 @@ }; system_noc: interconnect0@1880000 { - reg = <0x1880000 0x60200>; + reg = <0x01880000 0x5e080>; compatible = "qcom,scuba-sys_noc"; qcom,keepalive; #interconnect-cells = <1>; @@ -761,21 +817,21 @@ pil_scm_pas { compatible = "qcom,pil-tz-scm-pas"; - //interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; }; qcom,lpass@ab00000 { compatible = "qcom,pil-tz-generic"; reg = <0xab00000 0x00100>; - //clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - //clock-names = "xo"; - //qcom,proxy-clock-names = "xo"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; - //vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; - //qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; - //vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; - //qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; qcom,firmware-name = "adsp"; @@ -790,11 +846,11 @@ qcom,minidump-as-elf32; /* Inputs from lpass */ - //interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>, - // <&adsp_smp2p_in 0 0>, - // <&adsp_smp2p_in 2 0>, - // <&adsp_smp2p_in 1 0>, - // <&adsp_smp2p_in 3 0>; + interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", @@ -803,7 +859,7 @@ "qcom,stop-ack"; /* Outputs to lpass */ - //qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; status = "ok"; }; @@ -812,12 +868,12 @@ compatible = "qcom,pil-tz-generic"; reg = <0x6080000 0x100>; - //clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - //clock-names = "xo"; - //qcom,proxy-clock-names = "xo"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; - //vdd_cx-supply = <&VDD_CX_LEVEL>; - //qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; qcom,proxy-reg-names = "vdd_cx"; qcom,firmware-name = "modem"; @@ -833,12 +889,12 @@ qcom,sequential-fw-load; /* Inputs from mss */ - //interrupts-extended = <&intc 0 307 1>, - // <&modem_smp2p_in 0 0>, - // <&modem_smp2p_in 2 0>, - // <&modem_smp2p_in 1 0>, - // <&modem_smp2p_in 3 0>, - // <&modem_smp2p_in 7 0>; + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", @@ -848,7 +904,7 @@ "qcom,shutdown-ack"; /* Outputs to mss */ - //qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; status = "ok"; }; @@ -870,7 +926,7 @@ smem: qcom,smem { compatible = "qcom,smem"; - //memory-region = <&smem_mem>; + memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; @@ -886,6 +942,61 @@ reg = <0x45f0000 0x7000>; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + }; + + }; + rpm-glink { compatible = "qcom,glink-rpm"; interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; @@ -1104,14 +1215,134 @@ }; }; + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>,<1600 1600>, + /* 25 MB/s */ + <25600 250000>,<50000 133320>, + /* 50 MB/s */ + <51200 250000>,<65000 133320>, + /* 100 MB/s */ + <102400 250000>,<65000 133320>, + /* 200 MB/s */ + <204800 800000>,<200000 300000>, + /* 400 MB/s */ + <204800 800000>,<200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + non-removable; + supports-cqe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + }; +#include "sa410m-pmic.dtsi" #include "sa410m-pinctrl.dtsi" #include "pm2250-rpm-regulator.dtsi" #include "scuba-regulator.dtsi" #include "scuba-ion.dtsi" #include "msm-arm-smmu-scuba.dtsi" #include "sa410m-gdsc.dtsi" +#include "sa410m-qupv3.dtsi" +#include "sa410m-usb.dtsi" + +&qupv3_se4_2uart { + status = "ok"; +}; &gcc_camss_top_gdsc { status = "ok"; diff --git a/qcom/sa6155-audio.dtsi b/qcom/sa6155-audio.dtsi index 8e1aa63d..491907da 100755 --- a/qcom/sa6155-audio.dtsi +++ b/qcom/sa6155-audio.dtsi @@ -517,9 +517,12 @@ qcom,msm-dai-q6 { "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -555,7 +558,10 @@ qcom,msm-dai-q6 { asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/sa8155-audio.dtsi b/qcom/sa8155-audio.dtsi index e93ab895..5b47b3c3 100755 --- a/qcom/sa8155-audio.dtsi +++ b/qcom/sa8155-audio.dtsi @@ -513,9 +513,12 @@ qcom,msm-dai-q6 { "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -551,7 +554,10 @@ qcom,msm-dai-q6 { asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi index 0db1f18b..34bc5d4f 100755 --- a/qcom/sa8155-vm-audio.dtsi +++ b/qcom/sa8155-vm-audio.dtsi @@ -469,9 +469,12 @@ "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", "msm-pcm-dtmf"; asoc-cpu = <&dai_hdmi>, <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -507,7 +510,10 @@ asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 33b78767..ecba5e19 100755 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -738,10 +738,6 @@ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "km_clk_src"; }; - - cpu_pmu: cpu-pmu { - compatible = "arm,armv8-pmuv3"; - }; }; ®ulator { diff --git a/qcom/scuba-audio.dtsi b/qcom/scuba-audio.dtsi index bd1b4870..3413dfea 100755 --- a/qcom/scuba-audio.dtsi +++ b/qcom/scuba-audio.dtsi @@ -100,8 +100,10 @@ "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, + asoc-cpu = <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, @@ -128,6 +130,8 @@ <&afe_loopback_tx>; asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 470a6f07..13873b79 100755 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1385,7 +1385,6 @@ }; compute_noc: interconnect@9800000 { - reg = <0x9800000 0x40000>; compatible = "qcom,scshrike-compute_noc"; #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index af761c45..aa3a027e 100755 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -117,7 +117,7 @@ qcom,num-parf-testbus-sel = <0xb9>; qcom,config-recovery; - qcom,pcie-phy-ver = <1102>; + qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; @@ -160,7 +160,7 @@ 0x1168 0x0a 0x0 0x116c 0x04 0x0 0x119c 0x88 0x0 - 0x1174 0x20 0x0 + 0x1174 0x60 0x0 0x117c 0x06 0x0 0x11a0 0x14 0x0 0x11a8 0x0f 0x0 @@ -267,6 +267,8 @@ 0x1584 0x28 0x0 0x1370 0x2e 0x0 0x155c 0x2e 0x0 + 0x140c 0x1d 0x0 + 0x1388 0xaa 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 43abbcc5..3193b02c 100755 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -7,144 +7,126 @@ }; &i2c_1 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_2 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_3 { - iommus = <&apps_smmu 0x14c 0x0>, - <&apps_smmu 0x14d 0x0>; + iommus = <&apps_smmu 0x14c 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_4 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_5 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_6 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &i2c_7 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_1 { - iommus = <&apps_smmu 0x148 0x0>, - <&apps_smmu 0x149 0x0>; + iommus = <&apps_smmu 0x148 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_2 { - iommus = <&apps_smmu 0x14a 0x0>, - <&apps_smmu 0x14b 0x0>; + iommus = <&apps_smmu 0x14a 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_3 { - iommus = <&apps_smmu 0x14c 0x0>, - <&apps_smmu 0x14d 0x0>; + iommus = <&apps_smmu 0x14c 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &spi_4 { - iommus = <&apps_smmu 0x14e 0x0>, - <&apps_smmu 0x14f 0x0>; + iommus = <&apps_smmu 0x14e 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart1a_hs { - iommus = <&apps_smmu 0x140 0x0>, - <&apps_smmu 0x141 0x0>; + iommus = <&apps_smmu 0x140 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart1b_hs { - iommus = <&apps_smmu 0x140 0x0>, - <&apps_smmu 0x141 0x0>; + iommus = <&apps_smmu 0x140 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart2a_hs { - iommus = <&apps_smmu 0x142 0x0>, - <&apps_smmu 0x143 0x0>; + iommus = <&apps_smmu 0x142 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart2b_hs { - iommus = <&apps_smmu 0x142 0x0>, - <&apps_smmu 0x143 0x0>; + iommus = <&apps_smmu 0x142 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart3_hs { - iommus = <&apps_smmu 0x144 0x0>, - <&apps_smmu 0x145 0x0>; + iommus = <&apps_smmu 0x144 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart4a_hs { - iommus = <&apps_smmu 0x146 0x0>, - <&apps_smmu 0x147 0x0>; + iommus = <&apps_smmu 0x146 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; &blsp1_uart4b_hs { - iommus = <&apps_smmu 0x146 0x0>, - <&apps_smmu 0x147 0x0>; + iommus = <&apps_smmu 0x146 0x1>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; @@ -163,7 +145,7 @@ < 345600 >, < 576000 >, < 1094400 >, - < 1708800 >; + < 1804800 >; }; &cpu0_cpu_ddr_tbl { @@ -171,5 +153,5 @@ < 345600 MHZ_TO_MBPS( 300, 4) >, < 576000 MHZ_TO_MBPS( 768, 4) >, < 1440000 MHZ_TO_MBPS(1555, 4) >, - < 1708800 MHZ_TO_MBPS(2092, 4) >; + < 1804800 MHZ_TO_MBPS(2092, 4) >; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 96cb90e6..090b94f1 100755 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -972,7 +972,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0308>; qcom,pcie-link-speed = <4>; - qcom,pcie-phy-ver = <6>; + qcom,pcie-phy-ver = <8>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; @@ -1012,7 +1012,7 @@ 0x1168 0x0a 0x0 0x116c 0x04 0x0 0x119c 0x88 0x0 - 0x1174 0x20 0x0 + 0x1174 0x60 0x0 0x11a0 0x14 0x0 0x11a8 0x0f 0x0 0x0220 0x16 0x0 @@ -1117,6 +1117,7 @@ 0x1370 0x2e 0x0 0x155c 0x2e 0x0 0x1484 0x08 0x0 + 0x1388 0xaa 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; diff --git a/qcom/shima-atp.dtsi b/qcom/shima-atp.dtsi index 3fc75973..f94b6882 100755 --- a/qcom/shima-atp.dtsi +++ b/qcom/shima-atp.dtsi @@ -199,8 +199,8 @@ }; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/shima-audio.dtsi b/qcom/shima-audio.dtsi index 10ee18cc..5fd0a1fa 100755 --- a/qcom/shima-audio.dtsi +++ b/qcom/shima-audio.dtsi @@ -180,9 +180,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -217,6 +221,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 728936ec..0b0623b7 100755 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -223,8 +223,8 @@ }; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 926f4c27..1621cfee 100755 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -467,8 +467,8 @@ <&bolero>; }; -&dai_mi2s2 { - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s2_tx { + qcom,msm-mi2s-lines = <1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active &tert_mi2s_sd0_active>; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index d621f8ff..d7f3bc06 100755 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -27,7 +27,7 @@ compatible = "qcom,slate-daemon"; }; - qcom,audio-cc-ipc-platform { + audio_cc_ipc_platform: qcom,audio-cc-ipc-platform { compatible = "qcom,audio-cc-ipc-platform"; cc_codec: qcom,cc-codec { compatible = "qcom,cc-codec"; diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi index c902b9b7..320066a1 100755 --- a/qcom/sm8150-qupv3.dtsi +++ b/qcom/sm8150-qupv3.dtsi @@ -38,6 +38,84 @@ status = "ok"; }; + gpi_dma0: qcom,gpi-dma@0x800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x00d6 0x0>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + status = "disabled"; + }; + + gpi_dma1: qcom,gpi-dma@0xa00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x0616 0x0>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + status = "ok"; + }; + + gpi_dma2: qcom,gpi-dma@0xc00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xc00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x07b6 0x0>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + status = "disabled"; + }; + /* I2C */ qupv3_se0_i2c: i2c@880000 { compatible = "qcom,i2c-geni"; @@ -349,6 +427,9 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 1 2 64 0>, + <&gpi_dma1 1 1 2 64 0>; + dma-names = "tx", "rx"; pinctrl-names = "default","active", "sleep"; pinctrl-0 = <&qupv3_se4_2uart_default>; pinctrl-1 = <&qupv3_se4_2uart_active>; diff --git a/qcom/yupik-audio-overlay.dtsi b/qcom/yupik-audio-overlay.dtsi index c3de58d5..8a69b60a 100755 --- a/qcom/yupik-audio-overlay.dtsi +++ b/qcom/yupik-audio-overlay.dtsi @@ -488,9 +488,12 @@ }; }; -&dai_mi2s1 { - qcom,msm-mi2s-rx-lines = <0>; - qcom,msm-mi2s-tx-lines = <1>; +&dai_mi2s1_rx { + qcom,msm-mi2s-lines = <0>; +}; + +&dai_mi2s1_tx { + qcom,msm-mi2s-lines = <1>; }; &adsp_loader { diff --git a/qcom/yupik-audio.dtsi b/qcom/yupik-audio.dtsi index 6800853a..865416bd 100755 --- a/qcom/yupik-audio.dtsi +++ b/qcom/yupik-audio.dtsi @@ -180,9 +180,13 @@ "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_dp>, <&dai_dp1>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s0_rx>, <&dai_mi2s0_tx>, + <&dai_mi2s1_rx>, <&dai_mi2s1_tx>, + <&dai_mi2s2_rx>, <&dai_mi2s2_tx>, + <&dai_mi2s3_rx>, <&dai_mi2s3_tx>, + <&dai_mi2s4_rx>, <&dai_mi2s4_tx>, + <&dai_mi2s5_rx>, <&dai_mi2s5_tx>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, <&dai_sen_auxpcm>, @@ -217,6 +221,9 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-mi2s.6", "msm-dai-q6-mi2s.7", + "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", + "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", |