diff options
131 files changed, 31895 insertions, 1 deletions
diff --git a/qcom/Makefile b/qcom/Makefile index 1edebd29..c2c2115a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -289,6 +289,53 @@ sdm660-internal-codec-cdp.dtb \ sdm660-usbc-audio-rcm.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_SDM439) += sdm439-mtp-overlay.dtbo + +dtbo-$(CONFIG_ARCH_SDM429) += sdm429-mtp-overlay.dtbo \ + sdm429-cdp-overlay.dtbo \ + sdm429-qrd-overlay.dtbo + +dtbo-$(CONFIG_ARCH_QM215) +=qm215-qrd-overlay.dtbo \ + qcm2150-qrd-overlay.dtbo \ + qm215-qrd-smb1360-overlay.dtbo +sdm439-mtp-overlay.dtbo-base := sdm439.dtb \ + sda439.dtb \ + msm8937-interposer-sdm439.dtb + +sdm429-mtp-overlay.dtbo-base := sdm429.dtb \ + sda429.dtb \ + msm8937-interposer-sdm429.dtb + +sdm429-cdp-overlay.dtbo-base := sdm429.dtb \ + sda429.dtb \ + msm8937-interposer-sdm429.dtb + +sdm429-qrd-overlay.dtbo-base := sdm429.dtb \ + msm8937-interposer-sdm429.dtb + +qm215-qrd-overlay.dtbo-base := qm215.dtb +qcm2150-qrd-overlay.dtbo-base := qcm2150.dtb +qm215-qrd-smb1360-overlay.dtbo-base := qm215.dtb +else +dtb-$(CONFIG_ARCH_SDM439) += sdm439-mtp.dtb \ + sdm439-cdp.dtb \ + sdm439-qrd.dtb \ + sda439-mtp.dtb \ + sda439-cdp.dtb \ + sdm439-external-codec-mtp.dtb \ + sdm439-rcm.dtb +dtb-$(CONFIG_ARCH_QM215) += qm215-qrd.dtb \ + qcm2150-qrd.dtb \ + qm215-qrd-smb1360.dtb + +dtb-$(CONFIG_ARCH_SDM429) += sdm429-mtp.dtb \ + sdm429-cdp.dtb \ + sdm429-qrd.dtb \ + sda429-mtp.dtb \ + sda429-cdp.dtb +endif + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/dsi-adv7533-1080p.dtsi b/qcom/dsi-adv7533-1080p.dtsi new file mode 100644 index 00000000..0a4f9e63 --- /dev/null +++ b/qcom/dsi-adv7533-1080p.dtsi @@ -0,0 +1,63 @@ +&mdss_mdp { + dsi_adv7533_1080p: qcom,mdss_dsi_adv7533_1080p { + label = "adv7533 1080p video mode dsi panel"; + qcom,mdss-dsi-panel-name = "dsi_adv7533_1080p"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 c8 00 02 11 00 + 05 01 00 00 0a 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [ + E6 38 26 00 68 6C 2A 3A 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2B>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <160>; + qcom,mdss-pan-physical-height-dimension = <90>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-always-on; + qcom,mdss-dsi-panel-timings-phy-v2 = [1d 1a 03 05 01 03 04 a0 + 1d 1a 03 05 01 03 04 a0 + 1d 1a 03 05 01 03 04 a0 + 1d 1a 03 05 01 03 04 a0 + 1d 1a 03 05 01 03 04 a0]; + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + }; +}; diff --git a/qcom/dsi-adv7533-720p.dtsi b/qcom/dsi-adv7533-720p.dtsi new file mode 100644 index 00000000..82f6b92f --- /dev/null +++ b/qcom/dsi-adv7533-720p.dtsi @@ -0,0 +1,62 @@ +&mdss_mdp { +dsi_adv7533_720p: qcom,mdss_dsi_adv7533_720p { + label = "adv7533 720p video mode dsi panel"; + qcom,mdss-dsi-panel-name = "dsi_adv7533_720p"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <720>; + qcom,mdss-dsi-h-front-porch = <110>; + qcom,mdss-dsi-h-back-porch = <220>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 c8 00 02 11 00 + 05 01 00 00 0a 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-panel-timings = [ + A4 24 18 00 4E 52 1C 28 1C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x20>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <160>; + qcom,mdss-pan-physical-height-dimension = <90>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-always-on; + qcom,mdss-dsi-panel-timings-phy-v2 = [1c 19 02 03 01 03 04 a0 + 1c 19 02 03 01 03 04 a0 + 1c 19 02 03 01 03 04 a0 + 1c 19 02 03 01 03 04 a0 + 1c 08 02 03 01 03 04 a0]; + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + }; +}; diff --git a/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi b/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi new file mode 100644 index 00000000..ce5ac641 --- /dev/null +++ b/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi @@ -0,0 +1,76 @@ +&mdss_mdp { + dsi_edo_rm67162_qvga_cmd: qcom,mdss_dsi_edo_rm67162_qvga_cmd { + qcom,mdss-dsi-panel-name = "rm67162 qvga cmd mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <320>; + qcom,mdss-dsi-panel-height = <360>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-pixel-packing = "tight"; + qcom,mdss-dsi-pixel-alignment = <0>; + qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 FE 0A + 29 01 00 00 00 00 02 29 90 + 29 01 00 00 00 00 02 FE 05 + 29 01 00 00 00 00 02 05 00 + 29 01 00 00 00 00 02 FE 00 + 29 01 00 00 00 00 02 35 00 + 29 01 00 00 00 00 02 51 80 + 29 01 00 00 00 00 02 53 20 + 29 01 00 00 78 00 02 11 00 + 29 01 00 00 05 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 05 00 02 51 00 + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 14 00 02 4F 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-idle-on-command = [ + 15 01 00 00 00 00 02 FE 00 + 05 01 00 00 00 00 01 39 /* Idle-Mode On */ + ]; + qcom,mdss-dsi-idle-off-command = [ + 05 01 00 00 00 00 01 38 /* Idle-Mode Off */ + ]; + qcom,mdss-dsi-idle-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-idle-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 22 27 + 1e 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 1>, <0 12>, <1 12>; + }; +}; diff --git a/qcom/dsi-panel-hx8394f-720p-video.dtsi b/qcom/dsi-panel-hx8394f-720p-video.dtsi new file mode 100644 index 00000000..9a10e0cd --- /dev/null +++ b/qcom/dsi-panel-hx8394f-720p-video.dtsi @@ -0,0 +1,121 @@ +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *--------------------------------------------------------------------------- + */ +&mdss_mdp { + dsi_hx8394f_720p_video: qcom,mdss_dsi_hx8394f_720p_video { + qcom,mdss-dsi-panel-name = "hx8394f 720p video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <16>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <15>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 B9 FF 83 94 + 39 01 00 00 00 00 07 + BA 63 03 68 6B B2 C0 + 39 01 00 00 00 00 0B + B1 50 12 72 09 33 54 B1 31 6B 2F + 39 01 00 00 00 00 07 + B2 00 80 64 0E 0D 2F + 39 01 00 00 00 00 16 + B4 73 74 73 74 73 74 01 0C 86 75 + 00 3F 73 74 73 74 73 74 01 0C 86 + 39 01 00 00 00 00 22 + D3 00 00 07 07 40 07 10 00 08 10 + 08 00 08 54 15 0E 05 0E 02 15 06 + 05 06 47 44 0A 0A 4B 10 07 07 0E + 40 + 39 01 00 00 00 00 2D + D5 1A 1A 1B 1B 00 01 02 03 04 05 + 06 07 08 09 0A 0B 24 25 18 18 26 + 27 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 18 20 21 18 18 18 + 18 + 39 01 00 00 00 00 2D + D6 1A 1A 1B 1B 0B 0A 09 08 07 06 + 05 04 03 02 01 00 21 20 18 18 27 + 26 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 18 25 24 18 18 18 + 18 + 39 01 00 00 00 00 3B + E0 00 0C 19 20 23 26 29 28 51 61 + 70 6F 76 86 89 8D 99 9A 95 A1 B0 + 57 55 58 5C 5e 64 6B 7F 00 0C 19 + 20 23 26 29 28 51 61 70 6F 76 86 + 89 8D 99 9A 95 A1 B0 57 55 58 5C + 5E 64 6B 7F + 39 01 00 00 00 00 03 C0 1F 31 + 15 01 00 00 00 00 02 CC 0B + 15 01 00 00 00 00 02 D4 02 + 15 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 0D + D8 FF FF FF FF FF FF FF FF FF FF + FF FF + 15 01 00 00 00 00 02 BD 00 + 15 01 00 00 00 00 02 BD 01 + 15 01 00 00 00 00 02 B1 00 + 15 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 08 + BF 40 81 50 00 1A FC 01 + 39 01 00 00 00 00 03 B6 7D 7D + 05 01 00 00 78 00 02 11 00 + 39 01 00 00 00 00 0D + B2 00 80 64 0E 0D 2F 00 00 00 00 + C0 18 + 05 01 00 00 14 00 02 29 00]; + + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings + = [72 16 0e 00 38 3c 12 1a 10 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 D9 + 06 01 00 01 05 00 01 09 + 06 01 00 01 05 00 01 45]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <4 4 3>; + qcom,mdss-dsi-panel-status-valid-params = <1 3 2>; + qcom,mdss-dsi-panel-status-value = + <0x80 0x80 0x73 0x04 0x05 0x0f>, + <0x80 0x80 0x73 0x04 0x05 0x1e>; + qcom,mdss-dsi-panel-max-error-count = <3>; + }; +}; diff --git a/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi b/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi new file mode 100644 index 00000000..00766ed4 --- /dev/null +++ b/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi @@ -0,0 +1,123 @@ +&mdss_mdp { + dsi_hx8399c_hd_vid: qcom,mdss_dsi_hx8399c_hd_video { + qcom,mdss-dsi-panel-name = + "hx8399c video mode dsi hd panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <48>; + qcom,mdss-dsi-h-back-porch = <48>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <40>; + qcom,mdss-dsi-v-front-porch = <36>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 + b9 ff 83 99 + 39 01 00 00 00 00 02 + d2 88 + 39 01 00 00 00 00 0c + b1 02 04 72 92 01 + 32 aa 11 11 52 57 + 39 01 00 00 00 00 10 + b2 00 80 80 cc 05 07 5a + 11 10 10 00 1e 70 03 d4 + 39 01 00 00 00 00 2d + b4 00 ff 59 59 01 ab 00 + 00 09 00 03 05 00 28 03 + 0b 0d 21 03 02 00 0c a3 + 80 59 59 02 ab 00 00 09 + 00 03 05 00 28 03 0b 0d + 02 00 0c a3 01 + 39 01 00 00 05 00 22 + d3 00 0c 03 03 00 00 10 + 10 00 00 03 00 03 00 08 + 78 08 78 00 00 00 00 00 + 24 02 05 05 03 00 00 00 + 05 40 + 39 01 00 00 05 00 21 + d5 20 20 19 19 18 18 02 + 03 00 01 24 24 18 18 18 + 18 24 24 00 00 00 00 00 + 00 00 00 2f 2f 30 30 31 + 31 + 39 01 00 00 05 00 21 + d6 24 24 18 18 19 19 01 + 00 03 02 24 24 18 18 18 + 18 20 20 40 40 40 40 40 + 40 40 40 2f 2f 30 30 31 + 31 + 39 01 00 00 00 00 02 + bd 00 + 39 01 00 00 00 00 11 + d8 aa aa aa aa aa aa aa + aa aa ba aa aa aa ba aa + aa + 39 01 00 00 00 00 02 + bd 01 + 39 01 00 00 00 00 11 + d8 00 00 00 00 00 00 00 + 00 82 ea aa aa 82 ea aa + aa + 39 01 00 00 00 00 02 + bd 02 + 39 01 00 00 00 00 09 + d8 ff ff c0 3f ff ff c0 + 3f + 39 01 00 00 00 00 02 + bd 00 + 39 01 00 00 05 00 37 + e0 01 21 31 2d 66 6f 7b + 75 7a 81 86 89 8c 90 95 + 97 9a a1 a2 aa 9e ad b0 + 5b 57 63 7a 01 21 31 2d + 66 6f 7b 75 7a 81 86 89 + 8c 90 95 97 9a a1 a2 aa + 9e ad b0 5b 57 63 7a + 39 01 00 00 00 00 03 + b6 7e 7e + 39 01 00 00 00 00 02 + cc 08 + 39 01 00 00 00 00 02 + 35 00 + 39 01 00 00 00 00 02 + dd 03 + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = + [7a 1a 12 00 3e 42 16 1e 14 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x1d>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + }; +}; diff --git a/qcom/dsi-panel-icn9706-720-1440p-video.dtsi b/qcom/dsi-panel-icn9706-720-1440p-video.dtsi new file mode 100644 index 00000000..482e6a72 --- /dev/null +++ b/qcom/dsi-panel-icn9706-720-1440p-video.dtsi @@ -0,0 +1,86 @@ +&mdss_mdp { + dsi_icn9706_720_1440_vid: qcom,mdss_dsi_icn9706_720_1440p_video { + qcom,mdss-dsi-panel-name = + "icn9706 720 1440p video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <84>; + qcom,mdss-dsi-h-back-porch = <84>; + qcom,mdss-dsi-h-pulse-width = <24>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <24>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [8b 1e 14 00 44 48 18 22 19 + 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1c>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-on-command = [39 01 00 00 64 00 02 01 00 + 39 01 00 00 00 00 03 f0 5a 5a + 39 01 00 00 00 00 03 f1 5a 5a + 39 01 00 00 00 00 03 f0 b4 4b + 39 01 00 00 00 00 03 b6 10 10 + 39 01 00 00 00 00 15 b4 0a 08 12 10 0e 0c 00 00 + 00 03 00 03 03 03 03 03 03 03 04 06 + 39 01 00 00 00 00 15 b3 0b 09 13 11 0f 0d 00 00 + 00 03 00 03 03 03 03 03 03 03 05 07 + 39 01 00 00 00 00 0d b0 54 32 23 45 44 44 44 44 + 60 01 60 01 + 39 01 00 00 00 00 09 b1 32 84 02 83 15 01 57 01 + 39 01 00 00 00 00 02 b2 33 + 39 01 00 00 00 00 07 bd 54 14 6a 6a 20 19 + 39 01 00 00 00 00 12 b7 01 01 09 11 0d 15 19 0d + 21 1d 00 00 20 00 02 ff 3c + 39 01 00 00 00 00 06 b8 23 01 30 34 53 + 39 01 00 00 00 00 05 b9 a1 2c ff c4 + 39 01 00 00 00 00 03 ba 88 23 + 39 01 00 00 00 00 07 c1 16 16 04 0c 10 04 + 39 01 00 00 00 00 03 c2 12 68 + 39 01 00 00 00 00 04 c3 22 31 04 + 39 01 00 00 00 00 06 c7 05 23 6b 41 00 + 39 01 00 00 00 00 27 c8 7c 54 3d 2d 26 16 1b 08 + 25 28 2d 4f 3e 48 3d 3d 35 25 06 7c 54 3d 2d + 26 16 1b 08 25 28 2d 4f 3e 48 3d 3d 35 25 06 + 39 01 00 00 00 00 09 c6 00 00 68 00 00 60 36 00 + 05 01 00 00 64 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + + qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 + 05 01 00 00 32 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "bta_check"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 20>, <1 50>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-pan-physical-width-dimension = <63>; + qcom,mdss-pan-physical-height-dimension = <112>; + }; +}; diff --git a/qcom/dsi-panel-r69006-1080p-cmd.dtsi b/qcom/dsi-panel-r69006-1080p-cmd.dtsi new file mode 100644 index 00000000..d51176e7 --- /dev/null +++ b/qcom/dsi-panel-r69006-1080p-cmd.dtsi @@ -0,0 +1,145 @@ +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *--------------------------------------------------------------------------- + */ + +&mdss_mdp { + dsi_r69006_1080p_cmd: qcom,mdss_dsi_r69006_1080p_cmd { + qcom,mdss-dsi-panel-name = "r69006 1080p cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <82>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <9>; + qcom,mdss-dsi-v-front-porch = <3>; + qcom,mdss-dsi-v-pulse-width = <15>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 06 + B3 04 10 00 00 00 + 29 01 00 00 00 00 03 + B4 0C 00 + 29 01 00 00 00 00 04 + B6 3B D3 00 + 23 01 00 00 00 00 + 02 C0 00 + 15 01 00 00 00 00 + 02 36 98 + 23 01 00 00 00 00 + 02 CC 04 + 29 01 00 00 00 00 20 + C1 84 00 10 EF 8B F1 FF + FF DF 9C C5 9A 73 8D AD + 63 FE FF FF CB F8 01 00 + AA 40 02 C2 01 08 00 01 + 29 01 00 00 00 00 0A + CB 0D FE 1F 2C 00 00 00 + 00 00 + 29 01 00 00 00 00 0B + C2 01 F7 80 04 63 00 60 + 00 01 30 + 29 01 00 00 00 00 07 + C3 55 01 00 01 00 00 + 29 01 00 00 00 00 12 + C4 70 00 00 00 00 00 00 + 00 00 02 01 00 05 01 00 + 00 00 + 29 01 00 00 00 00 0F + C6 57 07 4A 07 4A 01 0E + 01 02 01 02 09 15 07 + 29 01 00 00 00 00 1F + C7 00 06 0C 16 27 35 3F + 4D 33 3C 49 5B 64 66 67 + 00 06 0C 16 27 35 3F 4D + 33 3C 49 5B 64 66 67 + 29 01 00 00 00 00 14 + C8 00 00 FE 01 08 E7 00 + 00 FD 02 03 A8 00 00 FC + E7 E9 C9 00 + 29 01 00 00 00 00 09 + C9 1F 68 1F 68 4C 4C C4 + 11 + 29 01 00 00 00 00 11 + D0 11 01 91 0B D9 19 19 + 00 00 00 19 99 00 00 00 + 00 + 29 01 00 00 00 00 1D + D3 1B 3B BB AD A5 33 33 + 33 00 80 AD A8 37 33 33 + 33 33 F7 F2 1F 7D 7C FF + 0F 99 00 FF FF + 29 01 00 00 00 00 04 + D4 57 33 03 + 29 01 00 00 00 00 0C + D5 66 00 00 01 32 01 32 + 00 0b 00 0b + 29 01 00 00 00 00 02 BE 04 + 29 01 00 00 00 00 11 + CF 40 10 00 00 00 00 32 + 00 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 06 + DE 00 00 3F FF 10 + 29 01 00 00 00 00 02 E9 00 + 29 01 00 00 00 00 02 F2 00 + 23 01 00 00 00 00 02 D6 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 2C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 0A 00 02 28 00 + 29 01 00 00 00 00 1d D3 13 3B BB A5 A5 33 33 33 + 00 80 A4 A8 37 33 33 33 33 F7 F2 1F 7D + 7C FF 0F 99 00 FF FF + 05 01 00 00 5A 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-timings = [6E 3F 36 00 5A 4F 38 41 54 + 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x1e>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 0A]; + qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-status-value = <0x1C>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-rx-eot-ignore; + qcom,mdss-dsi-tx-eot-append; + }; +}; diff --git a/qcom/dsi-panel-r69006-1080p-video.dtsi b/qcom/dsi-panel-r69006-1080p-video.dtsi new file mode 100644 index 00000000..e3e84797 --- /dev/null +++ b/qcom/dsi-panel-r69006-1080p-video.dtsi @@ -0,0 +1,125 @@ +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *--------------------------------------------------------------------------- + */ + +&mdss_mdp { + dsi_r69006_1080p_video: qcom,mdss_dsi_r69006_1080p_video { + qcom,mdss-dsi-panel-name = "r69006 1080p video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <82>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <9>; + qcom,mdss-dsi-v-front-porch = <3>; + qcom,mdss-dsi-v-pulse-width = <15>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 06 + B3 05 10 00 00 00 + 29 01 00 00 00 00 03 B4 0c 00 + 29 01 00 00 00 00 04 B6 3b c3 00 + 23 01 00 00 00 00 02 C0 00 + 15 01 00 00 00 00 02 36 98 + 23 01 00 00 00 00 02 CC 04 + 29 01 00 00 00 00 20 + C1 84 00 10 EF 8B + F1 FF FF DF 9C C5 + 9A 73 8D AD 63 FE + FF FF CB F8 01 00 + AA 40 00 C2 01 08 + 00 01 + 29 01 00 00 00 00 0A + CB 0D FE 1F 2C 00 + 00 00 00 00 + 29 01 00 00 00 00 0B + C2 01 F7 80 04 63 + 00 60 00 01 30 + 29 01 00 00 00 00 07 + C3 55 01 00 01 00 + 00 + 29 01 00 00 00 00 12 + C4 70 00 00 00 00 + 00 00 00 00 02 01 + 00 05 01 00 00 00 + 29 01 00 00 00 00 0F + C6 59 07 4a 07 4a + 01 0E 01 02 01 02 + 09 15 07 + 29 01 00 00 00 00 1F + C7 00 30 32 34 42 + 4E 56 62 44 4A 54 + 62 6B 73 7F 08 30 + 32 34 42 4E 56 62 + 44 4A 54 62 6B 73 + 7F + 29 01 00 00 00 00 14 + C8 00 00 00 00 00 + FC 00 00 00 00 00 + FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 09 + C9 1F 68 1F 68 4C + 4C C4 11 + 29 01 00 00 00 00 11 + D0 33 01 91 0B D9 + 19 19 00 00 00 19 + 99 00 00 00 00 + 29 01 00 00 00 00 1D + D3 1B 3B BB AD A5 + 33 33 33 00 80 AD + A8 6f 6f 33 33 33 + F7 F2 1F 7D 7C FF + 0F 99 00 FF FF + 29 01 00 00 00 00 04 + D4 57 33 03 + 29 01 00 00 00 00 0C + D5 66 00 00 01 27 + 01 27 00 6D 00 6D + 23 01 00 00 00 00 02 D6 81 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 0A]; + qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-status-value = <0x1C>; + qcom,mdss-dsi-panel-max-error-count = <3>; + }; +}; diff --git a/qcom/dsi-panel-truly-720p-cmd.dtsi b/qcom/dsi-panel-truly-720p-cmd.dtsi new file mode 100644 index 00000000..e9227d98 --- /dev/null +++ b/qcom/dsi-panel-truly-720p-cmd.dtsi @@ -0,0 +1,243 @@ +&mdss_mdp { + dsi_truly_720_cmd: qcom,mdss_dsi_truly_720p_cmd { + qcom,mdss-dsi-panel-name = "truly 720p cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <6>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <32>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [87 2c 12 00 40 44 16 1e 17 03 + 04 00]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 f0 55 aa 52 + 08 00 + 29 01 00 00 00 00 03 b1 78 21 + 23 01 00 00 00 00 02 b6 0f + 29 01 00 00 00 00 03 bc 00 00 + 29 01 00 00 00 00 06 bd 02 67 20 20 00 + 29 01 00 00 00 00 0b e7 f2 e6 d8 cc bf b2 a5 99 99 95 + 29 01 00 00 00 00 0b e8 f2 e6 d8 cc bf b2 a5 99 99 95 + 29 01 00 00 00 00 06 f0 55 aa 52 08 01 + 29 01 00 00 00 00 03 bc a0 00 + 29 01 00 00 00 00 03 bd a0 00 + 23 01 00 00 00 00 02 ca 01 + 23 01 00 00 00 00 02 c0 0c + 23 01 00 00 00 00 02 be 4e + 29 01 00 00 00 00 03 b3 38 38 + 29 01 00 00 00 00 03 b4 11 11 + 29 01 00 00 00 00 03 b6 05 05 + 29 01 00 00 00 00 03 b9 45 45 + 29 01 00 00 00 00 03 ba 25 25 + 29 01 00 00 00 00 03 c4 11 11 + 23 01 00 00 00 00 02 c6 66 + 29 01 00 00 00 00 06 f0 55 aa 52 08 02 + 23 01 00 00 00 00 02 ee 00 + 29 01 00 00 00 00 11 b0 00 37 00 48 00 69 00 8a 00 ab 00 + cb 00 eb 01 1c + 29 01 00 00 00 00 11 b1 01 41 01 7c 01 aa 01 f3 02 2d 02 + 2e 02 63 02 9d + 29 01 00 00 00 00 11 b2 02 c3 02 f6 03 19 03 54 03 85 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 b3 03 e0 03 e8 + 29 01 00 00 00 00 11 bc 00 37 00 48 00 69 00 8a 00 ab 00 + cb 00 eb 01 1c + 29 01 00 00 00 00 11 bd 01 41 01 7c 01 aa 01 f3 02 2d 02 + 2e 02 63 02 9d + 29 01 00 00 00 00 11 be 02 c3 02 f6 03 19 03 54 03 85 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 bf 03 e0 03 e8 + 29 01 00 00 00 00 11 b4 00 d1 00 d7 00 e4 00 f1 00 fe 01 + 12 01 26 01 48 + 29 01 00 00 00 00 11 b5 01 64 01 95 01 bd 02 01 02 36 02 + 38 02 6c 02 a7 + 29 01 00 00 00 00 11 b6 02 ce 03 04 03 2b 03 5b 03 89 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 b7 03 e0 03 e8 + 29 01 00 00 00 00 11 c0 00 d1 00 d7 00 e4 00 f1 00 fe 01 + 12 01 26 01 48 + 29 01 00 00 00 00 11 c1 01 64 01 95 01 bd 02 01 02 36 02 + 38 02 6c 02 a7 + 29 01 00 00 00 00 11 c2 02 ce 03 04 03 2b 03 5b 03 89 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 c3 03 e0 03 e8 + 29 01 00 00 00 00 11 b8 00 37 00 45 00 61 00 7d 00 9a 00 + bb 00 dc 01 0b + 29 01 00 00 00 00 11 b9 01 31 01 6e 01 9e 01 ea 02 24 02 + 25 02 58 02 90 + 29 01 00 00 00 00 11 ba 02 b4 02 e4 03 04 03 44 03 7f 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 bb 03 e0 03 e8 + 29 01 00 00 00 00 11 c4 00 37 00 45 00 61 00 7d 00 9a 00 + bb 00 dc 01 0b + 29 01 00 00 00 00 11 c5 01 31 01 6e 01 9e 01 ea 02 24 02 + 25 02 58 02 90 + 29 01 00 00 00 00 11 c6 02 b4 02 e4 03 04 03 44 03 7f 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 c7 03 e0 03 e8 + 29 01 00 00 00 00 06 f0 55 aa 52 08 06 + 29 01 00 00 00 00 03 b0 29 2a + 29 01 00 00 00 00 03 b1 10 12 + 29 01 00 00 00 00 03 b2 14 16 + 29 01 00 00 00 00 03 b3 18 1a + 29 01 00 00 00 00 03 b4 02 04 + 29 01 00 00 00 00 03 b5 34 34 + 29 01 00 00 00 00 03 b6 34 2e + 29 01 00 00 00 00 03 b7 2e 2e + 29 01 00 00 00 00 03 b8 34 00 + 29 01 00 00 00 00 03 b9 34 34 + 29 01 00 00 00 00 03 ba 34 34 + 29 01 00 00 00 00 03 bb 01 34 + 29 01 00 00 00 00 03 bc 2e 2e + 29 01 00 00 00 00 03 bd 2e 34 + 29 01 00 00 00 00 03 be 34 34 + 29 01 00 00 00 00 03 bf 05 03 + 29 01 00 00 00 00 03 c0 1b 19 + 29 01 00 00 00 00 03 c1 17 15 + 29 01 00 00 00 00 03 c2 13 11 + 29 01 00 00 00 00 03 c3 2a 29 + 29 01 00 00 00 00 03 e5 2e 2e + 29 01 00 00 00 00 03 c4 29 2a + 29 01 00 00 00 00 03 c5 1b 19 + 29 01 00 00 00 00 03 c6 17 15 + 29 01 00 00 00 00 03 c7 13 11 + 29 01 00 00 00 00 03 c8 01 05 + 29 01 00 00 00 00 03 c9 34 34 + 29 01 00 00 00 00 03 ca 34 2e + 29 01 00 00 00 00 03 cb 2e 2e + 29 01 00 00 00 00 03 cc 34 03 + 29 01 00 00 00 00 03 cd 34 34 + 29 01 00 00 00 00 03 ce 34 34 + 29 01 00 00 00 00 03 cf 02 34 + 29 01 00 00 00 00 03 d0 2e 2e + 29 01 00 00 00 00 03 d1 2e 34 + 29 01 00 00 00 00 03 d2 34 34 + 29 01 00 00 00 00 03 d3 04 00 + 29 01 00 00 00 00 03 d4 10 12 + 29 01 00 00 00 00 03 d5 14 16 + 29 01 00 00 00 00 03 d6 18 1a + 29 01 00 00 00 00 03 d7 2a 29 + 29 01 00 00 00 00 03 e6 2e 2e + 29 01 00 00 00 00 06 d8 00 00 00 54 00 + 29 01 00 00 00 00 06 d9 00 15 00 00 00 + 23 01 00 00 00 00 02 e7 00 + 29 01 00 00 00 00 06 f0 55 aa 52 08 03 + 29 01 00 00 00 00 03 b1 00 00 + 29 01 00 00 00 00 03 b0 00 00 + 29 01 00 00 00 00 06 b2 05 00 00 00 00 + 29 01 00 00 00 00 06 b3 05 00 00 00 00 + 29 01 00 00 00 00 06 b4 05 00 00 00 00 + 29 01 00 00 00 00 06 b5 05 00 17 00 00 + 29 01 00 00 00 00 06 b6 12 00 19 00 00 + 29 01 00 00 00 00 06 b7 12 00 19 00 00 + 29 01 00 00 00 00 06 b8 12 00 19 00 00 + 29 01 00 00 00 00 06 b9 12 00 19 00 00 + 29 01 00 00 00 00 06 ba 57 00 00 00 00 + 29 01 00 00 00 00 06 bb 57 00 00 00 00 + 29 01 00 00 00 00 06 bc 75 00 1a 00 00 + 29 01 00 00 00 00 06 bd 53 00 1a 00 00 + 29 01 00 00 00 00 05 c0 00 34 00 00 + 29 01 00 00 00 00 05 c1 00 34 00 00 + 29 01 00 00 00 00 05 c2 00 34 00 00 + 29 01 00 00 00 00 05 c3 00 34 00 00 + 23 01 00 00 00 00 02 c4 20 + 23 01 00 00 00 00 02 c5 00 + 23 01 00 00 00 00 02 c6 00 + 23 01 00 00 00 00 02 c7 00 + 29 01 00 00 00 00 06 f0 55 aa 52 08 05 + 23 01 00 00 00 00 02 ed 30 + 29 01 00 00 00 00 03 b0 17 06 + 23 01 00 00 00 00 02 b8 08 + 29 01 00 00 00 00 06 bd 03 07 00 03 00 + 29 01 00 00 00 00 03 b1 17 06 + 23 01 00 00 00 00 02 b9 00 + 29 01 00 00 00 00 03 b2 00 00 + 23 01 00 00 00 00 02 ba 00 + 29 01 00 00 00 00 03 b3 17 06 + 23 01 00 00 00 00 02 bb 0a + 29 01 00 00 00 00 03 b4 17 06 + 29 01 00 00 00 00 03 b5 17 06 + 29 01 00 00 00 00 03 b6 14 03 + 29 01 00 00 00 00 03 b7 00 00 + 23 01 00 00 00 00 02 bc 02 + 23 01 00 00 00 00 02 e5 06 + 23 01 00 00 00 00 02 e6 06 + 23 01 00 00 00 00 02 e7 00 + 23 01 00 00 00 00 02 e8 06 + 23 01 00 00 00 00 02 e9 06 + 23 01 00 00 00 00 02 ea 06 + 23 01 00 00 00 00 02 eb 00 + 23 01 00 00 00 00 02 ec 00 + 23 01 00 00 00 00 02 c0 07 + 23 01 00 00 00 00 02 c1 80 + 23 01 00 00 00 00 02 c2 a4 + 23 01 00 00 00 00 02 c3 05 + 23 01 00 00 00 00 02 c4 00 + 23 01 00 00 00 00 02 c5 02 + 23 01 00 00 00 00 02 c6 22 + 23 01 00 00 00 00 02 c7 03 + 29 01 00 00 00 00 03 c8 05 30 + 29 01 00 00 00 00 03 c9 01 31 + 29 01 00 00 00 00 03 ca 03 21 + 29 01 00 00 00 00 03 cb 01 20 + 29 01 00 00 00 00 06 d1 00 05 09 07 10 + 29 01 00 00 00 00 06 d2 10 05 0e 03 10 + 29 01 00 00 00 00 06 d3 20 00 48 07 10 + 29 01 00 00 00 00 06 d4 30 00 43 07 10 + 23 01 00 00 00 00 02 d0 00 + 29 01 00 00 00 00 04 cc 00 00 3e + 29 01 00 00 00 00 04 cd 00 00 3e + 29 01 00 00 00 00 04 ce 00 00 02 + 29 01 00 00 00 00 04 cf 00 00 02 + 23 01 00 00 00 00 02 6f 11 + 23 01 00 00 00 00 02 f3 01 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 2c + 15 01 00 00 00 00 02 55 03 + 15 01 00 00 c8 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 0a 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + }; +}; diff --git a/qcom/dsi-panel-truly-720p-video.dtsi b/qcom/dsi-panel-truly-720p-video.dtsi new file mode 100644 index 00000000..715b49bb --- /dev/null +++ b/qcom/dsi-panel-truly-720p-video.dtsi @@ -0,0 +1,237 @@ +&mdss_mdp { + dsi_truly_720_vid: qcom,mdss_dsi_truly_720p_video { + qcom,mdss-dsi-panel-name = "truly 720p video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <6>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <32>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [87 2c 12 00 40 44 16 1e 17 03 + 04 00]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 f0 55 aa 52 + 08 00 + 29 01 00 00 00 00 03 b1 78 21 + 23 01 00 00 00 00 02 b6 0f + 29 01 00 00 00 00 03 bc 00 00 + 29 01 00 00 00 00 06 bd 02 b0 1e 1e 00 + 29 01 00 00 00 00 0b e7 f2 e6 d8 cc bf b2 a5 99 99 95 + 29 01 00 00 00 00 0b e8 f2 e6 d8 cc bf b2 a5 99 99 95 + 29 01 00 00 00 00 06 f0 55 aa 52 08 01 + 29 01 00 00 00 00 03 bc a0 00 + 29 01 00 00 00 00 03 bd a0 00 + 23 01 00 00 00 00 02 ca 01 + 23 01 00 00 00 00 02 c0 0c + 23 01 00 00 00 00 02 be 4e + 29 01 00 00 00 00 03 b3 38 38 + 29 01 00 00 00 00 03 b4 11 11 + 29 01 00 00 00 00 03 b6 05 05 + 29 01 00 00 00 00 03 b9 45 45 + 29 01 00 00 00 00 03 ba 25 25 + 29 01 00 00 00 00 03 c4 11 11 + 23 01 00 00 00 00 02 c6 66 + 29 01 00 00 00 00 06 f0 55 aa 52 08 02 + 23 01 00 00 00 00 02 ee 00 + 29 01 00 00 00 00 11 b0 00 37 00 48 00 69 00 8a 00 ab 00 + cb 00 eb 01 1c + 29 01 00 00 00 00 11 b1 01 41 01 7c 01 aa 01 f3 02 2d 02 + 2e 02 63 02 9d + 29 01 00 00 00 00 11 b2 02 c3 02 f6 03 19 03 54 03 85 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 b3 03 e0 03 e8 + 29 01 00 00 00 00 11 bc 00 37 00 48 00 69 00 8a 00 ab 00 + cb 00 eb 01 1c + 29 01 00 00 00 00 11 bd 01 41 01 7c 01 aa 01 f3 02 2d 02 + 2e 02 63 02 9d + 29 01 00 00 00 00 11 be 02 c3 02 f6 03 19 03 54 03 85 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 bf 03 e0 03 e8 + 29 01 00 00 00 00 11 b4 00 d1 00 d7 00 e4 00 f1 00 fe 01 + 12 01 26 01 48 + 29 01 00 00 00 00 11 b5 01 64 01 95 01 bd 02 01 02 36 02 + 38 02 6c 02 a7 + 29 01 00 00 00 00 11 b6 02 ce 03 04 03 2b 03 5b 03 89 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 b7 03 e0 03 e8 + 29 01 00 00 00 00 11 c0 00 d1 00 d7 00 e4 00 f1 00 fe 01 + 12 01 26 01 48 + 29 01 00 00 00 00 11 c1 01 64 01 95 01 bd 02 01 02 36 02 + 38 02 6c 02 a7 + 29 01 00 00 00 00 11 c2 02 ce 03 04 03 2b 03 5b 03 89 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 c3 03 e0 03 e8 + 29 01 00 00 00 00 11 b8 00 37 00 45 00 61 00 7d 00 9a 00 + bb 00 dc 01 0b + 29 01 00 00 00 00 11 b9 01 31 01 6e 01 9e 01 ea 02 24 02 + 25 02 58 02 90 + 29 01 00 00 00 00 11 ba 02 b4 02 e4 03 04 03 44 03 7f 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 bb 03 e0 03 e8 + 29 01 00 00 00 00 11 c4 00 37 00 45 00 61 00 7d 00 9a 00 + bb 00 dc 01 0b + 29 01 00 00 00 00 11 c5 01 31 01 6e 01 9e 01 ea 02 24 02 + 25 02 58 02 90 + 29 01 00 00 00 00 11 c6 02 b4 02 e4 03 04 03 44 03 7f 03 + b2 03 c1 03 d1 + 29 01 00 00 00 00 05 c7 03 e0 03 e8 + 29 01 00 00 00 00 06 f0 55 aa 52 08 06 + 29 01 00 00 00 00 03 b0 29 2a + 29 01 00 00 00 00 03 b1 10 12 + 29 01 00 00 00 00 03 b2 14 16 + 29 01 00 00 00 00 03 b3 18 1a + 29 01 00 00 00 00 03 b4 02 04 + 29 01 00 00 00 00 03 b5 34 34 + 29 01 00 00 00 00 03 b6 34 2e + 29 01 00 00 00 00 03 b7 2e 2e + 29 01 00 00 00 00 03 b8 34 00 + 29 01 00 00 00 00 03 b9 34 34 + 29 01 00 00 00 00 03 ba 34 34 + 29 01 00 00 00 00 03 bb 01 34 + 29 01 00 00 00 00 03 bc 2e 2e + 29 01 00 00 00 00 03 bd 2e 34 + 29 01 00 00 00 00 03 be 34 34 + 29 01 00 00 00 00 03 bf 05 03 + 29 01 00 00 00 00 03 c0 1b 19 + 29 01 00 00 00 00 03 c1 17 15 + 29 01 00 00 00 00 03 c2 13 11 + 29 01 00 00 00 00 03 c3 2a 29 + 29 01 00 00 00 00 03 e5 2e 2e + 29 01 00 00 00 00 03 c4 29 2a + 29 01 00 00 00 00 03 c5 1b 19 + 29 01 00 00 00 00 03 c6 17 15 + 29 01 00 00 00 00 03 c7 13 11 + 29 01 00 00 00 00 03 c8 01 05 + 29 01 00 00 00 00 03 c9 34 34 + 29 01 00 00 00 00 03 ca 34 2e + 29 01 00 00 00 00 03 cb 2e 2e + 29 01 00 00 00 00 03 cc 34 03 + 29 01 00 00 00 00 03 cd 34 34 + 29 01 00 00 00 00 03 ce 34 34 + 29 01 00 00 00 00 03 cf 02 34 + 29 01 00 00 00 00 03 d0 2e 2e + 29 01 00 00 00 00 03 d1 2e 34 + 29 01 00 00 00 00 03 d2 34 34 + 29 01 00 00 00 00 03 d3 04 00 + 29 01 00 00 00 00 03 d4 10 12 + 29 01 00 00 00 00 03 d5 14 16 + 29 01 00 00 00 00 03 d6 18 1a + 29 01 00 00 00 00 03 d7 2a 29 + 29 01 00 00 00 00 03 e6 2e 2e + 29 01 00 00 00 00 06 d8 00 00 00 54 00 + 29 01 00 00 00 00 06 d9 00 15 00 00 00 + 23 01 00 00 00 00 02 e7 00 + 29 01 00 00 00 00 06 f0 55 aa 52 08 03 + 29 01 00 00 00 00 03 b1 00 00 + 29 01 00 00 00 00 03 b0 00 00 + 29 01 00 00 00 00 06 b2 05 00 00 00 00 + 29 01 00 00 00 00 06 b3 05 00 00 00 00 + 29 01 00 00 00 00 06 b4 05 00 00 00 00 + 29 01 00 00 00 00 06 b5 05 00 17 00 00 + 29 01 00 00 00 00 06 b6 12 00 19 00 00 + 29 01 00 00 00 00 06 b7 12 00 19 00 00 + 29 01 00 00 00 00 06 b8 12 00 19 00 00 + 29 01 00 00 00 00 06 b9 12 00 19 00 00 + 29 01 00 00 00 00 06 ba 57 00 00 00 00 + 29 01 00 00 00 00 06 bb 57 00 00 00 00 + 29 01 00 00 00 00 06 bc 75 00 1a 00 00 + 29 01 00 00 00 00 06 bd 53 00 1a 00 00 + 29 01 00 00 00 00 05 c0 00 34 00 00 + 29 01 00 00 00 00 05 c1 00 34 00 00 + 29 01 00 00 00 00 05 c2 00 34 00 00 + 29 01 00 00 00 00 05 c3 00 34 00 00 + 23 01 00 00 00 00 02 c4 20 + 23 01 00 00 00 00 02 c5 00 + 23 01 00 00 00 00 02 c6 00 + 23 01 00 00 00 00 02 c7 00 + 29 01 00 00 00 00 06 f0 55 aa 52 08 05 + 23 01 00 00 00 00 02 ed 30 + 29 01 00 00 00 00 03 b0 17 06 + 23 01 00 00 00 00 02 b8 08 + 29 01 00 00 00 00 06 bd 03 07 00 03 00 + 29 01 00 00 00 00 03 b1 17 06 + 23 01 00 00 00 00 02 b9 00 + 29 01 00 00 00 00 03 b2 00 00 + 23 01 00 00 00 00 02 ba 00 + 29 01 00 00 00 00 03 b3 17 06 + 23 01 00 00 00 00 02 bb 0a + 29 01 00 00 00 00 03 b4 17 06 + 29 01 00 00 00 00 03 b5 17 06 + 29 01 00 00 00 00 03 b6 14 03 + 29 01 00 00 00 00 03 b7 00 00 + 23 01 00 00 00 00 02 bc 02 + 23 01 00 00 00 00 02 e5 06 + 23 01 00 00 00 00 02 e6 06 + 23 01 00 00 00 00 02 e7 00 + 23 01 00 00 00 00 02 e8 06 + 23 01 00 00 00 00 02 e9 06 + 23 01 00 00 00 00 02 ea 06 + 23 01 00 00 00 00 02 eb 00 + 23 01 00 00 00 00 02 ec 00 + 23 01 00 00 00 00 02 c0 07 + 23 01 00 00 00 00 02 c1 80 + 23 01 00 00 00 00 02 c2 a4 + 23 01 00 00 00 00 02 c3 05 + 23 01 00 00 00 00 02 c4 00 + 23 01 00 00 00 00 02 c5 02 + 23 01 00 00 00 00 02 c6 22 + 23 01 00 00 00 00 02 c7 03 + 29 01 00 00 00 00 03 c8 05 30 + 29 01 00 00 00 00 03 c9 01 31 + 29 01 00 00 00 00 03 ca 03 21 + 29 01 00 00 00 00 03 cb 01 20 + 29 01 00 00 00 00 06 d1 00 05 09 07 10 + 29 01 00 00 00 00 06 d2 10 05 0e 03 10 + 29 01 00 00 00 00 06 d3 20 00 48 07 10 + 29 01 00 00 00 00 06 d4 30 00 43 07 10 + 23 01 00 00 00 00 02 d0 00 + 29 01 00 00 00 00 04 cc 00 00 3e + 29 01 00 00 00 00 04 cd 00 00 3e + 29 01 00 00 00 00 04 ce 00 00 02 + 29 01 00 00 00 00 04 cf 00 00 02 + 23 01 00 00 00 00 02 6f 11 + 23 01 00 00 00 00 02 f3 01 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 2c + 15 01 00 00 00 00 02 55 03 + 15 01 00 00 c8 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 0a 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-post-init-delay = <1>; + }; +}; diff --git a/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi b/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi new file mode 100644 index 00000000..570198a4 --- /dev/null +++ b/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi @@ -0,0 +1,71 @@ +qcom,3388014_i13z5p_680mah_averaged_masterslave_mar26th2018 { + qcom,fastchg-current-ma = <480>; + /* #3388014_I13Z5P_680mAh_averaged_MasterSlave_Mar26th2018*/ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,nom-batt-capacity-mah = <680>; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <3435>; + qcom,battery-type = + "3388014_i13z5p_680mah_averaged_masterslave_mar26th2018"; + qcom,checksum = <0x8C0B>; + qcom,gui-version = "PM660GUI - 0.0.0.45"; + qcom,fg-profile-data = [ + 5E 24 56 0C + E9 12 B0 0D + 05 1D 59 01 + F8 05 8C 02 + 24 1B CF 13 + D6 35 86 3B + A2 00 00 00 + 1A 00 00 00 + 00 00 1F CD + 57 AD 6C CA + 47 00 08 00 + FD DA E6 ED + 09 EC 03 E2 + 58 07 89 01 + 21 14 BA 5A + 0A 06 09 20 + 27 00 14 00 + 55 20 C3 04 + 3A 0B 7C 05 + 01 1D 39 02 + 41 0D 1A 0B + 89 18 A6 2B + 2E 54 B7 72 + 75 00 00 00 + 07 00 00 00 + 00 00 9C CC + DE C3 51 A4 + 48 00 00 00 + 77 EB E6 ED + 6F EC D3 D2 + FF 07 DF F3 + 91 E3 56 1A + 99 33 CC FF + 07 10 00 00 + BB 02 66 46 + 48 00 40 00 + D8 02 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + ]; +}; diff --git a/qcom/msm-arm-smmu-8917.dtsi b/qcom/msm-arm-smmu-8917.dtsi new file mode 100644 index 00000000..adea3a4d --- /dev/null +++ b/qcom/msm-arm-smmu-8917.dtsi @@ -0,0 +1,81 @@ +&soc { + gfx_iommu: qcom,iommu@1f00000 { + status = "ok"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1f00000 0x10000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <1>; + qcom,tz-device-id = "GPU"; + qcom,skip-init; + qcom,enable-static-cb; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,regulator-names = "vdd"; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; + + apps_iommu: qcom,iommu@1e00000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1e00000 0x40000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,tz-device-id = "APPS"; + qcom,skip-init; + qcom,disable-atos; + ranges; + qcom,enable-static-cb; + qcom,use-3-lvl-tables; + qcom,regulator-names = "vdd"; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; +}; diff --git a/qcom/msm-arm-smmu-8937.dtsi b/qcom/msm-arm-smmu-8937.dtsi new file mode 100644 index 00000000..0ca21049 --- /dev/null +++ b/qcom/msm-arm-smmu-8937.dtsi @@ -0,0 +1,89 @@ +&soc { + kgsl_smmu: arm,smmu-kgsl@1c40000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + qcom,tz-device-id = "GPU"; + reg = <0x1c40000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <0>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,enable-smmu-halt; + qcom,skip-init; + vdd-supply = <&gdsc_oxili_cx>; + qcom,regulator-names = "vdd"; + clocks = <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>; + clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk"; + }; + + /* A test device to test the SMMU operation */ + kgsl_iommu_test_device0 { + status = "disabled"; + compatible = "iommu-debug-test"; + /* The SID should be valid one to get the proper + *SMR,S2CR indices. + */ + iommus = <&kgsl_smmu 0x0>; + }; + + apps_iommu: qcom,iommu@1e00000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1e00000 0x40000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,tz-device-id = "APPS"; + qcom,skip-init; + qcom,enable-static-cb; + qcom,use-3-lvl-tables; + qcom,disable-atos; + qcom,regulator-names = "vdd"; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; +}; + +#include "msm-arm-smmu-impl-defs-8937.dtsi" diff --git a/qcom/msm-arm-smmu-impl-defs-8937.dtsi b/qcom/msm-arm-smmu-impl-defs-8937.dtsi new file mode 100644 index 00000000..6ee2f98e --- /dev/null +++ b/qcom/msm-arm-smmu-impl-defs-8937.dtsi @@ -0,0 +1,12 @@ +&kgsl_smmu { + attach-impl-defs = <0x6000 0x270>, + <0x6060 0x1055>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x10800>, + <0x6930 0x400>, + <0x6960 0xffffffff>, + <0x6b64 0xa0000>, + <0x6b68 0xaaab92a>; +}; diff --git a/qcom/msm-gdsc-8916.dtsi b/qcom/msm-gdsc-8916.dtsi new file mode 100644 index 00000000..89a35d77 --- /dev/null +++ b/qcom/msm-gdsc-8916.dtsi @@ -0,0 +1,78 @@ +&soc { + gdsc_venus: qcom,gdsc@184c018 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0x184c018 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@184d078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0x184d078 0x4>; + status = "disabled"; + }; + + gdsc_jpeg: qcom,gdsc@185701c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_jpeg"; + reg = <0x185701c 0x4>; + status = "disabled"; + }; + + gdsc_vfe: qcom,gdsc@1858034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe"; + reg = <0x1858034 0x4>; + status = "disabled"; + }; + + gdsc_vfe1: qcom,gdsc@185806c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe1"; + reg = <0x185806c 0x4>; + status = "disabled"; + }; + + gdsc_cpp: qcom,gdsc@1858078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_cpp"; + reg = <0x1858078 0x4>; + status = "disabled"; + }; + + gdsc_oxili_gx: qcom,gdsc@185901c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + reg = <0x185901c 0x4>; + status = "disabled"; + }; + + gdsc_venus_core0: qcom,gdsc@184c028 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core0"; + reg = <0x184c028 0x4>; + status = "disabled"; + }; + + gdsc_venus_core1: qcom,gdsc@184c030 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core1"; + reg = <0x184c030 0x4>; + status = "disabled"; + }; + + gdsc_oxili_cx: qcom,gdsc@185904c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_cx"; + reg = <0x185904c 0x4>; + status = "disabled"; + }; + + gdsc_usb30: qcom,gdsc@183f078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x183f078 0x4>; + status = "disabled"; + }; +}; diff --git a/qcom/msm8917-bus.dtsi b/qcom/msm8917-bus.dtsi new file mode 100644 index 00000000..2ce4843d --- /dev/null +++ b/qcom/msm8917-bus.dtsi @@ -0,0 +1,932 @@ +#include <dt-bindings/msm/msm-bus-ids.h> + +&soc { + /* Version = 11 */ + ad_hoc_bus: ad-hoc-bus@580000 { + compatible = "qcom,msm-bus-device"; + reg = <0x580000 0x16080>, + <0x580000 0x16080>, + <0x400000 0x5a000>, + <0x500000 0x13080>; + reg-names = "snoc-base", "snoc-mm-base", + "bimc-base", "pcnoc-base"; + + /* Buses */ + fab_bimc: fab-bimc { + cell-id = <MSM_BUS_FAB_BIMC>; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <154>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc BIMC_MSMBUS_CLK>, + <&rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_pcnoc: fab-pcnoc { + cell-id = <MSM_BUS_FAB_PERIPH_NOC>; + label = "fab-pcnoc"; + qcom,fab-dev; + qcom,base-name = "pcnoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc PNOC_MSMBUS_CLK>, + <&rpmcc PNOC_MSMBUS_A_CLK>; + }; + + fab_snoc: fab-snoc { + cell-id = <MSM_BUS_FAB_SYS_NOC>; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc SNOC_MSMBUS_CLK>, + <&rpmcc SNOC_MSMBUS_A_CLK>; + }; + + fab_snoc_mm: fab-snoc-mm { + cell-id = <MSM_BUS_FAB_MMSS_NOC>; + label = "fab-snoc-mm"; + qcom,fab-dev; + qcom,base-name = "snoc-mm-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + qcom,util-fact = <154>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc SYSMMNOC_MSMBUS_CLK>, + <&rpmcc SYSMMNOC_MSMBUS_A_CLK>; + }; + + /* BIMC Masters */ + mas_apps_proc: mas-apps-proc { + cell-id = <MSM_BUS_MASTER_AMPSS_M0>; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>; + }; + + mas_oxili: mas-oxili { + cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>; + label = "mas-oxili"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>; + }; + + mas_snoc_bimc_0: mas-snoc-bimc-0 { + cell-id = <MSM_BUS_SNOC_BIMC_0_MAS>; + label = "mas-snoc-bimc-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_0>; + }; + + mas_snoc_bimc_2: mas-snoc-bimc-2 { + cell-id = <MSM_BUS_SNOC_BIMC_2_MAS>; + label = "mas-snoc-bimc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_2>; + }; + + mas_snoc_bimc_1: mas-snoc-bimc-1 { + cell-id = <MSM_BUS_SNOC_BIMC_1_MAS>; + label = "mas-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_1>; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = <MSM_BUS_MASTER_TCU_0>; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <2>; + qcom,prio-rd = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>; + }; + + /* PCNOC Masters */ + mas_spdm: mas-spdm { + cell-id = <MSM_BUS_MASTER_SPDM>; + label = "mas-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&pcnoc_m_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SPDM>; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = <MSM_BUS_MASTER_BLSP_1>; + label = "mas-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = <MSM_BUS_MASTER_BLSP_2>; + label = "mas-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>; + }; + + mas_usb_hs1: mas-usb-hs1 { + cell-id = <MSM_BUS_MASTER_USB_HS>; + label = "mas-usb-hs1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "fixed"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>; + }; + + mas_xi_usb_hs1: mas-xi-usb-hs1 { + cell-id = <MSM_BUS_MASTER_XM_USB_HS1>; + label = "mas-xi-usb-hs1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>; + }; + + mas_crypto: mas-crypto { + cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>; + label = "mas-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>; + }; + + mas_sdcc_1: mas-sdcc-1 { + cell-id = <MSM_BUS_MASTER_SDCC_1>; + label = "mas-sdcc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = <MSM_BUS_MASTER_SDCC_2>; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>; + }; + + mas_snoc_pcnoc: mas-snoc-pcnoc { + cell-id = <MSM_BUS_SNOC_PNOC_MAS>; + label = "mas-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_s_7 + &pcnoc_int_2 &pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>; + }; + + /* SNOC Masters */ + mas_qdss_bam: mas-qdss-bam { + cell-id = <MSM_BUS_MASTER_QDSS_BAM>; + label = "mas-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <11>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = <MSM_BUS_BIMC_SNOC_MAS>; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&snoc_int_0 + &snoc_int_1 &snoc_int_2>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>; + }; + + mas_jpeg: mas-jpeg { + cell-id = <MSM_BUS_MASTER_JPEG>; + label = "mas-jpeg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_JPEG>; + }; + + mas_mdp: mas-mdp { + cell-id = <MSM_BUS_MASTER_MDP_PORT0>; + label = "mas-mdp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <7>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_MDP>; + }; + + mas_pcnoc_snoc: mas-pcnoc-snoc { + cell-id = <MSM_BUS_PNOC_SNOC_MAS>; + label = "mas-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,qos-mode = "fixed"; + qcom,connections = <&snoc_int_0 + &snoc_int_1 &slv_snoc_bimc_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>; + qcom,blacklist = <&slv_snoc_pcnoc>; + }; + + mas_venus: mas-venus { + cell-id = <MSM_BUS_MASTER_VIDEO_P0>; + label = "mas-venus"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <8>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>; + }; + + mas_vfe0: mas-vfe0 { + cell-id = <MSM_BUS_MASTER_VFE>; + label = "mas-vfe0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <9>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VFE>; + }; + + mas_vfe1: mas-vfe1 { + cell-id = <MSM_BUS_MASTER_VFE1>; + label = "mas-vfe1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <13>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VFE1>; + }; + + mas_cpp: mas-cpp { + cell-id = <MSM_BUS_MASTER_CPP>; + label = "mas-cpp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_CPP>; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = <MSM_BUS_MASTER_QDSS_ETR>; + label = "mas-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <10>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>; + }; + + /* Internal nodes */ + pcnoc_m_0: pcnoc-m-0 { + cell-id = <MSM_BUS_PNOC_M_0>; + label = "pcnoc-m-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>; + }; + + pcnoc_m_1: pcnoc-m-1 { + cell-id = <MSM_BUS_PNOC_M_1>; + label = "pcnoc-m-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>; + }; + + pcnoc_int_0: pcnoc-int-0 { + cell-id = <MSM_BUS_PNOC_INT_0>; + label = "pcnoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc + &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>; + }; + + pcnoc_int_1: pcnoc-int-1 { + cell-id = <MSM_BUS_PNOC_INT_1>; + label = "pcnoc-int-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc + &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_1>; + }; + + pcnoc_int_2: pcnoc-int-2 { + cell-id = <MSM_BUS_PNOC_INT_2>; + label = "pcnoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_6 &pcnoc_s_8>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>; + }; + + pcnoc_int_3: pcnoc-int-3 { + cell-id = <MSM_BUS_PNOC_INT_3>; + label = "pcnoc-int-3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = < &pcnoc_s_1 &pcnoc_s_0 &pcnoc_s_4 + &slv_gpu_cfg &slv_tcu >; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>; + }; + + pcnoc_s_0: pcnoc-s-0 { + cell-id = <MSM_BUS_PNOC_SLV_0>; + label = "pcnoc-s-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_spdm &slv_pdm &slv_prng + &slv_sdcc_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>; + }; + + pcnoc_s_1: pcnoc-s-1 { + cell-id = <MSM_BUS_PNOC_SLV_1>; + label = "pcnoc-s-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tcsr>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>; + }; + + pcnoc_s_2: pcnoc-s-2 { + cell-id = <MSM_BUS_PNOC_SLV_2>; + label = "pcnoc-s-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_snoc_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>; + }; + + pcnoc_s_3: pcnoc-s-3 { + cell-id = <MSM_BUS_PNOC_SLV_3>; + label = "pcnoc-s-3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_message_ram>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>; + }; + + pcnoc_s_4: pcnoc-s-4 { + cell-id = <MSM_BUS_PNOC_SLV_4>; + label = "pcnoc-s-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_camera_ss_cfg + &slv_disp_ss_cfg &slv_venus_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>; + }; + + pcnoc_s_6: pcnoc-s-6 { + cell-id = <MSM_BUS_PNOC_SLV_6>; + label = "pcnoc-s-6"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tlmm &slv_blsp_1 &slv_blsp_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>; + }; + + pcnoc_s_7: pcnoc-s-7 { + cell-id = <MSM_BUS_PNOC_SLV_7>; + label = "pcnoc-s-7"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_sdcc_1 &slv_pmic_arb>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>; + }; + + pcnoc_s_8: pcnoc-s-8 { + cell-id = <MSM_BUS_PNOC_SLV_8>; + label = "pcnoc-s-8"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_usb_hs &slv_crypto_0_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>; + }; + + qdss_int: qdss-int { + cell-id = <MSM_BUS_SNOC_QDSS_INT>; + label = "qdss-int"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&snoc_int_1 &slv_snoc_bimc_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>; + }; + + snoc_int_0: snoc-int-0 { + cell-id = <MSM_BUS_SNOC_INT_0>; + label = "snoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_lpass + &slv_wcss &slv_kpss_ahb>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>; + }; + + snoc_int_1: snoc-int-1 { + cell-id = <MSM_BUS_SNOC_INT_1>; + label = "snoc-int-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qdss_stm + &slv_imem &slv_snoc_pcnoc>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>; + }; + + snoc_int_2: snoc-int-2 { + cell-id = <MSM_BUS_SNOC_INT_2>; + label = "snoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_cats_0 &slv_cats_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_2>; + }; + + /* Slaves */ + slv_ebi:slv-ebi { + cell-id = <MSM_BUS_SLAVE_EBI_CH0>; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = <MSM_BUS_BIMC_SNOC_SLV>; + label = "slv-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = <MSM_BUS_SLAVE_SDCC_2>; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>; + }; + + slv_spdm:slv-spdm { + cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>; + }; + + slv_pdm:slv-pdm { + cell-id = <MSM_BUS_SLAVE_PDM>; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PDM>; + }; + + slv_prng:slv-prng { + cell-id = <MSM_BUS_SLAVE_PRNG>; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>; + }; + + slv_tcsr:slv-tcsr { + cell-id = <MSM_BUS_SLAVE_TCSR>; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = <MSM_BUS_SLAVE_SNOC_CFG>; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>; + }; + + slv_message_ram:slv-message-ram { + cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>; + }; + + slv_camera_ss_cfg:slv-camera-ss-cfg { + cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>; + label = "slv-camera-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>; + }; + + slv_disp_ss_cfg:slv-disp-ss-cfg { + cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>; + label = "slv-disp-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>; + }; + + slv_venus_cfg:slv-venus-cfg { + cell-id = <MSM_BUS_SLAVE_VENUS_CFG>; + label = "slv-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>; + }; + + slv_gpu_cfg:slv-gpu-cfg { + cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>; + label = "slv-gpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>; + }; + + slv_tlmm:slv-tlmm { + cell-id = <MSM_BUS_SLAVE_TLMM>; + label = "slv-tlmm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = <MSM_BUS_SLAVE_BLSP_1>; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = <MSM_BUS_SLAVE_BLSP_2>; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = <MSM_BUS_SLAVE_PMIC_ARB>; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>; + }; + + slv_sdcc_1:slv-sdcc-1 { + cell-id = <MSM_BUS_SLAVE_SDCC_1>; + label = "slv-sdcc-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>; + }; + + slv_crypto_0_cfg:slv-crypto-0-cfg { + cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>; + label = "slv-crypto-0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>; + }; + + slv_usb_hs:slv-usb-hs { + cell-id = <MSM_BUS_SLAVE_USB_HS>; + label = "slv-usb-hs"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>; + }; + + slv_tcu:slv-tcu { + cell-id = <MSM_BUS_SLAVE_TCU>; + label = "slv-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCU>; + }; + + slv_pcnoc_snoc:slv-pcnoc-snoc { + cell-id = <MSM_BUS_PNOC_SNOC_SLV>; + label = "slv-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,connections = <&mas_pcnoc_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>; + }; + + slv_kpss_ahb:slv-kpss-ahb { + cell-id = <MSM_BUS_SLAVE_APPSS>; + label = "slv-kpss-ahb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>; + }; + + slv_wcss:slv-wcss { + cell-id = <MSM_BUS_SLAVE_WCSS>; + label = "slv-wcss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_WCSS>; + }; + + slv_snoc_bimc_0:slv-snoc-bimc-0 { + cell-id = <MSM_BUS_SNOC_BIMC_0_SLV>; + label = "slv-snoc-bimc-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,connections = <&mas_snoc_bimc_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_0>; + }; + + slv_snoc_bimc_1:slv-snoc-bimc-1 { + cell-id = <MSM_BUS_SNOC_BIMC_1_SLV>; + label = "slv-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_1>; + }; + + slv_snoc_bimc_2:slv-snoc-bimc-2 { + cell-id = <MSM_BUS_SNOC_BIMC_2_SLV>; + label = "slv-snoc-bimc-2"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,connections = <&mas_snoc_bimc_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_2>; + }; + + slv_imem:slv-imem { + cell-id = <MSM_BUS_SLAVE_OCIMEM>; + label = "slv-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>; + }; + + slv_snoc_pcnoc:slv-snoc-pcnoc { + cell-id = <MSM_BUS_SNOC_PNOC_SLV>; + label = "slv-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_PCNOC>; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = <MSM_BUS_SLAVE_QDSS_STM>; + label = "slv-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>; + }; + + slv_cats_0:slv-cats-0 { + cell-id = <MSM_BUS_SLAVE_CATS_128>; + label = "slv-cats-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>; + }; + + slv_cats_1:slv-cats-1 { + cell-id = <MSM_BUS_SLAVE_OCMEM_64>; + label = "slv-cats-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CATS_1>; + }; + + slv_lpass:slv-lpass { + cell-id = <MSM_BUS_SLAVE_LPASS>; + label = "slv-lpass"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>; + }; + }; + +}; diff --git a/qcom/msm8917-camera-pinctrl.dtsi b/qcom/msm8917-camera-pinctrl.dtsi new file mode 100644 index 00000000..3f7bc45c --- /dev/null +++ b/qcom/msm8917-camera-pinctrl.dtsi @@ -0,0 +1,292 @@ +cci { + cci0_active: cci0_active { + /* cci0 active state */ + mux { + /* CLK, DATA */ + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + }; + + config { + pins = "gpio29", "gpio30"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci0_suspend: cci0_suspend { + /* cci0 suspended state */ + mux { + /* CLK, DATA */ + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + }; + + config { + pins = "gpio29", "gpio30"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci1_active: cci1_active { + /* cci1 active state */ + mux { + /* CLK, DATA */ + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31", "gpio32"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci1_suspend: cci1_suspend { + /* cci1 suspended state */ + mux { + /* CLK, DATA */ + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31", "gpio32"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; +}; + +/*sensors */ +cam_sensor_mclk0_default: cam_sensor_mclk0_default { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio26"; + function = "cam_mclk"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_mclk0_sleep: cam_sensor_mclk0_sleep { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio26"; + function = "cam_mclk"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_default: cam_sensor_rear_default { + /* RESET, STANDBY */ + mux { + pins = "gpio36", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio36","gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_sleep: cam_sensor_rear_sleep { + /* RESET, STANDBY */ + mux { + pins = "gpio36","gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio36","gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_vdig: cam_sensor_rear_vdig { + /* VDIG */ + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_vdig_sleep: cam_sensor_rear_vdig_sleep { + /* VDIG */ + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_vdig_qm215: cam_sensor_rear_vdig_qm215 { + /* VDIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + output-high; + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_rear_vdig_sleep_qm215: cam_sensor_rear_vdig_sleep_qm215 { + /* VDIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + output-low; + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_mclk1_default: cam_sensor_mclk1_default { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_mclk1_sleep: cam_sensor_mclk1_sleep { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_front_default: cam_sensor_front_default { + /* RESET, STANDBY */ + mux { + pins = "gpio38","gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio38","gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_front_sleep: cam_sensor_front_sleep { + /* RESET, STANDBY */ + mux { + pins = "gpio38","gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio38","gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_mclk2_default: cam_sensor_mclk2_default { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_mclk2_sleep: cam_sensor_mclk2_sleep { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_front1_default: cam_sensor_front1_default { + /* RESET, STANDBY */ + mux { + pins = "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +cam_sensor_front1_sleep: cam_sensor_front1_sleep { + /* RESET, STANDBY */ + mux { + pins = "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; diff --git a/qcom/msm8917-camera.dtsi b/qcom/msm8917-camera.dtsi new file mode 100644 index 00000000..b72cd436 --- /dev/null +++ b/qcom/msm8917-camera.dtsi @@ -0,0 +1,514 @@ +&soc { + qcom,msm-cam@1b00000 { + compatible = "qcom,msm-cam"; + reg = <0x1b00000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 160000000 320000000 320000000>; + }; + + qcom,csiphy@1b34000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b34000 0x1000>, + <0x1b00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "csi_phy_clk", + "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0 0>; + }; + + qcom,csiphy@1b35000 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b35000 0x1000>, + <0x1b00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "csi_phy_clk", + "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0 0>; + }; + + qcom,csid@1b30000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30000 0x400>; + reg-names = "csid"; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,csid@1b30400 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30400 0x400>; + reg-names = "csid"; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,csid@1b30800 { + status = "ok"; + cell-index = <2>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30800 0x400>; + reg-names = "csid"; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,ispif@1b31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0x1b31000 0x500>, + <0x1b00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + vfe0-vdd-supply = <&gdsc_vfe>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "vfe0-vdd", "vfe1-vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "ispif_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_ahb_src", + "csi0_src_clk", "csi0_clk", + "csi0_rdi_clk", "csi0_pix_clk", + "csi1_src_clk", "csi1_clk", + "csi1_rdi_clk", "csi1_pix_clk", + "csi2_src_clk", "csi2_clk", + "csi2_rdi_clk", "csi2_pix_clk", + "vfe0_clk_src", "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", "vfe1_clk_src", + "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; + qcom,clock-rates = <61540000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-cntl-support; + qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE"; + }; + + vfe0: qcom,vfe0@1b10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0x1b10000 0x1000>, + <0x1b40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + vfe1: qcom,vfe1@1b14000 { + cell-index = <1>; + compatible = "qcom,vfe40"; + reg = <0x1b14000 0x1000>, + <0x1ba0000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk" , "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + qcom,cam_smmu { + status = "ok"; + compatible = "qcom,msm-cam-smmu"; + msm_cam_smmu_cb1: msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x400 0x00>, + <&apps_iommu 0x2400 0x00>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2: msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + label = "vfe_secure"; + qcom,secure-context; + }; + + msm_cam_smmu_cb3: msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1c00 0x00>; + label = "cpp"; + }; + + msm_cam_smmu_cb4: msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1800 0x00>; + label = "jpeg_enc0"; + }; + }; + + qcom,jpeg@1b1c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0x1b1c000 0x400>, + <0x1b60000 0xc30>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + qcom,vdd-names = "vdd"; + clock-names = "core_clk", "iface_clk", "bus_clk0", + "camss_top_ahb_clk", "camss_ahb_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + qcom,clock-rates = <266670000 0 0 0 0>; + qcom,qos-reg-settings = <0x28 0x0000555e>, + <0xc8 0x00005555>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 800000 800000>; + qcom,vbif-reg-settings = <0xc0 0x10101000>, + <0xb0 0x10100010>; + }; + + qcom,cpp@1b04000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0x1b04000 0x100>, + <0x1b80000 0x200>, + <0x1b18000 0x018>, + <0x1858078 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CPP_CLK_SRC>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>, + <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cpp_core_clk", + "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk", + "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk", + "micro_iface_clk", "camss_ahb_clk"; + qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>; + qcom,min-clock-rate = <133000000>; + resets = <&gcc GCC_CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,bus-master = <1>; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <156>; + qcom,plane-base = <141>; + qcom,stripe-size = <27>; + qcom,plane-size = <5>; + qcom,fe-ptr-off = <5>; + qcom,we-ptr-off = <11>; + }; + }; + + cci: qcom,cci@1b0c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0x1b0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cci"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CCI_CLK_SRC>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cci_src_clk", + "cci_ahb_clk", "camss_cci_clk", + "camss_ahb_clk", "camss_top_ahb_clk"; + qcom,clock-rates = <61540000 19200000 0 0 0 0>, + <61540000 37500000 0 0 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 30 0>, + <&tlmm 31 0>, + <&tlmm 32 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <20>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <32>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <15>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <25>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <19>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/qcom/msm8917-coresight.dtsi b/qcom/msm8917-coresight.dtsi new file mode 100644 index 00000000..d40e3b54 --- /dev/null +++ b/qcom/msm8917-coresight.dtsi @@ -0,0 +1,31 @@ +#include "msm8937-coresight.dtsi" + +&funnel_apss { + ports { + /delete-node/ port@1; + /delete-node/ port@2; + /delete-node/ port@3; + /delete-node/ port@4; + }; +}; + +&funnel_mm { + ports { + /delete-node/ port@4; + }; +}; + +&soc { + /delete-node/ etm@619c000; + /delete-node/ etm@619d000; + /delete-node/ etm@619e000; + /delete-node/ etm@619f000; + /delete-node/ cti@6198000; + /delete-node/ cti@6199000; + /delete-node/ cti@619a000; + /delete-node/ cti@619b000; +}; + +&dbgui { + qcom,dbgui-size = <32>; +}; diff --git a/qcom/msm8917-cpu.dtsi b/qcom/msm8917-cpu.dtsi new file mode 100644 index 00000000..71cb09d9 --- /dev/null +++ b/qcom/msm8917-cpu.dtsi @@ -0,0 +1,132 @@ +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + + cluster0 { + }; + + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + }; + + energy_costs: energy-costs { + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 656 159 + 682 172 + 748 207 + 827 244 + 853 256 + 893 283 + 958 327 + 1024 343 + >; + }; + }; +}; diff --git a/qcom/msm8917-gpu.dtsi b/qcom/msm8917-gpu.dtsi new file mode 100644 index 00000000..26d3c8b2 --- /dev/null +++ b/qcom/msm8917-gpu.dtsi @@ -0,0 +1,175 @@ +&soc { + msm_bus: qcom,kgsl-busmon { + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + /* Bus governor */ + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + /* + * Need to configure 2x Clock as BIMC + * Internally Divides by 2 for Gen1 DDR PHY. + */ + qcom,active-only; + qcom,bw-tbl = + < 0 >, /* Off */ + < 769 >, /* 1. DDR:100.80 MHz BIMC: 201.60 MHz */ + < 1611 >, /* 2. DDR:211.20 MHz BIMC: 422.40 MHz */ + < 2270 >, /* 3. DDR:297.60 MHz BIMC: 595.20 MHz */ + < 2929 >, /* 4. DDR:384.00 MHz BIMC: 768.00 MHz */ + < 4248 >, /* 5. DDR:556.80 MHz BIMC: 1113.60 MHz */ + < 4541 >, /* 6. DDR:595.20 MHz BIMC: 1190.40 MHz */ + < 5126 >, /* 7. DDR:672.00 MHz BIMC: 1344.00 MHz */ + < 5639 >; /* 8. DDR:739.20 MHz BIMC: 1478.40 MHz */ + }; + + msm_gpu: qcom,kgsl-3d0@1c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0x1c00000 0x10000 + 0x1c10000 0x10000 + 0x00a0000 0x06fff>; + reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory", + "qfprom_memory"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000620>; + + qcom,initial-pwrlevel = <3>; + + qcom,idle-timeout = <80>; //msecs + qcom,strtstp-sleepwake; + qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz + + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GCC_GTCU_AHB_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GFX_TBU_CLK>, + <&rpmcc RPM_SMD_BIMC_GPU_CLK>; + + clock-names = "core_clk", "iface_clk", "mem_iface_clk", + "alt_mem_iface_clk", "gtcu_iface_clk", + "gtcu_clk", "gtbu_clk", "bimc_gpu_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,bus-width = <16>; + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, /* off */ + <26 512 0 806400>, /* 1. 100.80 MHz */ + <26 512 0 1689600>, /* 2. 211.20 MHz */ + <26 512 0 2380800>, /* 3. 297.60 MHz */ + <26 512 0 3072000>, /* 4. 384.00 MHz */ + <26 512 0 4454400>, /* 5. 556.80 MHz */ + <26 512 0 4761600>, /* 6. 595.20 MHz */ + <26 512 0 5376000>, /* 7. 672.00 MHz */ + <26 512 0 5913600>; /* 8. 739.20 MHz */ + + /* GDSC regulator names */ + regulator-names = "vdd"; + /* GDSC oxili regulators */ + vdd-supply = <&gdsc_oxili_gx>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <651>; + + /* Enable gpu cooling device */ + #cooling-cells = <2>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <598000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <7>; + qcom,bus-max = <7>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <523200000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <484800000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <6>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + + kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x1f00000 0x10000>; + /* + * The gpu can only program a single context bank + * at this fixed offset. + */ + qcom,protect = <0xa000 0x1000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GTCU_AHB_CLK>, + <&gcc GCC_GFX_TBU_CLK>; + clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk", + "gtbu_clk"; + qcom,retention; + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&gfx_iommu 0>; + qcom,gpu-offset = <0xa000>; + }; + }; +}; diff --git a/qcom/msm8917-ion.dtsi b/qcom/msm8917-ion.dtsi new file mode 100644 index 00000000..5ad5c152 --- /dev/null +++ b/qcom/msm8917-ion.dtsi @@ -0,0 +1,24 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/msm8917-mdss-pll.dtsi b/qcom/msm8917-mdss-pll.dtsi new file mode 100644 index 00000000..15190242 --- /dev/null +++ b/qcom/msm8917-mdss-pll.dtsi @@ -0,0 +1,7 @@ +#include "msm8937-mdss-pll.dtsi" + +&mdss_dsi0_pll { + vddio-supply = <&pm8937_l6>; +}; + +/delete-node/ &mdss_dsi1_pll; diff --git a/qcom/msm8917-mdss.dtsi b/qcom/msm8917-mdss.dtsi new file mode 100644 index 00000000..235c6534 --- /dev/null +++ b/qcom/msm8917-mdss.dtsi @@ -0,0 +1,84 @@ +#include "msm8937-mdss.dtsi" +#include <dt-bindings/clock/mdss-28nm-pll-clk.h> +&mdss_dsi { + vdda-supply = <&pm8937_l2>; + vddio-supply = <&pm8937_l6>; + + ranges = <0x1a94000 0x1a94000 0x300 + 0x1a94400 0x1a94400 0x280 + 0x1a94b80 0x1a94b80 0x30 + 0x193e000 0x193e000 0x30>; + + clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_pixel0_clk"; + + /delete-property/ qcom,mdss-fb-map-sec; + +}; + +&mdss_dsi0 { + vdd-supply = <&pm8937_l17>; + vddio-supply = <&pm8937_l6>; +}; + +/delete-node/ &mdss_dsi1; + +&mdss_mdp { + qcom,max-bandwidth-low-kbps = <1800000>; + qcom,max-bandwidth-high-kbps = <1800000>; + qcom,max-bandwidth-per-pipe-kbps = <1000000>; + + qcom,mdss-intf-off = <0x00000000 0x0006B800>; + qcom,mdss-pingpong-off = <0x00071000>; + qcom,mdss-mixer-intf-off = <0x00045000>; + qcom,mdss-mixer-wb-off = <0x00046000>; + qcom,mdss-wfd-mode = "dedicated"; + qcom,mdss-per-pipe-panic-luts = <0x000f>, + <0x0>, + <0xfffc>, + <0x0>; + + /delete-property/ qcom,mdss-highest-bank-bit; + /delete-property/ qcom,vbif-settings; + + qcom,regs-dump-mdp = <0x01000 0x01454>, + <0x02000 0x02064>, + <0x02200 0x02264>, + <0x02400 0x02464>, + <0x05000 0x05150>, + <0x05200 0x05230>, + <0x15000 0x15150>, + <0x17000 0x17150>, + <0x25000 0x25150>, + <0x35000 0x35150>, + <0x45000 0x452bc>, + <0x46000 0x462bc>, + <0x55000 0x5522c>, + <0x65000 0x652c0>, + <0x66000 0x662c0>, + <0x6b800 0x6ba68>, + <0x71000 0x710d4>; + + qcom,regs-dump-names-mdp = "MDP", + "CTL_0", "CTL_1", "CTL_2", + "VIG0_SSPP", "VIG0", + "RGB0_SSPP", "RGB1_SSPP", + "DMA0_SSPP", + "CURSOR0_SSPP", + "LAYER_0", "LAYER_1", + "DSPP_0", + "WB_0", "WB_2", + "INTF_1", + "PP_0"; +}; + +&mdss_rotator { + /delete-property/ qcom,mdss-has-ubwc; +}; + +/delete-node/ &mdss_fb2; diff --git a/qcom/msm8917-pinctrl.dtsi b/qcom/msm8917-pinctrl.dtsi new file mode 100644 index 00000000..0a590db4 --- /dev/null +++ b/qcom/msm8917-pinctrl.dtsi @@ -0,0 +1,1852 @@ +&soc { + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8917-pinctrl"; + reg = <0x1000000 0x300000>; + reg-names = "pinctrl_regs"; + interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + wakeup-parent = <&wakegpio>; + #interrupt-cells = <2>; + irqdomain-map = <38 0 &wakegpio 3 0>, + <1 0 &wakegpio 4 0>, + <5 0 &wakegpio 5 0>, + <9 0 &wakegpio 6 0>, + <37 0 &wakegpio 8 0>, + <36 0 &wakegpio 9 0>, + <13 0 &wakegpio 10 0>, + <35 0 &wakegpio 11 0>, + <17 0 &wakegpio 12 0>, + <21 0 &wakegpio 13 0>, + <54 0 &wakegpio 14 0>, + <34 0 &wakegpio 15 0>, + <31 0 &wakegpio 16 0>, + <58 0 &wakegpio 17 0>, + <28 0 &wakegpio 18 0>, + <42 0 &wakegpio 19 0>, + <25 0 &wakegpio 20 0>, + <12 0 &wakegpio 21 0>, + <43 0 &wakegpio 22 0>, + <44 0 &wakegpio 23 0>, + <45 0 &wakegpio 24 0>, + <46 0 &wakegpio 25 0>, + <48 0 &wakegpio 26 0>, + <65 0 &wakegpio 27 0>, + <93 0 &wakegpio 28 0>, + <97 0 &wakegpio 29 0>, + <63 0 &wakegpio 30 0>, + <70 0 &wakegpio 31 0>, + <71 0 &wakegpio 32 0>, + <72 0 &wakegpio 33 0>, + <81 0 &wakegpio 34 0>, + <126 0 &wakegpio 35 0>, + <90 0 &wakegpio 36 0>, + <128 0 &wakegpio 37 0>, + <91 0 &wakegpio 38 0>, + <41 0 &wakegpio 39 0>, + <127 0 &wakegpio 40 0>, + <86 0 &wakegpio 41 0>, + <67 0 &wakegpio 50 0>, + <73 0 &wakegpio 51 0>, + <74 0 &wakegpio 52 0>, + <62 0 &wakegpio 53 0>, + <124 0 &wakegpio 54 0>, + <61 0 &wakegpio 55 0>, + <130 0 &wakegpio 56 0>, + <59 0 &wakegpio 57 0>, + <50 0 &wakegpio 59 0>; + irqdomain-map-pass-thru = <0 0xff>; + irqdomain-map-mask = <0xff 0>; + +#include "msm8917-camera-pinctrl.dtsi" + /* add pingrp for touchscreen */ + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio65", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio65", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx-uartconsole { + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart_console_sleep: uart_console_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + }; + + blsp1_uart1 { + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + wcnss_pmux_5wire { + /* Active configuration of bus pins */ + wcnss_default: wcnss_default { + wcss_wlan2 { + pins = "gpio76"; + function = "wcss_wlan2"; + }; + + wcss_wlan1 { + pins = "gpio77"; + function = "wcss_wlan1"; + }; + + wcss_wlan0 { + pins = "gpio78"; + function = "wcss_wlan0"; + }; + + wcss_wlan { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <6>; /* 6 MA */ + bias-pull-up; /* PULL UP */ + }; + }; + + wcnss_sleep: wcnss_sleep { + wcss_wlan2 { + pins = "gpio76"; + function = "wcss_wlan2"; + }; + + wcss_wlan1 { + pins = "gpio77"; + function = "wcss_wlan1"; + }; + + wcss_wlan0 { + pins = "gpio78"; + function = "wcss_wlan0"; + }; + + wcss_wlan { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + }; + + wcnss_pmux_gpio: wcnss_pmux_gpio { + wcnss_gpio_default: wcnss_gpio_default { + /* Active configuration of bus pins */ + mux { + /* Uses general purpose pins */ + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <6>; /* 6 MA */ + bias-pull-up; /* PULL UP */ + }; + }; + }; + + cdc_mclk2_pin { + cdc_mclk2_sleep: cdc_mclk2_sleep { + mux { + pins = "gpio66"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + cdc_mclk2_active: cdc_mclk2_active { + mux { + pins = "gpio66"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_mdss: pmx_mdss { + mdss_dsi_active: mdss_dsi_active { + mux { + pins = "gpio60", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + + mdss_dsi_suspend: mdss_dsi_suspend { + mux { + pins = "gpio60", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + pmx_mdss_te { + mdss_te_active: mdss_te_active { + mux { + pins = "gpio24"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* pull down*/ + }; + }; + + mdss_te_suspend: mdss_te_suspend { + mux { + pins = "gpio24"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + pmx_qdsd_clk { + qdsd_clk_sdcard: clk_sdcard { + config { + pins = "qdsd_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + qdsd_clk_trace: clk_trace { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_clk_swdtrc: clk_swdtrc { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_clk_spmi: clk_spmi { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_cmd { + qdsd_cmd_sdcard: cmd_sdcard { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_cmd_trace: cmd_trace { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_swduart: cmd_uart { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_swdtrc: cmd_swdtrc { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_jtag: cmd_jtag { + config { + pins = "qdsd_cmd"; + bias-disable; /* NO pull */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_cmd_spmi: cmd_spmi { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <10>; /* 10 MA */ + }; + }; + }; + + pmx_qdsd_data0 { + qdsd_data0_sdcard: data0_sdcard { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data0_trace: data0_trace { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data0_swduart: data0_uart { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_swdtrc: data0_swdtrc { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_jtag: data0_jtag { + config { + pins = "qdsd_data0"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_spmi: data0_spmi { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data1 { + qdsd_data1_sdcard: data1_sdcard { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data1_trace: data1_trace { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data1_swduart: data1_uart { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data1_swdtrc: data1_swdtrc { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data1_jtag: data1_jtag { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data2 { + qdsd_data2_sdcard: data2_sdcard { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data2_trace: data2_trace { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data2_swduart: data2_uart { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data2_swdtrc: data2_swdtrc { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data2_jtag: data2_jtag { + config { + pins = "qdsd_data2"; + bias-pull-up; /* pull up */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_qdsd_data3 { + qdsd_data3_sdcard: data3_sdcard { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data3_trace: data3_trace { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data3_swduart: data3_uart { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_swdtrc: data3_swdtrc { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_jtag: data3_jtag { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_spmi: data3_spmi { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_sdc1_rclk { + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + }; + + pmx_sdc1_clk { + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc1_cmd { + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc1_data { + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + sdhc2_cd_pin { + sdc2_cd_on: cd_on { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_sdc2_clk { + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + drive-strength = <16>; /* 16 MA */ + bias-disable; /* NO pull */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_cmd { + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_data { + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + sdc2_wlan_gpio { + sdc2_wlan_gpio_active: sdc2_wlan_gpio_active { + config { + pins = "gpio99"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc2_wlan_gpio_sleep: sdc2_wlan_gpio_sleep { + config { + pins = "gpio99"; + output-low; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + pri_mi2s_mclk_b_lines { + pri_mi2s_mclk_b_default: pri_mi2s_mclk_default { + mux { + pins = "gpio69"; + function = "pri_mi2s_mclk_b"; + }; + + config { + pins = "gpio69"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + }; + + sec_mi2s_mclk_a_lines { + sec_mi2s_mclk_a_active: sec_mi2s_mclk_a_active { + mux { + pins = "gpio25"; + function = "sec_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <8>; /* 8 MA */ + output-high; + bias-disable; + }; + }; + + sec_mi2s_mclk_a_sleep: sec_mi2s_mclk_a_sleep { + mux { + pins = "gpio25"; + function = "sec_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; /* 2 MA */ + output-low; + bias-pull-down; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + + cdc-pdm-2-lines { + cdc_pdm_lines_2_act: pdm_lines_2_on { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio70", "gpio71", "gpio72"; + drive-strength = <8>; + }; + }; + + cdc_pdm_lines_2_sus: pdm_lines_2_off { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio70", "gpio71", "gpio72"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cdc-pdm-lines { + cdc_pdm_lines_act: pdm_lines_on { + mux { + pins = "gpio69", "gpio73", "gpio74"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio69", "gpio73", "gpio74"; + drive-strength = <8>; + }; + }; + + cdc_pdm_lines_sus: pdm_lines_off { + mux { + pins = "gpio69", "gpio73", "gpio74"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio69", "gpio73", "gpio74"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cross-conn-det { + cross_conn_det_act: lines_on { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <8>; + output-low; + bias-pull-down; + }; + }; + + cross_conn_det_sus: lines_off { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* WSA VI sense */ + wsa-vi { + wsa_vi_on: wsa_vi_on { + mux { + pins = "gpio94", "gpio95"; + function = "wsa_io"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* NO pull */ + }; + }; + + wsa_vi_off: wsa_vi_off { + mux { + pins = "gpio94", "gpio95"; + function = "wsa_io"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + }; + + /* WSA Reset */ + wsa_reset { + wsa_reset_on: wsa_reset_on { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + wsa_reset_off: wsa_reset_off { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + }; + + /* WSA CLK */ + wsa_clk { + wsa_clk_on: wsa_clk_on { + mux { + pins = "gpio25"; + function = "pri_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <8>; /* 8 MA */ + output-high; + }; + }; + + wsa_clk_off: wsa_clk_off { + mux { + pins = "gpio25"; + function = "pri_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; /* 2 MA */ + output-low; + bias-pull-down; + }; + }; + }; + + pri-tlmm-lines { + pri_tlmm_lines_act: pri_tlmm_lines_act { + mux { + pins = "gpio85", "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85", "gpio88"; + drive-strength = <8>; + }; + }; + + pri_tlmm_lines_sus: pri_tlmm_lines_sus { + mux { + pins = "gpio85", "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pri-tlmm-ws-lines { + pri_tlmm_ws_act: pri_tlmm_ws_act { + mux { + pins = "gpio87"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio87"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + pri_tlmm_ws_sus: pri_tlmm_ws_sus { + mux { + pins = "gpio87"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + spi3 { + spi3_default: spi3_default { + /* active state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <12>; /* 12 MA */ + bias-disable = <0>; /* No PULL */ + }; + }; + + spi3_sleep: spi3_sleep { + /* suspended state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + + spi3_cs0_active: cs0_active { + /* CS */ + mux { + pins = "gpio10"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + spi3_cs0_sleep: cs0_sleep { + /* CS */ + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + spi6 { + spi6_default: spi6_default { + /* active state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio20", "gpio21", "gpio23"; + drive-strength = <16>; /* 16 MA */ + bias-disable = <0>; /* No PULL */ + }; + }; + + spi6_sleep: spi6_sleep { + /* suspended state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio23"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + + spi6_cs0_active: cs0_active { + /* CS */ + mux { + pins = "gpio47"; + function = "blsp6_spi"; + }; + + config { + pins = "gpio47"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + spi6_cs0_sleep: cs0_sleep { + /* CS */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + spi6_cs1_active: cs1_active { + /* CS */ + mux { + pins = "gpio22"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio22"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + spi6_cs1_sleep: cs1_sleep { + /* CS */ + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio124"; + function = "fpc_reset_gpio_low"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio124"; + function = "fpc_reset_gpio_high"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio48"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + + i2c_2 { + i2c_2_active: i2c_2_active { + /* active state */ + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + /* suspended state */ + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + /* active state */ + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + /* suspended state */ + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* IO Expander SX150xq */ + i2c_4 { + i2c_4_active: i2c_4_active { + /* active state */ + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + /* suspended state */ + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + /* active state */ + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + /* suspended state */ + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + /* active state */ + mux { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + /* suspended state */ + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 17 NFC Read Interrupt */ + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 17 NFC Read Interrupt */ + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_disable_active: nfc_disable_active { + /* active state */ + mux { + /* 16: NFC ENABLE 130: FW DNLD */ + pins = "gpio16", "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio130"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_disable_suspend: nfc_disable_suspend { + /* sleep state */ + mux { + /* 16: NFC ENABLE 130: FW DNLD */ + pins = "gpio16", "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio130"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + tlmm_gpio_key { + gpio_key_active: gpio_key_active { + mux { + pins = "gpio91", "gpio127", "gpio128"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_key_suspend: gpio_key_suspend { + mux { + pins = "gpio91", "gpio127", "gpio128"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + tlmm_pmi_flash_led { + rear_flash_led_enable: rear_flash_led_enable { + mux { + pins = "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + output-high; + }; + }; + + rear_flash_led_disable: rear_flash_led_disable { + mux { + pins = "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + output-low; + }; + }; + + front_flash_led_enable: front_flash_led_enable { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <16>; + output-high; + }; + }; + + front_flash_led_disable: front_flash_led_disable { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; + output-low; + }; + }; + }; + + usbc_int_default: usbc_int_default { + mux { + pins = "gpio97", "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio131"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio85"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio85"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio88"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio86"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio86"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio86"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_ws { + sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { + mux { + pins = "gpio95"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sec_mi2s_ws_active: sec_mi2s_ws_active { + mux { + pins = "gpio95"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio95"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + }; + + sec_mi2s_sck { + sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { + mux { + pins = "gpio94"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sec_mi2s_sck_active: sec_mi2s_sck_active { + mux { + pins = "gpio94"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio94"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio12"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio12"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio13"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio13"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <16>; /* 16 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + usb_mode_select: usb_mode_select { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + usb2533_hub_reset: usb2533_hub_reset { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + output-low; + }; + }; + }; +}; diff --git a/qcom/msm8917-pm.dtsi b/qcom/msm8917-pm.dtsi new file mode 100644 index 00000000..b9288ff7 --- /dev/null +++ b/qcom/msm8917-pm.dtsi @@ -0,0 +1,120 @@ +#include <dt-bindings/msm/pm.h> + +&soc { + qcom,spm@b012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb012000 0x1000>; + qcom,name = "perf-l2"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C11840A>; + qcom,saw2-spm-ctl = <0xe>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <1>; + qcom,entry-latency-us = <38>; /* TBD */ + qcom,exit-latency-us = <180>; + qcom,min-residency-us = <305>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "perf-l2-gdhs"; + qcom,psci-mode = <4>; + qcom,entry-latency-us = <800>; /* TBD */ + qcom,exit-latency-us = <280>; + qcom,min-residency-us = <520>; + qcom,min-child-idx = <1>; + qcom,reset-level = <LPM_RESET_LVL_GDHS>; + }; + + qcom,pm-cluster-level@2 { + reg = <2>; + label = "perf-l2-retention"; + qcom,psci-mode = <2>; + qcom,entry-latency-us = <640>; /* TBD */ + qcom,exit-latency-us = <650>; + qcom,min-residency-us = <1350>; + qcom,min-child-idx = <1>; + qcom,reset-level = <LPM_RESET_LVL_RET>; + }; + + qcom,pm-cluster-level@3 { + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <5>; + qcom,entry-latency-us = <800>; /* TBD */ + qcom,exit-latency-us = <11200>; + qcom,min-residency-us = <1700>; + qcom,min-child-idx = <1>; + qcom,is-reset; + qcom,notify-rpm; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <1>; + qcom,entry-latency-us = <49>; /* TBD */ + qcom,exit-latency-us = <12>; + qcom,min-residency-us = <25>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <3>; + qcom,entry-latency-us = <290>; /* TBD */ + qcom,exit-latency-us = <180>; + qcom,min-residency-us = <305>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + }; + }; + }; + + qcom,rpm-stats@29dba0 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, <0x290014 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + }; + + qcom,rpm-master-stats@60150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x60150 0x5000>; + qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/qcom/msm8917-regulator.dtsi b/qcom/msm8917-regulator.dtsi new file mode 100644 index 00000000..c125a621 --- /dev/null +++ b/qcom/msm8917-regulator.dtsi @@ -0,0 +1,277 @@ +#include "msm8937-regulator.dtsi" + +&soc { + /* delete the CPR and MEM ACC nodes of msm8937 */ + /delete-node/ regulator@b018000; + /delete-node/ regulator@01946004; + + mem_acc_vreg_corner: regulator@01946004 { + compatible = "qcom,mem-acc-regulator"; + reg = <0xa4000 0x1000>; + reg-names = "efuse_addr"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-reg-addr-list = + <0x01942138 0x01942130 0x01942120 0x01942124>; + + qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x0>, + < 4 0x0>; + + qcom,corner2-reg-config = + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>; + + qcom,corner3-reg-config = + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>; + + qcom,override-acc-fuse-sel = <71 17 3 0>; + qcom,override-fuse-version-map = <1>, + <2>, + <3>, + <4>; + qcom,override-corner1-addr-val-map = + /* 1st fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x1>, + < 4 0x0>, + + /* 2nd fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x3>, + < 4 0x0>, + + /* 3rd fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x0>, + < 4 0x0>, + + /* 4th fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x1>, + < 4 0x0>; + + qcom,override-corner2-addr-val-map = + /* 1st fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x1>, < 4 0x0>, + + /* 2nd fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x3>, < 4 0x0>, + + /* 3rd fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>, + + /* 4th fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x1>, < 4 0x0>; + + qcom,override-corner3-addr-val-map = + /* 1st fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 2nd fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 3rd fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 4th fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <5>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; + qcom,cpr-voltage-floor = <1050000 1050000 1090000>; + vdd-apc-supply = <&pm8937_s5>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <16>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <4>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,cpr-fuse-row = <67 0>; + qcom,cpr-fuse-target-quot = <42 24 6>; + qcom,cpr-fuse-ro-sel = <60 57 54>; + qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>; + qcom,cpr-fuse-init-voltage = + <67 36 6 0>, + <67 18 6 0>, + <67 0 6 0>; + qcom,cpr-fuse-quot-offset = + <71 26 6 0>, + <71 20 6 0>, + <70 54 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 960000000>, + <2 1094400000>, + <3 1248000000>, + <4 1401000000>, + <5 1497600000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 (-1) 1 2 4>, + <1 (-1) 1 2 5>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-fuse-revision = <69 39 3 0>; + qcom,pvs-version-fuse-sel = <37 40 3 0>; /* foundry */ + qcom,cpr-fuse-version-map = + < 1 0 3 (-1) (-1) (-1)>, + < 1 5 3 (-1) (-1) (-1)>, + <(-1) 0 1 (-1) (-1) (-1)>, + <(-1) 0 2 (-1) (-1) (-1)>, + <(-1) 5 1 (-1) (-1) (-1)>, + <(-1) 5 2 (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1)>; + qcom,cpr-quotient-adjustment = + <50 40 50>, + <0 0 40>, + <50 40 100>, + <50 40 50>, + <0 0 100>, + <0 0 50>, + <0 0 0>; + qcom,cpr-init-voltage-adjustment = + <30000 5000 10000>, + <0 0 0>, + <30000 5000 35000>, + <30000 5000 10000>, + <0 0 20000>, + <0 0 0>, + <0 0 0>; + qcom,cpr-enable; + }; + + eldo2_pm8937: eldo2 { + compatible = "regulator-fixed"; + regulator-name = "eldo2_pm8937"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pm8937_gpios 7 0>; + regulator-always-on; + }; +}; diff --git a/qcom/msm8917-thermal.dtsi b/qcom/msm8917-thermal.dtsi new file mode 100644 index 00000000..6fe1977f --- /dev/null +++ b/qcom/msm8917-thermal.dtsi @@ -0,0 +1,364 @@ +#include <dt-bindings/thermal/thermal.h> + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + q6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + penta-cpu-max-step { + polling-delay-passive = <50>; + polling-delay = <100>; + thermal-governor = "step_wise"; + trips { + cpu_trip:cpu-trip { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu1_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu2_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu3_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + }; + }; + + gpu0-step { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + gpu_step_trip: gpu-step-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev0 { + trip = <&gpu_step_trip>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + apc1-cpu0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "step_wise"; + trips { + apc1_cpu0_trip: apc1-cpu0-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&apc1_cpu0_trip>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + trips { + apc1_cpu1_trip: apc1-cpu1--trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&apc1_cpu1_trip>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + apc1_cpu2_trip: apc1-cpu2-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu2_cdev { + trip = <&apc1_cpu2_trip>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + apc1_cpu3_trip: apc1-cpu3-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu3_cdev { + trip = <&apc1_cpu3_trip>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + tracks-low; + trips { + aoss_lowf: aoss-lowf { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&aoss_lowf>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&aoss_lowf>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&aoss_lowf>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; +}; diff --git a/qcom/msm8917-vidc.dtsi b/qcom/msm8917-vidc.dtsi new file mode 100644 index 00000000..362c1368 --- /dev/null +++ b/qcom/msm8917-vidc.dtsi @@ -0,0 +1,158 @@ +&soc { + qcom,vidc@1d00000 { + compatible = "qcom,msm-vidc"; + reg = <0x01d00000 0xff000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + qcom,hfi-version = "3xx"; + venus-supply = <&gdsc_venus>; + venus-core0-supply = <&gdsc_venus_core0>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core_clk", "core0_clk", "iface_clk", "bus_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x0>; + qcom,sw-power-collapse; + qcom,slave-side-cp; + qcom,dcvs-tbl = + <108000 108000 244800 0x00000004>, /* Encoder */ + <108000 108000 244800 0x0c000000>; /* Decoder */ + qcom,dcvs-limit = + <8160 30>, /* Encoder */ + <8160 30>; /* Decoder */ + qcom,hfi = "venus"; + qcom,reg-presets = <0xe0020 0x05555556>, + <0xe0024 0x05555556>, + <0x80124 0x00000003>; + qcom,qdss-presets = <0x826000 0x1000>, + <0x827000 0x1000>, + <0x822000 0x1000>, + <0x803000 0x1000>, + <0x9180000 0x1000>, + <0x9181000 0x1000>; + qcom,max-hw-load = <352800>; /* 1080p@30 + 720p@30 */ + qcom,pm-qos-latency-us = <651>; + qcom,firmware-name = "venus"; + qcom,allowed-clock-rates = <360000000 329140000 + 308570000 270000000 200000000>; + qcom,clock-freq-tbl { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,cycles-per-mb = <2470>; + qcom,low-power-mode-factor = <32768>; + }; + + qcom,profile-dec { + qcom,codec-mask = <0xf3ffffff>; + qcom,cycles-per-mb = <788>; + }; + + qcom,profile-hevcdec { + qcom,codec-mask = <0x0c000000>; + qcom,cycles-per-mb = <1015>; + }; + }; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_iommu 0x800 0x00>, + <&apps_iommu 0x807 0x00>, + <&apps_iommu 0x808 0x27>, + <&apps_iommu 0x811 0x20>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_iommu 0x900 0x00>, + <&apps_iommu 0x90a 0x04>, + <&apps_iommu 0x909 0x22>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x12c00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_iommu 0x90c 0x20>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_iommu 0x940 0x00>, + <&apps_iommu 0x907 0x08>, + <&apps_iommu 0x908 0x20>, + <&apps_iommu 0x90d 0x20>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>; + qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>; + qcom,bus-governor = "venus-ddr-gov"; + qcom,bus-range-kbps = <1000 917000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>; + qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + }; + + venus-ddr-gov { + compatible = "qcom,msm-vidc,governor,table"; + name = "venus-ddr-gov"; + status = "ok"; + qcom,bus-freq-table { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,load-busfreq-tbl = + <244800 841000>, /* 1080p30E */ + <216000 740000>, /* 720p60E */ + <194400 680000>, /* FWVGA120E */ + <144000 496000>, /* VGA120E */ + <108000 370000>, /* 720p30E */ + <97200 340000>, /* FWVGA60E */ + <48600 170000>, /* FWVGA30E */ + <72000 248000>, /* VGA60E */ + <36000 124000>, /* VGA30E */ + <18000 70000>, /* QVGA60E */ + <9000 35000>, /* QVGA30E */ + <0 0>; + }; + + qcom,profile-dec { + qcom,codec-mask = <0xffffffff>; + qcom,load-busfreq-tbl = + <244800 605000>, /* 1080p30D */ + <216000 540000>, /* 720p60D */ + <194400 484000>, /* FWVGA120D */ + <144000 360000>, /* VGA120D */ + <108000 270000>, /* 720p30D */ + <97200 242000>, /* FWVGA60D */ + <48600 121000>, /* FWVGA30D */ + <72000 180000>, /* VGA60D */ + <36000 90000>, /* VGA30D */ + <18000 45000>, /* HVGA30D */ + <0 0>; + }; + }; + }; +}; diff --git a/qcom/msm8917.dtsi b/qcom/msm8917.dtsi new file mode 100644 index 00000000..5b573ce9 --- /dev/null +++ b/qcom/msm8917.dtsi @@ -0,0 +1,2148 @@ +#include "skeleton64.dtsi" +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include <dt-bindings/clock/mdss-28nm-pll-clk.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} + +/ { + model = "Qualcomm Technologies, Inc. MSM8917"; + compatible = "qcom,msm8917"; + qcom,msm-id = <303 0x0>, <308 0x0>, <309 0x0>; + interrupt-parent = <&wakegic>; + + chosen { + bootargs = "sched_enable_hmp=1"; + }; + + aliases { + /* smdtty devices */ + smd1 = &smdtty_apps_fm; + smd2 = &smdtty_apps_riva_bt_acl; + smd3 = &smdtty_apps_riva_bt_cmd; + smd4 = &smdtty_mbalbridge; + smd5 = &smdtty_apps_riva_ant_cmd; + smd6 = &smdtty_apps_riva_ant_data; + smd7 = &smdtty_data1; + smd8 = &smdtty_data4; + smd11 = &smdtty_data11; + smd21 = &smdtty_data21; + smd36 = &smdtty_loopback; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 for SD card */ + spi3 = &spi_3; + spi6 = &spi_6; + i2c2 = &i2c_2; + i2c5 = &i2c_5; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + other_ext_mem: other_ext_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85b00000 0x0 0xd00000>; + }; + + modem_mem: modem_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86800000 0x0 0x5500000>; + }; + + adsp_fw_mem: adsp_fw_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8bd00000 0x0 0x1100000>; + }; + + wcnss_fw_mem: wcnss_fw_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8ce00000 0x0 0x700000>; + }; + + venus_mem: venus_region@0 { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; + alignment = <0 0x400000>; + size = <0 0x0800000>; + }; + + qseecom_mem: qseecom_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + adsp_mem: adsp_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + cont_splash_mem: splash_region@83000000 { + reg = <0x0 0x90000000 0x0 0x1400000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0 0xd5000>; + }; + }; + + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + soc: soc { }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; +}; + +#include "msm8917-pinctrl.dtsi" +#include "msm8917-camera.dtsi" +#include "msm8917-cpu.dtsi" +#include "msm8917-pm.dtsi" +#include "msm8917-ion.dtsi" +#include "msm8917-coresight.dtsi" +#include "msm8917-bus.dtsi" +#include "msm8917-mdss.dtsi" +#include "msm8917-mdss-pll.dtsi" +#include "msm-arm-smmu-8917.dtsi" +#include "msm8917-gpu.dtsi" +#include "msm8917-vidc.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + dcc: dcc@b3000 { + compatible = "qcom,dcc"; + reg = <0xb3000 0x1000>, + <0xb4000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&gcc GCC_DCC_CLK>; + clock-names = "apb_pclk"; + + qcom,save-reg; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; + reg = <0x601d0 0x1000>, + <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <64>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 2 0xff08>, + <1 3 0xff08>, + <1 4 0xff08>, + <1 1 0xff08>; + clock-frequency = <19200000>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + thermal_zones: thermal-zones {}; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpm_sw_dump { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + vsense_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe9>; + }; + + tmc_etf_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + tmc_etr_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + tmc_etf_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c200_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c300_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache100 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x60>; + }; + + l1_icache101 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x61>; + }; + + l1_icache102 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x62>; + }; + + l1_icache103 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x63>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache101 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache102 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache103 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + }; + + tsens0: tsens@4a8000 { + compatible = "qcom,msm8937-tsens"; + reg = <0x4a8000 0x1000>, + <0x4a9000 0x1000>, + <0xa4000 0x1000>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical", "tsens_eeprom_physical"; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tsens-upper-lower"; + #thermal-sensor-cells = <1>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,rmtfs_sharedmem@00000000 { + compatible = "qcom,sharedmem-uio"; + reg = <0x00000000 0x00180000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4a3000 0x1000>; + clock-frequency = <32768>; + }; + + cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0xff00>; + }; + + slim_msm: slim@c140000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xc140000 0x2c000>, + <0xc104000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x600000>; + qcom,ea-pc = <0x230>; + status = "disabled"; + }; + + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart1: uart@78af000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x78af000 0x200>, + <0x7884000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-parent = <&blsp1_uart1>; + interrupts = <0 1 2>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + interrupt-map = <0 &intc 0 107 0 + 1 &intc 0 238 0 + 2 &tlmm 1 0>; + interrupt-map-mask = <0xffffffff>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + qcom,msm-bus,name = "blsp1_uart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x1f000>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <10>; + }; + + dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7ac4000 0x1f000>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <10>; + }; + + + /* IO Expander SX150xq */ + /* BLSP1 QUP4 */ + i2c_4: i2c@78b8000 { + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-msm8917"; + #clock-cells = <1>; + }; + + gcc: qcom,gcc@1800000 { + compatible = "qcom,gcc-msm8917", "syscon"; + reg = <0x1800000 0x80000>, + <0x00a6018 0x00004>; + reg-names = "cc_base", "gpu-bin"; + qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>; + vdd_cx-supply = <&pm8937_s2_level>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,msm8917-debugcc"; + reg = <0x1874000 0x4>, + <0xb01101c 0x8>; + reg-names = "cc_base", "meas"; + qcom,gcc = <&gcc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + gcc_mdss: qcom,gcc-mdss@1800000 { + compatible = "qcom,gcc-mdss-8917"; + reg = <0x1800000 0x80000>; + clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>; + clock-names = "pclk0_src", "byte0_src"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,cpu-clock-8939@b111050 { + compatible = "qcom,cpu-clock-8917"; + reg = <0xb011050 0x8>, + <0x00a412c 0x8>; + reg-names = "apcs-c1-rcg-base", "efuse"; + qcom,num-cluster; + vdd-c1-supply = <&apc_vreg_corner>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0_AO_OUT_MAIN>; + clock-names = "xo_ao", "gpll0_ao" ; + qcom,speed0-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1248000000 3>, + < 1401000000 4>; + + qcom,speed1-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1248000000 3>, + < 1401000000 4>, + < 1497600000 5>; + + qcom,speed2-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1209600000 3>; + + qcom,speed3-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1248000000 3>, + < 1305600000 4>; + + #clock-cells = <1>; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + /* TODO + * clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", + * "cpu3_clk"; + * clocks = <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>; + */ + + qcom,cpufreq-table = + < 960000 >, + < 1094400 >, + < 1209600 >, + < 1248000 >, + < 1305600 >, + < 1401000 >, + < 1497600 >; + }; + + i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 6 64 0x20000020 0x20>, + <&dma_blsp1 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x7af5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <84>; + dmas = <&dma_blsp2 4 64 0x20000020 0x20>, + <&dma_blsp2 5 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi_3: spi@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b7000 0x600>, + <0x7884000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi3_default &spi3_cs0_active>; + pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + status = "disabled"; + }; + + usb_otg: usb@78db000 { + compatible = "qcom,hsusb-otg"; + reg = <0x78db000 0x400>, <0x6c000 0x200>; + reg-names = "core", "phy_csr"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 134 IRQ_TYPE_LEVEL_HIGH>, + <0 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core_irq", "async_irq"; + + hsusb_vdd_dig-supply = <&pm8937_l2>; + HSUSB_1p8-supply = <&pm8937_l7>; + HSUSB_3p3-supply = <&pm8937_l13>; + qcom,vdd-voltage-level = <0 1200000 1200000>; + vbus_otg-supply = <&smbcharger_charger_otg>; + + qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ + qcom,hsusb-otg-mode = <3>; /* OTG mode */ + qcom,hsusb-otg-otg-control = <2>; /* PMIC */ + qcom,dp-manual-pullup; + qcom,phy-dvdd-always-on; + qcom,boost-sysclk-with-streaming; + qcom,axi-prefetch-enable; + qcom,enable-sdp-typec-current-limit; + qcom,hsusb-otg-delay-lpm; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 80000 0>, + <87 512 6000 6000>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>, + <&rpmcc BIMC_USB_A_CLK>, + <&rpmcc SNOC_USB_A_CLK>, + <&rpmcc PNOC_USB_A_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&rpmcc CXO_SMD_OTG_CLK>; + clock-names = "iface_clk", "core_clk", "sleep_clk", + "bimc_clk", "snoc_clk", "pcnoc_clk", + "phy_csr_clk", "xo"; + qcom,bus-clk-rate = <595200000 200000000 100000000>; + qcom,max-nominal-sysclk-rate = <133330000>; + + resets = <&gcc GCC_USB_HS_BCR>, + <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "core_reset", "phy_reset", "phy_por_reset"; + + qcom,usbbam@78c4000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x78c4000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 135 IRQ_TYPE_LEVEL_HIGH>; + + qcom,bam-type = <1>; + qcom,usb-bam-num-pipes = <4>; + qcom,usb-bam-fifo-baseaddr = <0x08605000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,reset-bam-on-disconnect; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6044000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0xe00>; + qcom,descriptor-fifo-offset = <0xe00>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 100, 8); /* 769 MB/s */ + BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ + BW_OPP_ENTRY( 297, 8); /* 2270 MB/s */ + BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */ + BW_OPP_ENTRY( 556, 8); /* 4248 MB/s */ + BW_OPP_ENTRY( 595, 8); /* 4541 MB/s */ + BW_OPP_ENTRY( 672, 8); /* 5126 MB/s */ + BW_OPP_ENTRY( 740, 8); /* 5645 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@408000 { + compatible = "qcom,bimc-bwmon2"; + reg = <0x408000 0x300>, <0x401000 0x200>; + reg-names = "base", "global_base"; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + qcom,mport = <0>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 998400 MHZ_TO_MBPS(230, 8) >, + < 1094400 MHZ_TO_MBPS(557, 8) >, + < 1497600 MHZ_TO_MBPS(557, 8) >; + }; + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + label = "modem"; + }; + }; + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + jtag_mm0: jtagmm@61bc000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bc000 0x1000>, + <0x61b0000 0x1000>; + reg-names = "etm-base", "debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + jtag_mm1: jtagmm@61bd000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bd000 0x1000>, + <0x61b2000 0x1000>; + reg-names = "etm-base", "debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + jtag_mm2: jtagmm@61be000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61be000 0x1000>, + <0x61b4000 0x1000>; + reg-names = "etm-base", "debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + jtag_mm3: jtagmm@61bf000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bf000 0x1000>, + <0x61b6000 0x1000>; + reg-names = "etm-base", "debug-base"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + qcom,ipc-spinlock@1905000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1905000 0x8000>; + qcom,num-locks = <8>; + }; + + apcs: syscon@0b011008 { + compatible = "syscon"; + reg = <0x0b011008 0x04>; + }; + + tcsr_mutex_block: syscon@01905000 { + compatible = "syscon"; + reg = <0x01905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + smem_mem: smem_region@86300000 { + no-map; + reg = <0x86300000 0x100000>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + modem { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 12>; + qcom,smd-edge = <0>; + qcom,remote-pid = <1>; + label = "mpss"; + + qcom,smd-channels = "IPCRTR"; + qcom,modem_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + adsp { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + label = "adsp"; + + qcom,smd-channels = "IPCRTR"; + qcom,adsp_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + wcnss { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + label = "wcnss"; + + qcom,smd-channels = "IPCRTR"; + qcom,wcnss_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 0>; + qcom,smd-edge = <15>; + label = "rpm"; + + rpm_requests: rpm_requests@0 { + compatible = "qcom,rpm-smd"; + qcom,smd-channels = "rpm_requests"; + }; + }; + + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_apps_fm: qcom,smdtty-apps-fm { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_FM"; + }; + + smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; + }; + + smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; + }; + + smdtty_mbalbridge: qcom,smdtty-mbalbridge { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "MBALBRIDGE"; + }; + + smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; + }; + + smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; + }; + + smdtty_data1: qcom,smdtty-data1 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA1"; + }; + + smdtty_data4: qcom,smdtty-data4 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA4"; + }; + + smdtty_data11: qcom,smdtty-data11 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA11"; + }; + + smdtty_data21: qcom,smdtty-data21 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA21"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; + + qcom,smdpkt { + compatible = "qcom,smdpkt"; + + qcom,smdpkt-data5-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-dev-name = "smdcntl0"; + }; + + qcom,smdpkt-data22 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA22"; + qcom,smdpkt-dev-name = "smd22"; + }; + + qcom,smdpkt-data40-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA40_CNTL"; + qcom,smdpkt-dev-name = "smdcntl8"; + }; + + qcom,smdpkt-data2 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA2"; + qcom,smdpkt-dev-name = "at_mdm0"; + }; + + qcom,smdpkt-apr-apps2 { + qcom,smdpkt-remote = "adsp"; + qcom,smdpkt-port-name = "apr_apps2"; + qcom,smdpkt-dev-name = "apr_apps2"; + }; + + qcom,smdpkt-loopback { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "LOOPBACK"; + qcom,smdpkt-dev-name = "smd_pkt_loopback"; + }; + }; + + qcom_tzlog: tz-log@8600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + bam_dmux: qcom,bam_dmux@4044000 { + compatible = "qcom,bam_dmux"; + reg = <0x4044000 0x19000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + qcom,rx-ring-size = <32>; + qcom,max-rx-mtu = <4096>; + qcom,fast-shutdown; + qcom,no-cpu-affinity; + }; + + sdcc1_ice: sdcc1ice@7803000 { + compatible = "qcom,ice"; + reg = <0x7803000 0x8000>; + interrupt-names = "sdcc_ice_nonsec_level_irq", + "sdcc_ice_sec_level_irq"; + interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>, + <0 313 IRQ_TYPE_LEVEL_HIGH>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&gcc SDCC1_ICE_CORE_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + qcom,op-freq-hz = <200000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <78 512 0 0>, /* No vote */ + <78 512 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm", "qcom,sdhci-msm-cqe"; + reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>, + <0x7803000 0x8000>; + reg-names = "hc_mem", "core_mem", "cqhci_mem", "cqhci_ice"; + + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <13 651>; + + qcom,pm-qos-cpu-groups = <0x0f>; + qcom,pm-qos-cmdq-latency-us = <13 651>; + + qcom,pm-qos-legacy-latency-us = <13 651>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1046 3200>, /* 400 KB/s*/ + <78 512 52286 160000>, /* 20 MB/s */ + <78 512 65360 200000>, /* 25 MB/s */ + <78 512 130718 400000>, /* 50 MB/s */ + <78 512 130718 400000>, /* 100 MB/s */ + <78 512 261438 800000>, /* 200 MB/s */ + <78 512 261438 800000>, /* 400 MB/s */ + <78 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 + 50000000 100000000 200000000 400000000 4294967295>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + qcom,ice-clk-rates = <200000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + status = "disabled"; + }; + + sdhc_2: sdhci@7864900 { + compatible = "qcom,sdhci-msm"; + reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <13 651>; + + qcom,pm-qos-cpu-groups = <0x0f>; + qcom,pm-qos-legacy-latency-us = <13 651>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1046 3200>, /* 400 KB/s*/ + <81 512 52286 160000>, /* 20 MB/s */ + <81 512 65360 200000>, /* 25 MB/s */ + <81 512 130718 400000>, /* 50 MB/s */ + <81 512 261438 800000>, /* 100 MB/s */ + <81 512 261438 800000>, /* 200 MB/s */ + <81 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,devfreq,freq-table = <50000000 200000000>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + status = "disabled"; + }; + + qcom_seecom: qseecom@85b00000 { + compatible = "qcom,qseecom"; + reg = <0x85b00000 0x800000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,support-bus-scaling; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 0 0>, + <55 512 120000 1200000>, + <55 512 393600 3936000>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x04080000 0x100>, + <0x0194f000 0x010>, + <0x01950000 0x008>, + <0x01951000 0x008>, + <0x04020000 0x040>, + <0x01871000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", + "rmb_base", "restart_reg"; + + interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; + vdd_mss-supply = <&pm8937_s1>; + vdd_cx-supply = <&pm8937_s2_level>; + vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_mx-supply = <&pm8937_l3_level_ao>; + vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_pll-supply = <&pm8937_l7>; + qcom,vdd_pll = <1800000>; + vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + + clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>; + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; + + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sequential-fw-load; + qcom,override-acc-1 = <0x80800000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v56-1-8-inrush-current; + qcom,reset-clk; + + /* Inputs from mss */ + /* TBD */ + interrupts-extended = <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Output to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&modem_mem>; + }; + + qcom,lpass@c200000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xc200000 0x00100>; + interrupts = <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>; + + vdd_cx-supply = <&pm8937_s2_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; + + clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,scm_core_clk_src-freq = <80000000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <1>; + qcom,complete-ramdump; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + + /* Inputs from lpass */ + /* TBD */ + interrupts-extended = <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Output to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&adsp_fw_mem>; + }; + + qcom,pronto@a21b000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x0a21b000 0x3000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; + + vdd_pronto_pll-supply = <&pm8937_l7>; + proxy-reg-names = "vdd_pronto_pll"; + vdd_pronto_pll-uV-uA = <1800000 18000>; + clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + + clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,scm_core_clk_src = <80000000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <6>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <422>; + qcom,sysmon-id = <6>; + qcom,ssctl-instance-id = <0x13>; + qcom,firmware-name = "wcnss"; + + /* Inputs from wcnss */ + /* TBD */ + interrupts-extended = <&wcnss_smp2p_in 0 0>, + <&wcnss_smp2p_in 1 0>, + <&wcnss_smp2p_in 2 0>, + <&wcnss_smp2p_in 3 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Output to wcnss */ + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&wcnss_fw_mem>; + }; + + qcom,venus@1de0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1de0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + + clock-names = "core_clk", "iface_clk", "bus_clk", + "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "scm_core_clk", + "scm_iface_clk", "scm_bus_clk", + "scm_core_clk_src"; + qcom,scm_core_clk_src-freq = <80000000>; + + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <9>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&venus_mem>; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_crypto: qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <100000000>; + }; + + qcom_cedev: qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom,adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-legacy-compute"; + qcom,msm_fastrpc_compute_cb { + compatible = "qcom,msm-fastrpc-legacy-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_iommu 0x2008 0x7>; + sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; + }; + }; + + spi_6: spi@7af6000 { /* BLSP2 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x7af6000 0x600>, + <0x7ac4000 0x1d000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, + <0 239 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi6_default &spi6_cs0_active>; + pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <84>; + status = "disabled"; + }; + + qcom,wcnss-wlan@a000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xa000000 0x280000>, + <0xb011008 0x4>, + <0xa21b000 0x3000>, + <0x3204000 0x100>, + <0x3200800 0x200>, + <0xa100400 0x200>, + <0xa205050 0x200>, + <0xa219000 0x20>, + <0xa080488 0x8>, + <0xa080fb0 0x8>, + <0xa08040c 0x8>, + <0xa0120a8 0x8>, + <0xa012448 0x8>, + <0xa080c00 0x1>; + + reg-names = "wcnss_mmio", "wcnss_fiq", + "pronto_phy_base", "riva_phy_base", + "riva_ccu_base", "pronto_a2xb_base", + "pronto_ccpu_base", "pronto_saw2_base", + "wlan_tx_phy_aborts","wlan_brdg_err_source", + "wlan_tx_status", "alarms_txctl", + "alarms_tactl", "pronto_mcu_base"; + + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>; + qcom,pronto-vddcx-supply = <&pm8937_s2_level>; + qcom,pronto-vddpx-supply = <&pm8937_l5>; + qcom,iris-vddxo-supply = <&pm8937_l7>; + qcom,iris-vddrfa-supply = <&pm8937_l19>; + qcom,iris-vddpa-supply = <&pm8937_l9>; + qcom,iris-vdddig-supply = <&pm8937_l5>; + + qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; + qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>; + qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; + qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; + + qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,vddpx-voltage-level = <1800000 0 1800000>; + + qcom,iris-vddxo-current = <10000>; + qcom,iris-vddrfa-current = <100000>; + qcom,iris-vddpa-current = <515000>; + qcom,iris-vdddig-current = <10000>; + + qcom,pronto-vddmx-current = <0>; + qcom,pronto-vddcx-current = <0>; + qcom,pronto-vddpx-current = <0>; + + pinctrl-names = "wcnss_default", "wcnss_sleep", + "wcnss_gpio_default"; + pinctrl-0 = <&wcnss_default>; + pinctrl-1 = <&wcnss_sleep>; + pinctrl-2 = <&wcnss_gpio_default>; + + gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>, + <&tlmm 79 0>, <&tlmm 80 0>; + + clocks = <&rpmcc CXO_SMD_WLAN_CLK>, + <&rpmcc RPM_SMD_RF_CLK2>; + + clock-names = "xo", "rf_clk"; + + qcom,has-autodetect-xo; + qcom,is-pronto-v3; + qcom,has-pronto-hw; + qcom,has-vsys-adc-channel; + qcom,wcnss-adc_tm = <&pm8937_adc_tm>; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + }; +}; + +#include "pm8937-rpm-regulator.dtsi" +#include "msm8917-regulator.dtsi" +#include "pm8937.dtsi" +#include "msm-gdsc-8916.dtsi" +#include "msm8917-thermal.dtsi" + +&gdsc_venus { + clock-names = "bus_clk", "core_clk"; + clocks = <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_VENUS0_VCODEC0_CLK>; + status = "okay"; +}; + +&gdsc_venus_core0 { + qcom,support-hw-trigger; + clock-names ="core0_clk"; + clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>; + status = "okay"; +}; + +&gdsc_mdss { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AXI_CLK>; + status = "okay"; +}; + +&gdsc_jpeg { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>; + status = "okay"; +}; + +&gdsc_vfe { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>; + status = "okay"; +}; + +&gdsc_vfe1 { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + status = "okay"; +}; + +&gdsc_cpp { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>; + status = "okay"; +}; + +&gdsc_oxili_gx { + clock-names = "core_root_clk", "gfx_clk"; + clocks =<&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_GFX3D_CLK>; + qcom,enable-root-clk; + qcom,clk-dis-wait-val = <0x5>; + status = "okay"; +}; + +/* GPU overrides */ +&msm_gpu { + + qcom,gpu-speed-bin-vectors = + <0x6018 0x80000000 31>, + <0x0164 0x00000400 9>; + /delete-node/qcom,gpu-pwrlevels; + + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <598000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <7>; + qcom,bus-max = <7>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <523200000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <484800000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <6>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <8>; + qcom,bus-max = <8>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <523200000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <484800000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <6>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <2>; + qcom,initial-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; diff --git a/qcom/msm8937-audio.dtsi b/qcom/msm8937-audio.dtsi new file mode 100644 index 00000000..2b852e0d --- /dev/null +++ b/qcom/msm8937-audio.dtsi @@ -0,0 +1,480 @@ +#include "msm-audio-lpass.dtsi" +#include "msm8953-wsa881x.dtsi" + +&msm_audio_ion { + iommus = <&apps_iommu 0x2001 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&soc { + qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + msm_audio_apr_dummy { + compatible = "qcom,msm-audio-apr-dummy"; + }; + }; + + qcom,avtimer@c0a300c { + compatible = "qcom,avtimer"; + reg = <0x0c0a300c 0x4>, + <0x0c0a3010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <27>; + }; + + int_codec: sound { + status = "okay"; + compatible = "qcom,msm8952-audio-codec"; + qcom,model = "msm8952-snd-card-mtp"; + reg = <0xc051000 0x4>, + <0xc051004 0x4>, + <0xc055000 0x4>, + <0xc052000 0x4>; + reg-names = "csr_gp_io_mux_mic_ctl", + "csr_gp_io_mux_spkr_ctl", + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel", + "csr_gp_io_mux_quin_ctl"; + + qcom,msm-ext-pa = "primary"; + qcom,msm-mclk-freq = <9600000>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,msm-hs-micbias-type = "external"; + qcom,msm-micbias1-ext-cap; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "SPK_RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "RX_I2S_CLK", "MCLK", + "TX_I2S_CLK", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS External2", "Headset Mic", + "MIC BIAS External", "Secondary Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS External2", + "AMIC3", "MIC BIAS External", + "ADC1_IN", "ADC1_OUT", + "ADC2_IN", "ADC2_OUT", + "ADC3_IN", "ADC3_OUT", + "PDM_IN_RX1", "PDM_OUT_RX1", + "PDM_IN_RX2", "PDM_OUT_RX2", + "PDM_IN_RX3", "PDM_OUT_RX3", + "WSA_SPK OUT", "VDD_WSA_SWITCH", + "SpkrMono WSA_IN", "WSA_SPK OUT"; + + qcom,cdc-us-euro-gpios = <&tlmm 63 0>; + qcom,cdc-us-eu-gpios = <&cdc_us_euro_sw>; + qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>; + qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_pri_auxpcm>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_mi2s5>, + /* TBD + * &sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + * <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, + */ + <&bt_sco_rx>, <&bt_sco_tx>, + <&int_fm_rx>, <&int_fm_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>; + /* TBD + * <&proxy_rx>, <&proxy_tx>; + */ + + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6", + "msm-dai-q6-dev.16384", "msmdai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", + "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770"; + /* TBD + * "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195"; + */ + + asoc-codec = <&stub_codec>, <&msm_digital_codec>, + <&pmic_analog_codec>; + asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec", + "analog-codec"; + asoc-wsa-codec-names = "wsa881x-i2c-codec.2-000f"; + asoc-wsa-codec-prefixes = "SpkrMono"; + msm-vdd-wsa-switch-supply = <&pm8937_l5>; + qcom,msm-vdd-wsa-switch-voltage = <1800000>; + qcom,msm-vdd-wsa-switch-current = <10000>; + }; + + cdc_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cross_conn_det_act>; + pinctrl-1 = <&cross_conn_det_sus>; + }; + + cdc_pri_mi2s_gpios: msm_cdc_pinctrl_pri { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_pdm_lines_act &cdc_pdm_lines_2_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &cdc_pdm_lines_2_sus>; + }; + + cdc_quin_mi2s_gpios: msm_cdc_pinctrl_quin { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_tlmm_lines_act &pri_tlmm_ws_act>; + pinctrl-1 = <&pri_tlmm_lines_sus &pri_tlmm_ws_sus>; + }; + + + i2c@78b6000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + wsa881x_i2c_f: wsa881x-i2c-codec@f { + status = "okay"; + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x0f>; + qcom,wsa-analog-vi-gpio = <&wsa881x_analog_vi_gpio>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; + qcom,wsa-analog-reset-gpio = + <&wsa881x_analog_reset_gpio>; + }; + + wsa881x_i2c_45: wsa881x-i2c-codec@45 { + status = "okay"; + compatible = "qcom,wsa881x-i2c-codec"; + reg = <0x45>; + }; + }; + + wsa881x_analog_vi_gpio: wsa881x_analog_vi_pctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_vi_on>; + pinctrl-1 = <&wsa_vi_off>; + }; + + wsa881x_analog_clk_gpio: wsa881x_analog_clk_pctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_clk_on>; + pinctrl-1 = <&wsa_clk_off>; + }; + + wsa881x_analog_reset_gpio: wsa881x_analog_reset_pctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_reset_on>; + pinctrl-1 = <&wsa_reset_off>; + }; + + ext_codec: sound-9335 { + status = "disabled"; + compatible = "qcom,msm8952-audio-slim-codec"; + qcom,model = "msm8952-tasha-snd-card"; + + reg = <0xc051000 0x4>, + <0xc051004 0x4>, + <0xc055000 0x4>, + <0xc052000 0x4>; + reg-names = "csr_gp_io_mux_mic_ctl", + "csr_gp_io_mux_spkr_ctl", + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel", + "csr_gp_io_mux_quin_ctl"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "AIF4 VI", "MICBIAS_REGULATOR", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AIF4 MAD", "MICBIAS_REGULATOR", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "AMIC6", "MIC BIAS4", + "MIC BIAS4", "Analog Mic6", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "MIC BIAS1", "MICBIAS_REGULATOR", + "MIC BIAS2", "MICBIAS_REGULATOR", + "MIC BIAS3", "MICBIAS_REGULATOR", + "MIC BIAS4", "MICBIAS_REGULATOR", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,tasha-mclk-clk-freq = <9600000>; + qcom,cdc-us-euro-gpios = <&tlmm 63 0>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,cdc-us-eu-gpios = <&cdc_us_euro_sw>; + qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-pcm-dsp-noirq"; + + asoc-cpu = <&dai_pri_auxpcm>, + <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s5>, + /* TBD + * <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + * <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + * <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + */ + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, + /* TBD + * <&sb_5_rx>, <&bt_sco_rx>, <&bt_sco_tx>, + */ + <&int_fm_rx>, <&int_fm_tx>; + /* TBD + * , <&sb_6_rx>, + * <&proxy_rx>, <&proxy_tx>; + */ + + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.5", "msm-dai-q6-dev.16384", + "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", + "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", + "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", + "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", + "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.16394", "msm-dai-q6-dev.12288", + "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292", + "msm-dai-q6-dev.12293", "msm-dai-q6-dev.16396"; + /* TBD + * "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195"; + */ + + asoc-codec = <&stub_codec>, <&hdmi_dba>; + asoc-codec-names = "msm-stub-codec.1", "msm-hdmi-dba-codec-rx"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>, + <&wsa881x_213>, <&wsa881x_214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + }; + + cpe: qcom,msm-cpe-lsm { + compatible = "qcom,msm-cpe-lsm"; + }; + + wcd9xxx_intc: wcd9xxx-irq { + status = "disabled"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 73 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio: audio_ext_clk { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + clock-names = "osr_clk"; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + qcom,audio-ref-clk-gpio = <&pm8937_gpios 1 0>; + clocks = <&rpmcc RPM_SMD_DIV_CLK2>; + pinctrl-0 = <&cdc_mclk2_sleep>; + pinctrl-1 = <&cdc_mclk2_active>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; +}; + +&slim_msm { + status = "disabled"; + + dai_slim: msm_dai_slim { + status = "disabled"; + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; + + wcd9335: tasha_codec { + status = "disabled"; + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 A0 01 17 02]; + + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + /* TODO + * clocks = < &clock_audio clk_audio_pmi_clk>, + * <&clock_audio clk_audio_ap_clk2>; + */ + + qcom,cdc-static-supplies = + "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vdd-px"; + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-dmic-sample-rate = <2400000>; + qcom,cdc-mclk-clk-rate = <9600000>; + + cdc-vdd-buck-supply = <&eldo2_pm8937>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&eldo2_pm8937>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pm8937_l5>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8937_l5>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vdd-px-supply = <&pm8937_l5>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-mic-bias-supply = <&pm8937_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <15000>; + }; +}; + +&pm8937_1 { + pmic_analog_codec: analog-codec@f000 { + status = "okay"; + compatible = "qcom,pmic-analog-codec"; + reg = <0xf000 0x200>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int", + "ear_ocp_int", + "hphr_ocp_int", + "hphl_ocp_det", + "ear_cnp_int", + "hphr_cnp_int", + "hphl_cnp_int"; + + cdc-vdda-cp-supply = <&pm8937_s4>; + qcom,cdc-vdda-cp-voltage = <2050000 2050000>; + qcom,cdc-vdda-cp-current = <210000>; + + cdc-vdd-io-supply = <&pm8937_l5>; + qcom,cdc-vdd-io-voltage = <1800000 1800000>; + qcom,cdc-vdd-io-current = <5000>; + + cdc-vdd-pa-supply = <&pm8937_s4>; + qcom,cdc-vdd-pa-voltage = <1900000 2050000>; + qcom,cdc-vdd-pa-current = <260000>; + + cdc-vdd-mic-bias-supply = <&pm8937_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <5000>; + + qcom,cdc-mclk-clk-rate = <9600000>; + + qcom,cdc-static-supplies = "cdc-vdd-io", + "cdc-vdd-pa", + "cdc-vdda-cp"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + + msm_digital_codec: msm-dig-codec { + compatible = "qcom,msm-digital-codec"; + reg = <0xc0f0000 0x0>; + }; + }; +}; diff --git a/qcom/msm8937-bus.dtsi b/qcom/msm8937-bus.dtsi new file mode 100644 index 00000000..d423704a --- /dev/null +++ b/qcom/msm8937-bus.dtsi @@ -0,0 +1,932 @@ +#include <dt-bindings/msm/msm-bus-ids.h> + +&soc { + /*Version = 11 */ + ad_hoc_bus: ad-hoc-bus@580000 { + compatible = "qcom,msm-bus-device"; + reg = <0x580000 0x16080>, + <0x580000 0x16080>, + <0x400000 0x5A000>, + <0x500000 0x13080>; + reg-names = "snoc-base", "snoc-mm-base", + "bimc-base", "pcnoc-base"; + + /*Buses*/ + fab_bimc: fab-bimc { + cell-id = <MSM_BUS_FAB_BIMC>; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <154>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc BIMC_MSMBUS_CLK>, + <&rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_pcnoc: fab-pcnoc { + cell-id = <MSM_BUS_FAB_PERIPH_NOC>; + label = "fab-pcnoc"; + qcom,fab-dev; + qcom,base-name = "pcnoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc PNOC_MSMBUS_CLK>, + <&rpmcc PNOC_MSMBUS_A_CLK>; + }; + + fab_snoc: fab-snoc { + cell-id = <MSM_BUS_FAB_SYS_NOC>; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc SNOC_MSMBUS_CLK>, + <&rpmcc SNOC_MSMBUS_A_CLK>; + }; + + fab_snoc_mm: fab-snoc-mm { + cell-id = <MSM_BUS_FAB_MMSS_NOC>; + label = "fab-snoc-mm"; + qcom,fab-dev; + qcom,base-name = "snoc-mm-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + qcom,util-fact = <154>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc SYSMMNOC_MSMBUS_CLK>, + <&rpmcc SYSMMNOC_MSMBUS_A_CLK>; + }; + + /*BIMC Masters*/ + mas_apps_proc: mas-apps-proc { + cell-id = <MSM_BUS_MASTER_AMPSS_M0>; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>; + }; + + mas_oxili: mas-oxili { + cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>; + label = "mas-oxili"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>; + }; + + mas_snoc_bimc_0: mas-snoc-bimc-0 { + cell-id = <MSM_BUS_SNOC_BIMC_0_MAS>; + label = "mas-snoc-bimc-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_0>; + }; + + mas_snoc_bimc_2: mas-snoc-bimc-2 { + cell-id = <MSM_BUS_SNOC_BIMC_2_MAS>; + label = "mas-snoc-bimc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_2>; + }; + + mas_snoc_bimc_1: mas-snoc-bimc-1 { + cell-id = <MSM_BUS_SNOC_BIMC_1_MAS>; + label = "mas-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_1>; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = <MSM_BUS_MASTER_TCU_0>; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <2>; + qcom,prio-rd = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>; + }; + + /*PCNOC Masters*/ + mas_spdm: mas-spdm { + cell-id = <MSM_BUS_MASTER_SPDM>; + label = "mas-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&pcnoc_m_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SPDM>; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = <MSM_BUS_MASTER_BLSP_1>; + label = "mas-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = <MSM_BUS_MASTER_BLSP_2>; + label = "mas-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_m_1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>; + }; + + mas_usb_hs1: mas-usb-hs1 { + cell-id = <MSM_BUS_MASTER_USB_HS>; + label = "mas-usb-hs1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "fixed"; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>; + }; + + mas_xi_usb_hs1: mas-xi-usb-hs1 { + cell-id = <MSM_BUS_MASTER_XM_USB_HS1>; + label = "mas-xi-usb-hs1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>; + }; + + mas_crypto: mas-crypto { + cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>; + label = "mas-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>; + }; + + mas_sdcc_1: mas-sdcc-1 { + cell-id = <MSM_BUS_MASTER_SDCC_1>; + label = "mas-sdcc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = <MSM_BUS_MASTER_SDCC_2>; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>; + }; + + mas_snoc_pcnoc: mas-snoc-pcnoc { + cell-id = <MSM_BUS_SNOC_PNOC_MAS>; + label = "mas-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_s_7 + &pcnoc_int_2 &pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>; + }; + + /*SNOC Masters*/ + mas_qdss_bam: mas-qdss-bam { + cell-id = <MSM_BUS_MASTER_QDSS_BAM>; + label = "mas-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <11>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = <MSM_BUS_BIMC_SNOC_MAS>; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&snoc_int_0 + &snoc_int_1 &snoc_int_2>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>; + }; + + mas_jpeg: mas-jpeg { + cell-id = <MSM_BUS_MASTER_JPEG>; + label = "mas-jpeg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_JPEG>; + }; + + mas_mdp: mas-mdp { + cell-id = <MSM_BUS_MASTER_MDP_PORT0>; + label = "mas-mdp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <7>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_MDP>; + }; + + mas_pcnoc_snoc: mas-pcnoc-snoc { + cell-id = <MSM_BUS_PNOC_SNOC_MAS>; + label = "mas-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,qos-mode = "fixed"; + qcom,connections = <&snoc_int_0 + &snoc_int_1 &slv_snoc_bimc_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>; + qcom,blacklist = <&slv_snoc_pcnoc>; + }; + + mas_venus: mas-venus { + cell-id = <MSM_BUS_MASTER_VIDEO_P0>; + label = "mas-venus"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <8>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>; + }; + + mas_vfe0: mas-vfe0 { + cell-id = <MSM_BUS_MASTER_VFE>; + label = "mas-vfe0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <9>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VFE>; + }; + + mas_vfe1: mas-vfe1 { + cell-id = <MSM_BUS_MASTER_VFE1>; + label = "mas-vfe1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <13>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_0>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_VFE1>; + }; + + mas_cpp: mas-cpp { + cell-id = <MSM_BUS_MASTER_CPP>; + label = "mas-cpp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_2>; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,mas-rpm-id = <ICBID_MASTER_CPP>; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = <MSM_BUS_MASTER_QDSS_ETR>; + label = "mas-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <10>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>; + }; + + /*Internal nodes*/ + pcnoc_m_0: pcnoc-m-0 { + cell-id = <MSM_BUS_PNOC_M_0>; + label = "pcnoc-m-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>; + }; + + pcnoc_m_1: pcnoc-m-1 { + cell-id = <MSM_BUS_PNOC_M_1>; + label = "pcnoc-m-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>; + }; + + pcnoc_int_0: pcnoc-int-0 { + cell-id = <MSM_BUS_PNOC_INT_0>; + label = "pcnoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc + &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>; + }; + + pcnoc_int_1: pcnoc-int-1 { + cell-id = <MSM_BUS_PNOC_INT_1>; + label = "pcnoc-int-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc + &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_1>; + }; + + pcnoc_int_2: pcnoc-int-2 { + cell-id = <MSM_BUS_PNOC_INT_2>; + label = "pcnoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_6 &pcnoc_s_8>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>; + }; + + pcnoc_int_3: pcnoc-int-3 { + cell-id = <MSM_BUS_PNOC_INT_3>; + label = "pcnoc-int-3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = < &pcnoc_s_1 &pcnoc_s_0 &pcnoc_s_4 + &slv_gpu_cfg &slv_tcu >; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>; + }; + + pcnoc_s_0: pcnoc-s-0 { + cell-id = <MSM_BUS_PNOC_SLV_0>; + label = "pcnoc-s-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_spdm &slv_pdm &slv_prng + &slv_sdcc_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>; + }; + + pcnoc_s_1: pcnoc-s-1 { + cell-id = <MSM_BUS_PNOC_SLV_1>; + label = "pcnoc-s-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tcsr>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>; + }; + + pcnoc_s_2: pcnoc-s-2 { + cell-id = <MSM_BUS_PNOC_SLV_2>; + label = "pcnoc-s-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_snoc_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>; + }; + + pcnoc_s_3: pcnoc-s-3 { + cell-id = <MSM_BUS_PNOC_SLV_3>; + label = "pcnoc-s-3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_message_ram>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>; + }; + + pcnoc_s_4: pcnoc-s-4 { + cell-id = <MSM_BUS_PNOC_SLV_4>; + label = "pcnoc-s-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_camera_ss_cfg + &slv_disp_ss_cfg &slv_venus_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>; + }; + + pcnoc_s_6: pcnoc-s-6 { + cell-id = <MSM_BUS_PNOC_SLV_6>; + label = "pcnoc-s-6"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tlmm &slv_blsp_1 &slv_blsp_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>; + }; + + pcnoc_s_7: pcnoc-s-7 { + cell-id = <MSM_BUS_PNOC_SLV_7>; + label = "pcnoc-s-7"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_sdcc_1 &slv_pmic_arb>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>; + }; + + pcnoc_s_8: pcnoc-s-8 { + cell-id = <MSM_BUS_PNOC_SLV_8>; + label = "pcnoc-s-8"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_usb_hs &slv_crypto_0_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>; + }; + + qdss_int: qdss-int { + cell-id = <MSM_BUS_SNOC_QDSS_INT>; + label = "qdss-int"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&snoc_int_1 &slv_snoc_bimc_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>; + }; + + snoc_int_0: snoc-int-0 { + cell-id = <MSM_BUS_SNOC_INT_0>; + label = "snoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_lpass + &slv_wcss &slv_kpss_ahb>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>; + }; + + snoc_int_1: snoc-int-1 { + cell-id = <MSM_BUS_SNOC_INT_1>; + label = "snoc-int-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qdss_stm + &slv_imem &slv_snoc_pcnoc>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>; + }; + + snoc_int_2: snoc-int-2 { + cell-id = <MSM_BUS_SNOC_INT_2>; + label = "snoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_cats_0 &slv_cats_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_2>; + }; + /*Slaves*/ + + slv_ebi:slv-ebi { + cell-id = <MSM_BUS_SLAVE_EBI_CH0>; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = <MSM_BUS_BIMC_SNOC_SLV>; + label = "slv-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = <MSM_BUS_SLAVE_SDCC_2>; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>; + }; + + slv_spdm:slv-spdm { + cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>; + }; + + slv_pdm:slv-pdm { + cell-id = <MSM_BUS_SLAVE_PDM>; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PDM>; + }; + + slv_prng:slv-prng { + cell-id = <MSM_BUS_SLAVE_PRNG>; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>; + }; + + slv_tcsr:slv-tcsr { + cell-id = <MSM_BUS_SLAVE_TCSR>; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = <MSM_BUS_SLAVE_SNOC_CFG>; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>; + }; + + slv_message_ram:slv-message-ram { + cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>; + }; + + slv_camera_ss_cfg:slv-camera-ss-cfg { + cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>; + label = "slv-camera-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>; + }; + + slv_disp_ss_cfg:slv-disp-ss-cfg { + cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>; + label = "slv-disp-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>; + }; + + slv_venus_cfg:slv-venus-cfg { + cell-id = <MSM_BUS_SLAVE_VENUS_CFG>; + label = "slv-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>; + }; + + slv_gpu_cfg:slv-gpu-cfg { + cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>; + label = "slv-gpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>; + }; + + slv_tlmm:slv-tlmm { + cell-id = <MSM_BUS_SLAVE_TLMM>; + label = "slv-tlmm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = <MSM_BUS_SLAVE_BLSP_1>; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = <MSM_BUS_SLAVE_BLSP_2>; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = <MSM_BUS_SLAVE_PMIC_ARB>; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>; + }; + + slv_sdcc_1:slv-sdcc-1 { + cell-id = <MSM_BUS_SLAVE_SDCC_1>; + label = "slv-sdcc-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>; + }; + + slv_crypto_0_cfg:slv-crypto-0-cfg { + cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>; + label = "slv-crypto-0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>; + }; + + slv_usb_hs:slv-usb-hs { + cell-id = <MSM_BUS_SLAVE_USB_HS>; + label = "slv-usb-hs"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>; + }; + + slv_tcu:slv-tcu { + cell-id = <MSM_BUS_SLAVE_TCU>; + label = "slv-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_TCU>; + }; + + slv_pcnoc_snoc:slv-pcnoc-snoc { + cell-id = <MSM_BUS_PNOC_SNOC_SLV>; + label = "slv-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,connections = <&mas_pcnoc_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>; + }; + + slv_kpss_ahb:slv-kpss-ahb { + cell-id = <MSM_BUS_SLAVE_APPSS>; + label = "slv-kpss-ahb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>; + }; + + slv_wcss:slv-wcss { + cell-id = <MSM_BUS_SLAVE_WCSS>; + label = "slv-wcss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_WCSS>; + }; + + slv_snoc_bimc_0:slv-snoc-bimc-0 { + cell-id = <MSM_BUS_SNOC_BIMC_0_SLV>; + label = "slv-snoc-bimc-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,connections = <&mas_snoc_bimc_0>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_0>; + }; + + slv_snoc_bimc_1:slv-snoc-bimc-1 { + cell-id = <MSM_BUS_SNOC_BIMC_1_SLV>; + label = "slv-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc_1>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_1>; + }; + + slv_snoc_bimc_2:slv-snoc-bimc-2 { + cell-id = <MSM_BUS_SNOC_BIMC_2_SLV>; + label = "slv-snoc-bimc-2"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,connections = <&mas_snoc_bimc_2>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_2>; + }; + + slv_imem:slv-imem { + cell-id = <MSM_BUS_SLAVE_OCIMEM>; + label = "slv-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>; + }; + + slv_snoc_pcnoc:slv-snoc-pcnoc { + cell-id = <MSM_BUS_SNOC_PNOC_SLV>; + label = "slv-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_pcnoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_PCNOC>; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = <MSM_BUS_SLAVE_QDSS_STM>; + label = "slv-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>; + }; + + slv_cats_0:slv-cats-0 { + cell-id = <MSM_BUS_SLAVE_CATS_128>; + label = "slv-cats-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc_mm>; + qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>; + }; + + slv_cats_1:slv-cats-1 { + cell-id = <MSM_BUS_SLAVE_OCMEM_64>; + label = "slv-cats-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_CATS_1>; + }; + + slv_lpass:slv-lpass { + cell-id = <MSM_BUS_SLAVE_LPASS>; + label = "slv-lpass"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>; + }; + }; + +}; diff --git a/qcom/msm8937-camera.dtsi b/qcom/msm8937-camera.dtsi new file mode 100644 index 00000000..76bf8072 --- /dev/null +++ b/qcom/msm8937-camera.dtsi @@ -0,0 +1,517 @@ +&soc { + qcom,msm-cam@1b00000 { + compatible = "qcom,msm-cam"; + reg = <0x1b00000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 160000000 320000000 320000000>; + }; + + qcom,csiphy@1b34000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b34000 0x1000>, + <0x1b00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0>; + }; + + qcom,csiphy@1b35000 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b35000 0x1000>, + <0x1b00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0>; + }; + + qcom,csid@1b30000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csid-v3.4.2", "qcom,csid"; + reg = <0x1b30000 0x400>; + reg-names = "csid"; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi0_phy_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; + }; + + qcom,csid@1b30400 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csid-v3.4.2", "qcom,csid"; + reg = <0x1b30400 0x400>; + reg-names = "csid"; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi1_phy_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; + }; + + qcom,csid@1b30800 { + status = "ok"; + cell-index = <2>; + compatible = "qcom,csid-v3.4.2", "qcom,csid"; + reg = <0x1b30800 0x400>; + reg-names = "csid"; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8937_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi2_phy_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>; + }; + + qcom,ispif@1b31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0x1b31000 0x500>, + <0x1b00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + vfe0-vdd-supply = <&gdsc_vfe>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "vfe0-vdd", "vfe1-vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "ispif_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_ahb_src", + "csi0_src_clk", "csi0_clk", + "csi0_rdi_clk", "csi0_pix_clk", + "csi1_src_clk", "csi1_clk", + "csi1_rdi_clk", "csi1_pix_clk", + "csi2_src_clk", "csi2_clk", + "csi2_rdi_clk", "csi2_pix_clk", + "vfe0_clk_src", "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", "vfe1_clk_src", + "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; + qcom,clock-rates = <61540000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-cntl-support; + qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE"; + }; + + vfe0: qcom,vfe0@1b10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0x1b10000 0x1000>, + <0x1b40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + vfe1: qcom,vfe1@1b14000 { + cell-index = <1>; + compatible = "qcom,vfe40"; + reg = <0x1b14000 0x1000>, + <0x1ba0000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk" , "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + qcom,cam_smmu { + status = "ok"; + compatible = "qcom,msm-cam-smmu"; + msm_cam_smmu_cb1: msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x400 0x00>, + <&apps_iommu 0x2400 0x00>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2: msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + label = "vfe_secure"; + qcom,secure-context; + }; + + msm_cam_smmu_cb3: msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1c00 0x00>; + label = "cpp"; + }; + + msm_cam_smmu_cb4: msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1800 0x00>; + label = "jpeg_enc0"; + }; + }; + + qcom,jpeg@1b1c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0x1b1c000 0x400>, + <0x1b60000 0xc30>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + qcom,vdd-names = "vdd"; + clock-names = "core_clk", "iface_clk", "bus_clk0", + "camss_top_ahb_clk", "camss_ahb_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + qcom,clock-rates = <266670000 0 0 0 0>; + qcom,qos-reg-settings = <0x28 0x0000555e>, + <0xc8 0x00005555>; + qcom,vbif-reg-settings = <0xc0 0x10101000>, + <0xb0 0x10100010>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 800000 800000>; + }; + + qcom,cpp@1b04000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0x1b04000 0x100>, + <0x1b80000 0x200>, + <0x1b18000 0x018>, + <0x1858078 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CPP_CLK_SRC>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>, + <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cpp_core_clk", + "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk", + "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk", + "micro_iface_clk", "camss_ahb_clk"; + qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>; + qcom,min-clock-rate = <133000000>; + resets = <&gcc GCC_CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,bus-master = <1>; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <156>; + qcom,plane-base = <141>; + qcom,stripe-size = <27>; + qcom,plane-size = <5>; + qcom,fe-ptr-off = <5>; + qcom,we-ptr-off = <11>; + }; + }; + + cci: qcom,cci@1b0c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0x1b0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cci"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CCI_CLK_SRC>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cci_src_clk", + "cci_ahb_clk", "camss_cci_clk", + "camss_ahb_clk", "camss_top_ahb_clk"; + qcom,clock-rates = <61540000 19200000 0 0 0 0>, + <61540000 37500000 0 0 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 30 0>, + <&tlmm 31 0>, + <&tlmm 32 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <20>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <32>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <15>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <25>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <19>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/qcom/msm8937-coresight.dtsi b/qcom/msm8937-coresight.dtsi new file mode 100644 index 00000000..cbaa44a9 --- /dev/null +++ b/qcom/msm8937-coresight.dtsi @@ -0,0 +1,1203 @@ +&soc { + tmc_etr: tmc@6028000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6028000 0x1000>, + <0x6044000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "byte-cntr-irq"; + + arm,buffer-size = <0x100000>; + arm,sg-enable; + qcom,force-reg-dump; + + coresight-name = "coresight-tmc-etr"; + coresight-csr = <&csr>; + coresight-ctis = <&cti0 &cti8>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@6027000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6027000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-csr = <&csr>; + + arm,default-sink; + qcom,force-reg-dump; + + coresight-ctis = <&cti0 &cti8>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + tmc_etf_out_replicator:endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_tmc_etf>; + }; + }; + }; + }; + + replicator: replicator@6026000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6026000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator>; + }; + }; + + port@1 { + reg = <0>; + replicator_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + funnel_in0: funnel@6021000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6021000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + funnel_in0_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_in0>; + }; + }; + + port@1 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + + port@2 { + reg = <6>; + funnel_in0_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_in0>; + }; + }; + + port@3 { + reg = <3>; + funnel_in0_in_funnel_center: endpoint { + slave-mode; + remote-endpoint = + <&funnel_center_out_funnel_in0>; + }; + }; + + port@4 { + reg = <4>; + funnel_in0_in_funnel_right: endpoint { + slave-mode; + remote-endpoint = + <&funnel_right_out_funnel_in0>; + }; + }; + + port@5 { + reg = <5>; + funnel_in0_in_funnel_mm: endpoint { + slave-mode; + remote-endpoint = + <&funnel_mm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_center: funnel@6100000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6100000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-center"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + funnel_center_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_center>; + }; + }; + + port@1 { + reg = <0>; + funnel_center_in_rpm_etm0: endpoint { + slave-mode; + remote-endpoint = + <&rpm_etm0_out_funnel_center>; + }; + }; + + port@2 { + reg = <2>; + funnel_center_in_dbgui: endpoint { + slave-mode; + remote-endpoint = + <&dbgui_out_funnel_center>; + }; + }; + }; + }; + + funnel_right: funnel@6120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6120000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-right"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + funnel_right_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_right>; + }; + }; + + port@1 { + reg = <1>; + funnel_right_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_right>; + }; + }; + + port@2 { + reg = <2>; + funnel_right_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_right>; + }; + }; + }; + }; + + funnel_mm: funnel@6130000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6130000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-mm"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + funnel_mm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_mm>; + }; + }; + + port@1 { + reg = <0>; + funnel_mm_in_wcn_etm0: endpoint { + slave-mode; + remote-endpoint = + <&wcn_etm0_out_funnel_mm>; + }; + }; + + port@2 { + reg = <4>; + funnel_mm_in_funnel_cam: endpoint { + slave-mode; + remote-endpoint = + <&funnel_cam_out_funnel_mm>; + }; + }; + + port@3 { + reg = <5>; + funnel_mm_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_mm>; + }; + }; + + port@4 { + reg = <6>; + funnel_mm_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_mm>; + }; + }; + }; + }; + + funnel_cam: funnel@6132000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6132000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-cam"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + funnel_cam_out_funnel_mm: endpoint { + remote-endpoint = <&funnel_mm_in_funnel_cam>; + }; + }; + }; + + funnel_apss: funnel@61a1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x61a1000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + funnel_apss_out_funnel_right: endpoint { + remote-endpoint = + <&funnel_right_in_funnel_apss>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss0_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss0>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss0_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss0>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss0_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss0>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss0_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss0>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss0_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss0>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss0_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss0>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss0_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss0>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss0_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss0>; + }; + }; + }; + }; + + etm4: etm@619c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x619c000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm4_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm4>; + }; + }; + }; + + etm5: etm@619d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x619d000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm5_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm5>; + }; + }; + }; + + etm6: etm@619e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x619e000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm6_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm6>; + }; + }; + }; + + etm7: etm@619f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x619f000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm7_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm7>; + }; + }; + }; + + etm0: etm@61bc000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bc000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm0>; + }; + }; + }; + + etm1: etm@61bd000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bd000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm1>; + }; + }; + }; + + etm2: etm@61be000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61be000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm2_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm2>; + }; + }; + }; + + etm3: etm@61bf000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bf000 0x1000>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + cpu = <&CPU3>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + etm3_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm3>; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x9280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti8"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti9"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti10"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti11"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti12"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti13"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti14"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti15"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu0: cti@61b8000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x61b8000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu1: cti@61b9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x61b9000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@61ba000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x61ba000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@61bb000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x61bb000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@6198000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6198000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@6199000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6199000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@619a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x619a000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@619b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x619b000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + qcom,cti-save; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_modem_cpu0: cti@6124000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6124000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-modem-cpu0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + /* Venus CTI */ + cti_video_cpu0: cti@6035000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6035000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-video-cpu0"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + /* Pronto CTI */ + cti_wcn_cpu0: cti@6039000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x6039000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-wcn-cpu0"; + + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + /* LPASS CTI */ + cti_audio_cpu0: cti@613c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x613c000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-audio-cpu0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + cti_rpm_cpu0: cti@610c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + + reg = <0x610c000 0x1000>; + reg-names = "cti-base"; + coresight-name = "coresight-cti-rpm-cpu0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + /* Pronto ETM */ + wcn_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-wcn-etm0"; + qcom,inst-id = <3>; + + port { + wcn_etm0_out_funnel_mm: endpoint { + remote-endpoint = <&funnel_mm_in_wcn_etm0>; + }; + }; + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-rpm-etm0"; + qcom,inst-id = <4>; + + port { + rpm_etm0_out_funnel_center: endpoint { + remote-endpoint = <&funnel_center_in_rpm_etm0>; + }; + }; + }; + + /* LPASS ETM */ + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_mm: endpoint { + remote-endpoint = <&funnel_mm_in_audio_etm0>; + }; + }; + }; + + /* MSS_SCL */ + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_right: endpoint { + remote-endpoint = <&funnel_right_in_modem_etm0>; + }; + }; + }; + + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + coresight-name = "coresight-csr"; + + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + + dbgui: dbgui@6108000 { + compatible = "qcom,coresight-dbgui"; + reg = <0x6108000 0x1000>; + reg-names = "dbgui-base"; + coresight-name = "coresight-dbgui"; + + qcom,dbgui-addr-offset = <0x30>; + qcom,dbgui-data-offset = <0x130>; + qcom,dbgui-size = <64>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + dbgui_out_funnel_center: endpoint { + remote-endpoint = <&funnel_center_in_dbgui>; + }; + }; + }; + + tpda: tpda@6003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + + reg = <0x6003000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <64>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + tpda_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@6110000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6110000 0x1000>; + reg-names = "tpdm-base"; + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + hwevent: hwevent@6101000 { + compatible = "qcom,coresight-hwevent"; + + reg = <0x6101000 0x148>, + <0x6101fb0 0x4>, + <0x6121000 0x148>, + <0x6121fb0 0x4>, + <0x6131000 0x148>, + <0x6131fb0 0x4>, + <0x78c5010 0x4>, + <0x7885010 0x4>; + + reg-names = "center-wrapper-mux", "center-wrapper-lockaccess", + "right-wrapper-mux", "right-wrapper-lockaccess", + "mm-wrapper-mux", "mm-wrapper-lockaccess", + "usbbam-mux", "blsp-mux"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk"; + }; + +}; diff --git a/qcom/msm8937-cpu.dtsi b/qcom/msm8937-cpu.dtsi new file mode 100644 index 00000000..a39b6e93 --- /dev/null +++ b/qcom/msm8937-cpu.dtsi @@ -0,0 +1,225 @@ +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1126>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1126>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1126>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1126>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_1>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_1>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_1>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_1>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + }; + + energy_costs: energy-costs { + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 512 623 + 731 917 + 805 1106 + 914 1432 + 1024 1740 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 333 70 + 532 114 + 599 141 + 665 178 + 732 213 + >; + }; + }; +}; diff --git a/qcom/msm8937-gpu.dtsi b/qcom/msm8937-gpu.dtsi new file mode 100644 index 00000000..0571cc1a --- /dev/null +++ b/qcom/msm8937-gpu.dtsi @@ -0,0 +1,234 @@ +&soc { + msm_bus: qcom,kgsl-busmon { + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + /* + * active-only flag is used while registering the bus + * governor.It helps release the bus vote when the CPU + * subsystem is inactiv3 + */ + qcom,active-only; + qcom,bw-tbl = + < 0 >, /* off */ + < 769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */ + < 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */ + < 2124 >, /* 3. DDR:278.40 MHz BIMC: 139.20 MHz */ + < 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */ + < 4101 >, /* 5. DDR:537.60 MHz BIMC: 268.80 MHz */ + < 4248 >, /* 6. DDR:556.80 MHz BIMC: 278.40 MHz */ + < 5346 >, /* 7. DDR:662.40 MHz BIMC: 331.20 MHz */ + < 5712 >, /* 8. DDR:748.80 MHz BIMC: 374.40 MHz */ + < 6152 >, /* 9. DDR:806.40 MHz BIMC: 403.20 MHz */ + < 7031 >; /* 10. DDR:921.60 MHz BIMC: 460.80 MHz */ + }; + + msm_gpu: qcom,kgsl-3d0@1c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x1c00000 0x40000 + 0xa0000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", "qfprom_memory"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + qcom,chipid = <0x05000500>; + + qcom,initial-pwrlevel = <2>; + + qcom,idle-timeout = <80>; //msecs + qcom,strtstp-sleepwake; + + qcom,highest-bank-bit = <14>; + + qcom,snapshot-size = <1048576>; //bytes + + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GCC_OXILI_TIMER_CLK>, + <&gcc GCC_OXILI_AON_CLK>; + + clock-names = "core_clk", "iface_clk", + "mem_iface_clk", "alt_mem_iface_clk", + "rbbmtimer_clk", "alwayson_clk"; + + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,bus-width = <16>; + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <11>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, /* off */ + <26 512 0 806400>, /* 1. 100.80 MHz */ + <26 512 0 1689600>, /* 2. 211.20 MHz */ + <26 512 0 2227200>, /* 3. 278.40 MHz */ + <26 512 0 3072000>, /* 4. 384.00 MHz */ + <26 512 0 4300800>, /* 5. 537.60 MHz */ + <26 512 0 4454400>, /* 6. 556.80 MHz */ + <26 512 0 5299200>, /* 7. 662.40 MHz */ + <26 512 0 5990400>, /* 8. 748.80 MHz */ + <26 512 0 6451200>, /* 9. 806.40 MHz */ + <26 512 0 7372800>; /* 10. 921.60 MHz */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_oxili_cx>; + vdd-supply = <&gdsc_oxili_gx>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <360>; + qcom,pm-qos-wakeup-latency = <360>; + + /* Quirks */ + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-dp2clockgating-disable; + qcom,gpu-quirk-lmloadkill-disable; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <1>; + + /* Enable gpu cooling device */ + #cooling-cells = <2>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + qcom,mempool-max-pages = <32768>; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <65536>; + }; + }; + + qcom,gpu-coresights { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-coresight"; + + /* Trace bus */ + qcom,gpu-coresight@0 { + reg = <0>; + coresight-name = "coresight-gfx"; + coresight-atid = <67>; + port { + gfx_out_funnel_mm: endpoint { + remote-endpoint = + <&funnel_mm_in_gfx>; + }; + }; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <450000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <9>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <375000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <300000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <216000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@1c40000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x1c40000 0x10000>; + qcom,protect = <0x40000 0x10000>; + qcom,micro-mmu-control = <0x6000>; + + clocks = <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>; + + clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0>; + qcom,gpu-offset = <0x48000>; + }; + }; +}; diff --git a/qcom/msm8937-interposer-sdm429-cdp.dts b/qcom/msm8937-interposer-sdm429-cdp.dts new file mode 100644 index 00000000..2a85d990 --- /dev/null +++ b/qcom/msm8937-interposer-sdm429-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm429.dtsi" +#include "sdm429-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM429 CDP"; + compatible = "qcom,msm8937-cdp", "qcom,msm8937", "qcom,cdp"; + qcom,board-id = <1 3>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/msm8937-interposer-sdm429-mtp.dts b/qcom/msm8937-interposer-sdm429-mtp.dts new file mode 100644 index 00000000..ae35852e --- /dev/null +++ b/qcom/msm8937-interposer-sdm429-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm429.dtsi" +#include "sdm429-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM429 MTP"; + compatible = "qcom,msm8937-mtp", "qcom,msm8937", "qcom,mtp"; + qcom,board-id = <8 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/msm8937-interposer-sdm429.dts b/qcom/msm8937-interposer-sdm429.dts new file mode 100644 index 00000000..dd794d21 --- /dev/null +++ b/qcom/msm8937-interposer-sdm429.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm429.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8953 + PMI632 SOC"; + compatible = "qcom,msm8953"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/msm8937-interposer-sdm429.dtsi b/qcom/msm8937-interposer-sdm429.dtsi new file mode 100644 index 00000000..85cd896b --- /dev/null +++ b/qcom/msm8937-interposer-sdm429.dtsi @@ -0,0 +1,59 @@ +#include "msm8937-interposer-sdm439.dtsi" +#include "sdm429-cpu.dtsi" + +&soc { + /delete-node/ etm@619c000; + /delete-node/ etm@619d000; + /delete-node/ etm@619e000; + /delete-node/ etm@619f000; + /delete-node/ cti@6198000; + /delete-node/ cti@6199000; + /delete-node/ cti@619a000; + /delete-node/ cti@619b000; + /delete-node/ jtagmm@619c000; + /delete-node/ jtagmm@619d000; + /delete-node/ jtagmm@619e000; + /delete-node/ jtagmm@619f000; + /delete-node/ qcom,cpu4-cpugrp; + + qcom,spm@b1d2000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0 { + /delete-node/qcom,pm-cluster@1; + }; + }; +}; + +&funnel_apss { + ports { + /delete-node/ port@1; + /delete-node/ port@2; + /delete-node/ port@3; + /delete-node/ port@4; + }; +}; + +&thermal_zones { + hexa-cpu-max-step { + cooling-maps { + /delete-node/ cpu4_cdev; + /delete-node/ cpu5_cdev; + /delete-node/ cpu6_cdev; + /delete-node/ cpu7_cdev; + }; + }; + + /delete-node/ cpuss0-step; + + quiet-therm-step { + cooling-maps { + /delete-node/ skin_cpu4; + /delete-node/ skin_cpu5; + /delete-node/ skin_cpu6; + /delete-node/ skin_cpu7; + }; + }; +}; diff --git a/qcom/msm8937-interposer-sdm439-cdp.dts b/qcom/msm8937-interposer-sdm439-cdp.dts new file mode 100644 index 00000000..01353a3d --- /dev/null +++ b/qcom/msm8937-interposer-sdm439-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm439.dtsi" +#include "sdm439-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 CDP"; + compatible = "qcom,msm8937-cdp", "qcom,msm8937", "qcom,cdp"; + qcom,board-id = <1 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/msm8937-interposer-sdm439-mtp.dts b/qcom/msm8937-interposer-sdm439-mtp.dts new file mode 100644 index 00000000..b734cbdf --- /dev/null +++ b/qcom/msm8937-interposer-sdm439-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm439.dtsi" +#include "sdm439-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 MTP"; + compatible = "qcom,msm8937-mtp", "qcom,msm8937", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/msm8937-interposer-sdm439-qrd.dts b/qcom/msm8937-interposer-sdm439-qrd.dts new file mode 100644 index 00000000..66e2757e --- /dev/null +++ b/qcom/msm8937-interposer-sdm439-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm439.dtsi" +#include "sdm439-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 QRD"; + compatible = "qcom,msm8937-qrd", "qcom,msm8937", "qcom,qrd"; + qcom,board-id = <0xb 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/msm8937-interposer-sdm439.dts b/qcom/msm8937-interposer-sdm439.dts new file mode 100644 index 00000000..57d2674e --- /dev/null +++ b/qcom/msm8937-interposer-sdm439.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "msm8937-interposer-sdm439.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8953 + PMI632 SOC"; + compatible = "qcom,msm8953"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/msm8937-interposer-sdm439.dtsi b/qcom/msm8937-interposer-sdm439.dtsi new file mode 100644 index 00000000..543e3632 --- /dev/null +++ b/qcom/msm8937-interposer-sdm439.dtsi @@ -0,0 +1,172 @@ +#include "msm8937.dtsi" +#include "sdm439-pm8953.dtsi" +#include "sdm439-audio.dtsi" +#include "sdm439-pmi632.dtsi" + +&pm8953_s5 { + regulator-min-microvolt = <1155000>; + regulator-max-microvolt = <1350000>; +}; + +&pm8953_s5_limit { + regulator-min-microvolt = <1155000>; + regulator-max-microvolt = <1350000>; +}; + +&soc { + qcom,csiphy@1b34000 { + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + }; + + qcom,csiphy@1b35000 { + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + }; + + qcom,csid@1b30000 { + qcom,mipi-csi-vdd-supply = <&pm8953_l2>; + }; + + qcom,csid@1b30400 { + qcom,mipi-csi-vdd-supply = <&pm8953_l2>; + }; + + qcom,csid@1b30800 { + qcom,mipi-csi-vdd-supply = <&pm8953_l2>; + }; + + mem_acc_vreg_corner: regulator@01946004 { + compatible = "qcom,mem-acc-regulator"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-reg-addr-list = + <0x01942138 0x01942130 0x01942120 + 0x01942124 0x01946000 0x01946004>; + + qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>, <6 0x55>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + < 3 0x0>, < 4 0x0>, < 5 0x0>; + + qcom,corner2-reg-config = + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>, < 5 0x0>; + + qcom,corner3-reg-config = + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; + qcom,cpr-voltage-floor = <1050000 1050000 1090000>; + vdd-apc-supply = <&pm8953_s5>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <10>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <4>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,cpr-fuse-row = <67 0>; + qcom,cpr-fuse-target-quot = <42 24 6>; + qcom,cpr-fuse-ro-sel = <60 57 54>; + qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>; + qcom,cpr-fuse-init-voltage = + <67 36 6 0>, + <67 18 6 0>, + <67 0 6 0>; + qcom,cpr-fuse-quot-offset = + <71 26 6 0>, + <71 20 6 0>, + <70 54 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 960000000>, + <2 1094400000>, + <3 1209600000>, + <4 1248000000>, + <5 1344000000>, + <6 1401000000>, + <7 1497600000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 0 1 2 6>, + <1 0 1 2 7>, + <2 0 1 2 3>; + qcom,cpr-fuse-revision = <69 39 3 0>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-fuse-version-map = + <0 (-1) 1 (-1) (-1) (-1)>, + <(-1) (-1) 2 (-1) (-1) (-1)>, + <(-1) (-1) 3 (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1)>; + qcom,cpr-quotient-adjustment = + <(-20) (-40) (-20)>, + <0 (-40) (20)>, + <0 0 (20)>, + <0 0 0>; + qcom,cpr-init-voltage-adjustment = + <0 0 0>, + <(10000) (15000) (20000)>, + <0 0 0>, + <0 0 0>; + qcom,cpr-enable; + }; + + qcom,cpu-clock-8939@b111050 { + vdd-c0-supply = <&apc_vreg_corner>; + vdd-c1-supply = <&apc_vreg_corner>; + vdd-cci-supply = <&apc_vreg_corner>; + }; +}; + +&mdss_dsi { + vdda-supply = <&pm8953_l2>; + vddio-supply = <&pm8953_l6>; +}; diff --git a/qcom/msm8937-ion.dtsi b/qcom/msm8937-ion.dtsi new file mode 100644 index 00000000..86feded8 --- /dev/null +++ b/qcom/msm8937-ion.dtsi @@ -0,0 +1,30 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + reg = <8>; + memory-region = <&secure_mem>; + qcom,ion-heap-type = "SECURE_DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/msm8937-mdss-panels.dtsi b/qcom/msm8937-mdss-panels.dtsi new file mode 100644 index 00000000..46dced54 --- /dev/null +++ b/qcom/msm8937-mdss-panels.dtsi @@ -0,0 +1,84 @@ +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-truly-1080p-video.dtsi" +#include "dsi-panel-truly-1080p-cmd.dtsi" +#include "dsi-panel-truly-720p-video.dtsi" +#include "dsi-panel-truly-720p-cmd.dtsi" +#include "dsi-panel-r69006-1080p-cmd.dtsi" +#include "dsi-panel-r69006-1080p-video.dtsi" +#include "dsi-panel-hx8394f-720p-video.dtsi" +#include "dsi-adv7533-1080p.dtsi" +#include "dsi-adv7533-720p.dtsi" +#include "dsi-panel-hx8399c-fhd-plus-video.dtsi" +#include "dsi-panel-hx8399c-hd-plus-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-icn9706-720-1440p-video.dtsi" +#include "dsi-panel-edo-rm67162-qvga-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2850000>; + qcom,supply-max-voltage = <2850000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <10>; + }; + }; + + dsi_pm660_panel_pwr_supply: dsi_pm660_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; +}; diff --git a/qcom/msm8937-mdss-pll.dtsi b/qcom/msm8937-mdss-pll.dtsi new file mode 100644 index 00000000..56d7c1e0 --- /dev/null +++ b/qcom/msm8937-mdss-pll.dtsi @@ -0,0 +1,91 @@ +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@1a94a00 { + compatible = "qcom,mdss_dsi_pll_28lpm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x001a94a00 0xd4>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + vddio-supply = <&pm8937_l6>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <30000>; + qcom,ssc-ppm = <5000>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 { + compatible = "qcom,mdss_dsi_pll_28lpm"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + + reg = <0x001a96a00 0xd4>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + vddio-supply = <&pm8937_l6>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <30000>; + qcom,ssc-ppm = <5000>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + }; +}; diff --git a/qcom/msm8937-mdss.dtsi b/qcom/msm8937-mdss.dtsi new file mode 100644 index 00000000..2342d00a --- /dev/null +++ b/qcom/msm8937-mdss.dtsi @@ -0,0 +1,401 @@ +&soc { + mdss_mdp: qcom,mdss_mdp@1a00000 { + compatible = "qcom,mdss_mdp"; + reg = <0x01a00000 0x90000>, + <0x01ab0000 0x1040>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + vdd-supply = <&gdsc_mdss>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_mdp"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + /* Fudge factors */ + qcom,mdss-ab-factor = <1 1>; /* 1 time */ + qcom,mdss-ib-factor = <1 1>; /* 1 time */ + qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ + + qcom,max-mixer-width = <2048>; + qcom,max-pipe-width = <2048>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; + qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; + + qcom,mdss-has-panic-ctrl; + qcom,mdss-per-pipe-panic-luts = <0x000f>, + <0xffff>, + <0xfffc>, + <0xff00>; + + qcom,mdss-mdp-reg-offset = <0x00001000>; + qcom,max-bandwidth-low-kbps = <3100000>; + qcom,max-bandwidth-high-kbps = <3100000>; + qcom,max-bandwidth-per-pipe-kbps = <2300000>; + + /* Bandwidth limit settings */ + qcom,max-bw-settings = <1 3100000>, /* Default */ + <2 1700000>; /* Camera */ + + qcom,max-clk-rate = <320000000>; + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <16>; + + qcom,mdss-pipe-vig-off = <0x00005000>; + qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>; + qcom,mdss-pipe-dma-off = <0x00025000>; + qcom,mdss-pipe-cursor-off = <0x00035000>; + + qcom,mdss-pipe-vig-xin-id = <0>; + qcom,mdss-pipe-rgb-xin-id = <1 5>; + qcom,mdss-pipe-dma-xin-id = <2>; + qcom,mdss-pipe-cursor-xin-id = <7>; + + /* Offsets relative to "mdp_phys + mdp-reg-offset" address */ + qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>; + qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>, + <0x2B4 4 8>; + qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>; + qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>; + + + qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400>; + qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>; + qcom,mdss-dspp-off = <0x00055000>; + qcom,mdss-wb-off = <0x00065000 0x00066000>; + qcom,mdss-intf-off = <0x00000000 0x0006B800 0x0006C000>; + qcom,mdss-pingpong-off = <0x00071000 0x00071800>; + qcom,mdss-slave-pingpong-off = <0x00073000>; + qcom,mdss-cdm-off = <0x0007a200>; + qcom,mdss-wfd-mode = "intf"; + qcom,mdss-highest-bank-bit = <0x1>; + qcom,mdss-has-decimation; + qcom,mdss-has-non-scalar-rgb; + qcom,mdss-has-rotator-downscale; + qcom,mdss-rot-downscale-min = <2>; + qcom,mdss-rot-downscale-max = <16>; + qcom,mdss-idle-power-collapse-enabled; + qcom,mdss-rot-block-size = <64>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MDP_CLK_SRC>, + <&gcc_mdss MDSS_MDP_VOTE_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", "bus_clk", "core_clk_src", + "core_clk", "vsync_clk"; + + qcom,mdp-settings = <0x0506c 0x00000000>, + <0x1506c 0x00000000>, + <0x1706c 0x00000000>, + <0x2506c 0x00000000>; + + qcom,vbif-settings = <0x0d0 0x00000010>; + + qcom,regs-dump-mdp = <0x01000 0x01454>, + <0x02000 0x02064>, + <0x02200 0x02264>, + <0x02400 0x02464>, + <0x05000 0x05150>, + <0x05200 0x05230>, + <0x15000 0x15150>, + <0x17000 0x17150>, + <0x25000 0x25150>, + <0x35000 0x35150>, + <0x45000 0x452bc>, + <0x46000 0x462bc>, + <0x55000 0x5522c>, + <0x65000 0x652c0>, + <0x66000 0x662c0>, + <0x6b800 0x6ba68>, + <0x6c000 0x6c268>, + <0x71000 0x710d4>, + <0x71800 0x718d4>; + + qcom,regs-dump-names-mdp = "MDP", + "CTL_0", "CTL_1", "CTL_2", + "VIG0_SSPP", "VIG0", + "RGB0_SSPP", "RGB1_SSPP", + "DMA0_SSPP", + "CURSOR0_SSPP", + "LAYER_0", "LAYER_1", + "DSPP_0", + "WB_0", "WB_2", + "INTF_1", "INTF_2", + "PP_0", "PP_1"; + + /* buffer parameters to calculate prefill bandwidth */ + qcom,mdss-prefill-outstanding-buffer-bytes = <0>; + qcom,mdss-prefill-y-buffer-bytes = <0>; + qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; + qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; + qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>; + qcom,mdss-prefill-pingpong-buffer-pixels = <4096>; + + qcom,mdss-pp-offsets { + qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; + qcom,mdss-sspp-vig-pcc-off = <0x1780>; + qcom,mdss-sspp-rgb-pcc-off = <0x380>; + qcom,mdss-sspp-dma-pcc-off = <0x380>; + qcom,mdss-lm-pgc-off = <0x3C0>; + qcom,mdss-dspp-pcc-off = <0x1700>; + qcom,mdss-dspp-pgc-off = <0x17C0>; + }; + + qcom,mdss-reg-bus { + /* Reg Bus Scale Settings */ + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 160000>, + <1 590 0 320000>; + }; + + qcom,mdss-hw-rt-bus { + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_hw_rt"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + }; + + smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { + compatible = "qcom,smmu_mdp_unsec"; + iommus = <&apps_iommu 0x2800 0>; /* For NS ctx bank */ + }; + + smmu_mdp_sec: qcom,smmu_mdp_sec_cb { + compatible = "qcom,smmu_mdp_sec"; + iommus = <&apps_iommu 0x2801 0>; /* For SEC Ctx Bank */ + }; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + qcom,cont-splash-memory { + linux,contiguous-region = <&cont_splash_mem>; + }; + }; + + mdss_fb1: qcom,mdss_fb_wfd { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb2: qcom,mdss_fb_secondary { + cell-index = <2>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_dsi: qcom,mdss_dsi@0 { + compatible = "qcom,mdss-dsi"; + hw-config = "single_dsi"; + #address-cells = <1>; + #size-cells = <1>; + gdsc-supply = <&gdsc_mdss>; + vdda-supply = <&pm8937_l2>; + vddio-supply = <&pm8937_l6>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_dsi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + + ranges = <0x1a94000 0x1a94000 0x300 + 0x1a94400 0x1a94400 0x280 + 0x1a94b80 0x1a94b80 0x30 + 0x193e000 0x193e000 0x30 + 0x1a96000 0x1a96000 0x300 + 0x1a96400 0x1a96400 0x280 + 0x1a96b80 0x1a96b80 0x30 + 0x193e000 0x193e000 0x30>; + + clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>; + /* TODO + * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>, + * <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>; + */ + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", + "ext_pixel1_clk"; + + qcom,mmss-ulp-clamp-ctrl-offset = <0x20>; + qcom,mmss-phyreset-ctrl-offset = <0x24>; + + qcom,mdss-fb-map-prim = <&mdss_fb0>; + qcom,mdss-fb-map-sec = <&mdss_fb2>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0x1a94000 0x300>, + <0x1a94400 0x280>, + <0x1a94b80 0x30>, + <0x193e000 0x30>; + reg-names = "dsi_ctrl", "dsi_phy", + "dsi_phy_regulator", "mmss_misc_phys"; + + qcom,timing-db-mode; + qcom,mdss-mdp = <&mdss_mdp>; + vdd-supply = <&pm8937_l17>; + vddio-supply = <&pm8937_l6>; + + clocks = <&gcc_mdss GCC_MDSS_BYTE0_CLK>, + <&gcc_mdss GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>, + <&gcc_mdss BYTE0_CLK_SRC>, + <&gcc_mdss PCLK0_CLK_SRC>; + clock-names = "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg"; + + qcom,platform-strength-ctrl = [ff 06]; + qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; + qcom,platform-regulator-settings = [03 08 07 00 + 20 07 01]; + qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97 + 01 c0 00 00 05 00 00 01 97 + 01 c0 00 00 0a 00 00 01 97 + 01 c0 00 00 0f 00 00 01 97 + 00 40 00 00 00 00 00 01 ff]; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@1a96000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->1"; + cell-index = <1>; + reg = <0x1a96000 0x300>, + <0x1a96400 0x280>, + <0x1a94b80 0x30>, + <0x193e000 0x30>; + reg-names = "dsi_ctrl", "dsi_phy", + "dsi_phy_regulator", "mmss_misc_phys"; + + qcom,mdss-mdp = <&mdss_mdp>; + vdd-supply = <&pm8937_l17>; + vddio-supply = <&pm8937_l6>; + + clocks = <&gcc_mdss GCC_MDSS_BYTE1_CLK>, + <&gcc_mdss GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>, + <&gcc_mdss BYTE1_CLK_SRC>, + <&gcc_mdss PCLK1_CLK_SRC>; + clock-names = "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg"; + + qcom,platform-strength-ctrl = [ff 06]; + qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; + qcom,platform-regulator-settings = [03 08 07 00 + 20 07 01]; + qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97 + 01 c0 00 00 05 00 00 01 97 + 01 c0 00 00 0a 00 00 01 97 + 01 c0 00 00 0f 00 00 01 97 + 00 40 00 00 00 00 00 01 ff]; + + }; + + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <640 640>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb1>; + }; + + mdss_rotator: qcom,mdss_rotator { + compatible = "qcom,mdss_rotator"; + qcom,mdss-wb-count = <1>; + qcom,mdss-has-downscale; + qcom,mdss-has-ubwc; + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + rot-vdd-supply = <&gdsc_mdss>; + qcom,supply-names = "rot-vdd"; + qcom,mdss-has-reg-bus; + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc_mdss MDSS_ROTATOR_VOTE_CLK>; + clock-names = "iface_clk", "rot_core_clk"; + + qcom,mdss-rot-reg-bus { + /* Reg Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + }; +}; diff --git a/qcom/msm8937-pinctrl.dtsi b/qcom/msm8937-pinctrl.dtsi new file mode 100644 index 00000000..4e7db8e3 --- /dev/null +++ b/qcom/msm8937-pinctrl.dtsi @@ -0,0 +1,2026 @@ +&soc { + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8937-pinctrl"; + reg = <0x1000000 0x300000>; + reg-names = "pinctrl_regs"; + interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + wakeup-parent = <&wakegpio>; + #interrupt-cells = <2>; + irqdomain-map = <38 0 &wakegpio 3 0>, + <1 0 &wakegpio 4 0>, + <5 0 &wakegpio 5 0>, + <9 0 &wakegpio 6 0>, + <37 0 &wakegpio 8 0>, + <36 0 &wakegpio 9 0>, + <13 0 &wakegpio 10 0>, + <35 0 &wakegpio 11 0>, + <17 0 &wakegpio 12 0>, + <21 0 &wakegpio 13 0>, + <54 0 &wakegpio 14 0>, + <34 0 &wakegpio 15 0>, + <31 0 &wakegpio 16 0>, + <58 0 &wakegpio 17 0>, + <28 0 &wakegpio 18 0>, + <42 0 &wakegpio 19 0>, + <25 0 &wakegpio 20 0>, + <12 0 &wakegpio 21 0>, + <43 0 &wakegpio 22 0>, + <44 0 &wakegpio 23 0>, + <45 0 &wakegpio 24 0>, + <46 0 &wakegpio 25 0>, + <48 0 &wakegpio 26 0>, + <65 0 &wakegpio 27 0>, + <93 0 &wakegpio 28 0>, + <97 0 &wakegpio 29 0>, + <63 0 &wakegpio 30 0>, + <70 0 &wakegpio 31 0>, + <71 0 &wakegpio 32 0>, + <72 0 &wakegpio 33 0>, + <81 0 &wakegpio 34 0>, + <126 0 &wakegpio 35 0>, + <90 0 &wakegpio 36 0>, + <128 0 &wakegpio 37 0>, + <91 0 &wakegpio 38 0>, + <41 0 &wakegpio 39 0>, + <127 0 &wakegpio 40 0>, + <86 0 &wakegpio 41 0>, + <67 0 &wakegpio 50 0>, + <73 0 &wakegpio 51 0>, + <74 0 &wakegpio 52 0>, + <62 0 &wakegpio 53 0>, + <124 0 &wakegpio 54 0>, + <61 0 &wakegpio 55 0>, + <130 0 &wakegpio 56 0>, + <59 0 &wakegpio 57 0>, + <50 0 &wakegpio 59 0>; + irqdomain-map-pass-thru = <0 0xff>; + irqdomain-map-mask = <0xff 0>; + + pmx-uartconsole { + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart_console_sleep: uart_console_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + /* active state */ + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + /* suspended state */ + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + /* active state */ + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + /* suspended state */ + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + /* active state */ + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + /* suspended state */ + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + /* active state */ + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + /* suspended state */ + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 17 NFC Read Interrupt */ + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 17 NFC Read Interrupt */ + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_disable_active: nfc_disable_active { + /* active state */ + mux { + /* 16: NFC ENABLE 130: FW DNLD */ + /* 93: ESE Enable */ + pins = "gpio16", "gpio130", "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio130", "gpio93"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_disable_suspend: nfc_disable_suspend { + /* sleep state */ + mux { + /* 16: NFC ENABLE 130: FW DNLD */ + /* 93: ESE Enable */ + pins = "gpio16", "gpio130", "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio130", "gpio93"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + tlmm_pmi_flash_led { + rear_flash_led_enable: rear_flash_led_enable { + mux { + pins = "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + output-high; + }; + }; + + rear_flash_led_disable: rear_flash_led_disable { + mux { + pins = "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + output-low; + }; + }; + + front_flash_led_enable: front_flash_led_enable { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <16>; + output-high; + }; + }; + + front_flash_led_disable: front_flash_led_disable { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; + output-low; + }; + }; + }; + + spi3 { + spi3_default: spi3_default { + /* active state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <12>; /* 12 MA */ + bias-disable = <0>; /* No PULL */ + }; + }; + + spi3_sleep: spi3_sleep { + /* suspended state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + + spi3_cs0_active: cs0_active { + /* CS */ + mux { + pins = "gpio10"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + spi3_cs0_sleep: cs0_sleep { + /* CS */ + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + spi6 { + spi6_default: spi6_default { + /* active state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio20", "gpio21", "gpio23"; + drive-strength = <12>; /* 12 MA */ + bias-disable = <0>; /* No PULL */ + }; + }; + + spi6_sleep: spi6_sleep { + /* suspended state */ + mux { + /* MOSI, MISO, CLK */ + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio23"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + + spi6_cs0_active: cs0_active { + /* CS */ + mux { + pins = "gpio22"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + spi6_cs0_sleep: cs0_sleep { + /* CS */ + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + blsp2_uart2_active: blsp2_uart2_active { + mux { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "blsp_uart6"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_sleep: blsp2_uart2_sleep { + mux { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi7 { + spi7_default: spi7_default { + mux { + pins = "gpio85", "gpio86", "gpio88"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio85", "gpio86", "gpio88"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + spi7_sleep: spi7_sleep { + mux { + pins = "gpio85", "gpio86", "gpio88"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio85", "gpio86", "gpio88"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + spi7_cs0_active: cs0_active { + mux { + pins = "gpio87"; + function = "blsp_spi7_cs0"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio124"; + function = "fpc_reset_gpio_low"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio124"; + function = "fpc_reset_gpio_high"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio48"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + wcnss_pmux_5wire { + /* Active configuration of bus pins */ + wcnss_default: wcnss_default { + wcss_wlan2 { + pins = "gpio76"; + function = "wcss_wlan2"; + }; + + wcss_wlan1 { + pins = "gpio77"; + function = "wcss_wlan1"; + }; + + wcss_wlan0 { + pins = "gpio78"; + function = "wcss_wlan0"; + }; + + wcss_wlan { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <6>; /* 6 MA */ + bias-pull-up; /* PULL UP */ + }; + }; + + wcnss_sleep: wcnss_sleep { + wcss_wlan2 { + pins = "gpio76"; + function = "wcss_wlan2"; + }; + + wcss_wlan1 { + pins = "gpio77"; + function = "wcss_wlan1"; + }; + + wcss_wlan0 { + pins = "gpio78"; + function = "wcss_wlan0"; + }; + + wcss_wlan { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL Down */ + }; + }; + }; + + wcnss_pmux_gpio: wcnss_pmux_gpio { + wcnss_gpio_default: wcnss_gpio_default { + /* Active configuration of bus pins */ + mux { + /* Uses general purpose pins */ + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + function = "gpio"; + + }; + + config { + pins = "gpio76", "gpio77", + "gpio78", "gpio79", + "gpio80"; + drive-strength = <6>; /* 6 MA */ + bias-pull-up; /* PULL UP */ + }; + }; + }; + + pmx_quat_mi2s { + label = "quat_mi2s"; + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio94", "gpio95"; + function = "sec_mi2s"; + }; + + configs { + pins = "gpio94", "gpio95"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + }; + }; + + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio94", "gpio95"; + function = "sec_mi2s"; + }; + + configs { + pins = "gpio94", "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_quat_mi2s_din { + label = "quat_mi2s_din"; + quat_mi2s_din_active: quat_mi2s_din_active { + mux { + pins = "gpio12", "gpio13"; + function = "sec_mi2s"; + }; + + configs { + pins = "gpio12", "gpio13"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* No PULL */ + output-high; + }; + }; + + quat_mi2s_din_sleep: quat_mi2s_din_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "sec_mi2s"; + }; + + configs { + pins = "gpio12", "gpio13"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + cdc_mclk2_pin { + cdc_mclk2_sleep: cdc_mclk2_sleep { + mux { + pins = "gpio66"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + cdc_mclk2_active: cdc_mclk2_active { + mux { + pins = "gpio66"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + pmx_adv7533_int: pmx_adv7533_int { + adv7533_int_active: adv7533_int_active { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_int_suspend: adv7533_int_suspend { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <16>; + bias-disable; + }; + }; + + }; + + pmx_mdss: pmx_mdss { + mdss_dsi_active: mdss_dsi_active { + mux { + pins = "gpio60", "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio98", "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + + mdss_dsi_suspend: mdss_dsi_suspend { + mux { + pins = "gpio60", "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio98", "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + pmx_mdss_te { + mdss_te_active: mdss_te_active { + mux { + pins = "gpio24"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* pull down*/ + }; + }; + + mdss_te_suspend: mdss_te_suspend { + mux { + pins = "gpio24"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + usbc_int_default: usbc_int_default { + mux { + pins = "gpio97", "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio131"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tlmm_gpio_key { + gpio_key_active: gpio_key_active { + mux { + pins = "gpio91", "gpio127", "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio127", "gpio128"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_key_suspend: gpio_key_suspend { + mux { + pins = "gpio91", "gpio127", "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio127", "gpio128"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* add pingrp for touchscreen */ + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio65", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio65", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_qdsd_clk { + qdsd_clk_sdcard: clk_sdcard { + config { + pins = "qdsd_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + qdsd_clk_trace: clk_trace { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_clk_swdtrc: clk_swdtrc { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_clk_spmi: clk_spmi { + config { + pins = "qdsd_clk"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_cmd { + qdsd_cmd_sdcard: cmd_sdcard { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_cmd_trace: cmd_trace { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_swduart: cmd_uart { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_swdtrc: cmd_swdtrc { + config { + pins = "qdsd_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_cmd_jtag: cmd_jtag { + config { + pins = "qdsd_cmd"; + bias-disable; /* NO pull */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_cmd_spmi: cmd_spmi { + config { + pins = "qdsd_cmd"; + bias-pull-down; /* pull down */ + drive-strength = <10>; /* 10 MA */ + }; + }; + }; + + pmx_qdsd_data0 { + qdsd_data0_sdcard: data0_sdcard { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data0_trace: data0_trace { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data0_swduart: data0_uart { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_swdtrc: data0_swdtrc { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_jtag: data0_jtag { + config { + pins = "qdsd_data0"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data0_spmi: data0_spmi { + config { + pins = "qdsd_data0"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data1 { + qdsd_data1_sdcard: data1_sdcard { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data1_trace: data1_trace { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data1_swduart: data1_uart { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data1_swdtrc: data1_swdtrc { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data1_jtag: data1_jtag { + config { + pins = "qdsd_data1"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_qdsd_data2 { + qdsd_data2_sdcard: data2_sdcard { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data2_trace: data2_trace { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data2_swduart: data2_uart { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data2_swdtrc: data2_swdtrc { + config { + pins = "qdsd_data2"; + bias-pull-down; /* pull down */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data2_jtag: data2_jtag { + config { + pins = "qdsd_data2"; + bias-pull-up; /* pull up */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_qdsd_data3 { + qdsd_data3_sdcard: data3_sdcard { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data3_trace: data3_trace { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + qdsd_data3_swduart: data3_uart { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_swdtrc: data3_swdtrc { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_jtag: data3_jtag { + config { + pins = "qdsd_data3"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + qdsd_data3_spmi: data3_spmi { + config { + pins = "qdsd_data3"; + bias-pull-down; /* pull down */ + drive-strength = <8>; /* 8 MA */ + }; + }; + }; + + pmx_sdc1_rclk { + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + + cdc-pdm-2-lines { + cdc_pdm_lines_2_act: pdm_lines_2_on { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio70", "gpio71", "gpio72"; + drive-strength = <8>; + }; + }; + + cdc_pdm_lines_2_sus: pdm_lines_2_off { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio70", "gpio71", "gpio72"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cdc-pdm-lines { + cdc_pdm_lines_act: pdm_lines_on { + mux { + pins = "gpio69", "gpio73", "gpio74"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio69", "gpio73", "gpio74"; + drive-strength = <8>; + }; + }; + + cdc_pdm_lines_sus: pdm_lines_off { + mux { + pins = "gpio69", "gpio73", "gpio74"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio69", "gpio73", "gpio74"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cross-conn-det { + cross_conn_det_act: lines_on { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <8>; + output-low; + bias-pull-down; + }; + }; + + cross_conn_det_sus: lines_off { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* WSA VI sense */ + wsa-vi { + wsa_vi_on: wsa_vi_on { + mux { + pins = "gpio94", "gpio95"; + function = "wsa_io"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* NO pull */ + }; + }; + + wsa_vi_off: wsa_vi_off { + mux { + pins = "gpio94", "gpio95"; + function = "wsa_io"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + }; + + /* WSA Reset */ + wsa_reset { + wsa_reset_on: wsa_reset_on { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + wsa_reset_off: wsa_reset_off { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + }; + + /* WSA CLK */ + wsa_clk { + wsa_clk_on: wsa_clk_on { + mux { + pins = "gpio25"; + function = "pri_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <8>; /* 8 MA */ + output-high; + }; + }; + + wsa_clk_off: wsa_clk_off { + mux { + pins = "gpio25"; + function = "pri_mi2s_mclk_a"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; /* 2 MA */ + output-low; + bias-pull-down; + }; + }; + }; + + pri-tlmm-lines { + pri_tlmm_lines_act: pri_tlmm_lines_act { + mux { + pins = "gpio85", "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85", "gpio88"; + drive-strength = <8>; + }; + }; + + pri_tlmm_lines_sus: pri_tlmm_lines_sus { + mux { + pins = "gpio85", "gpio88"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio85", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pri-tlmm-ws-lines { + pri_tlmm_ws_act: pri_tlmm_ws_act { + mux { + pins = "gpio87"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio87"; + drive-strength = <8>; + }; + }; + + pri_tlmm_ws_sus: pri_tlmm_ws_sus { + mux { + pins = "gpio87"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_sdc1_clk { + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc1_cmd { + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc1_data { + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + sdhc2_cd_pin { + sdc2_cd_on: cd_on { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_sdc2_clk { + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + drive-strength = <16>; /* 16 MA */ + bias-disable; /* NO pull */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_cmd { + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc2_data { + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + cci { + cci0_active: cci0_active { + /* cci0 active state */ + mux { + /* CLK, DATA */ + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + }; + + config { + pins = "gpio29", "gpio30"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci0_suspend: cci0_suspend { + /* cci0 suspended state */ + mux { + /* CLK, DATA */ + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + }; + + config { + pins = "gpio29", "gpio30"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci1_active: cci1_active { + /* cci1 active state */ + mux { + /* CLK, DATA */ + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31", "gpio32"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + + cci1_suspend: cci1_suspend { + /* cci1 suspended state */ + mux { + /* CLK, DATA */ + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31", "gpio32"; + drive-strength = <2>; /* 2 MA */ + bias-disable; /* No PULL */ + }; + }; + }; + + cdc-dmic-lines { + cdc_dmic0_clk_act: dmic0_clk_on { + mux { + pins = "gpio89"; + function = "dmic0_clk"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; + bias-pull-none; + }; + }; + + cdc_dmic0_clk_sus: dmic0_clk_off { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_dmic0_data_act: dmic0_data_on { + mux { + pins = "gpio90"; + function = "dmic0_data"; + }; + + config { + pins = "gpio90"; + drive-strength = <8>; + bias-pull-none; + }; + }; + + cdc_dmic0_data_sus: dmic0_data_off { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + /*sensors */ + cam_sensor_mclk0_default: cam_sensor_mclk0_default { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio26"; + function = "cam_mclk"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_sleep: cam_sensor_mclk0_sleep { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio26"; + function = "cam_mclk"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_reset: cam_sensor_rear_reset { + /* RESET */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_reset_sleep: cam_sensor_rear_reset_sleep { + /* RESET */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_standby: cam_sensor_rear_standby { + /* STANDBY */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_standby_sleep: cam_sensor_rear_standby_sleep { + /* STANDBY */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_vdig: cam_sensor_rear_vdig { + /* VDIG */ + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_vdig_sleep: cam_sensor_rear_vdig_sleep { + /* VDIG */ + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_vana: cam_sensor_rear_vana { + /* VANA */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_vana_sleep: cam_sensor_rear_vana_sleep { + /* VANA */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_default: cam_sensor_mclk1_default { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_sleep: cam_sensor_mclk1_sleep { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_default: cam_sensor_front_default { + /* RESET, STANDBY */ + mux { + pins = "gpio38","gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio38","gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_sleep: cam_sensor_front_sleep { + /* RESET, STANDBY */ + mux { + pins = "gpio38","gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio38","gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_default: cam_sensor_mclk2_default { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_sleep: cam_sensor_mclk2_sleep { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front1_default: cam_sensor_front1_default { + /* RESET, STANDBY */ + mux { + pins = "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front1_sleep: cam_sensor_front1_sleep { + /* RESET, STANDBY */ + mux { + pins = "gpio40", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio39"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; +}; diff --git a/qcom/msm8937-pm.dtsi b/qcom/msm8937-pm.dtsi new file mode 100644 index 00000000..69fe3b9d --- /dev/null +++ b/qcom/msm8937-pm.dtsi @@ -0,0 +1,256 @@ +#include <dt-bindings/msm/pm.h> + +&soc { + qcom,spm@b1d2000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb1d2000 0x1000>; + qcom,name = "system-cci"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0xe>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3 + &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "system-active"; + qcom,psci-mode = <0>; + /* TBD */ + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <415>; + qcom,min-residency-us = <980>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "system-wfi"; + qcom,psci-mode = <1>; + /* TBD */ + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <475>; + qcom,min-residency-us = <1050>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2 { + reg = <2>; + label = "system-ret"; + qcom,psci-mode = <2>; + /* TBD */ + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <900>; + qcom,min-residency-us = <1250>; + qcom,min-child-idx = <1>; + qcom,reset-level = <LPM_RESET_LVL_RET>; + }; + + qcom,pm-cluster-level@3 { + reg = <3>; + label = "system-pc"; + qcom,psci-mode = <3>; + /* TBD */ + qcom,entry-latency-us = <800>; + qcom,exit-latency-us = <10782>; + qcom,min-residency-us = <1426>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,is-reset; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <1>; + /* TBD */ + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <210>; + qcom,min-residency-us = <326>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "perf-l2-gdhs"; + qcom,psci-mode = <4>; + /* TBD */ + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <267>; + qcom,min-residency-us = <627>; + qcom,min-child-idx = <1>; + qcom,reset-level = <LPM_RESET_LVL_GDHS>; + }; + + qcom,pm-cluster-level@2 { + reg = <2>; + label = "perf-l2-pc"; + qcom,psci-mode = <5>; + /* TBD */ + qcom,entry-latency-us = <800>; + qcom,exit-latency-us = <305>; + qcom,min-residency-us = <879>; + qcom,min-child-idx = <1>; + qcom,is-reset; + qcom,reset-level = <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { + reg = <0>; + qcom,psci-cpu-mode = <0>; + label = "wfi"; + /* TBD */ + qcom,entry-latency-us = <49>; + qcom,exit-latency-us = <1>; + qcom,min-residency-us = <67>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + qcom,psci-cpu-mode = <3>; + label = "pc"; + /* TBD */ + qcom,entry-latency-us = <290>; + qcom,exit-latency-us = <190>; + qcom,min-residency-us = <326>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = + <LPM_RESET_LVL_PC>; + }; + }; + }; + + qcom,pm-cluster@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <1>; + /* TBD */ + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <221>; + qcom,min-residency-us = <400>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "pwr-l2-gdhs"; + qcom,psci-mode = <4>; + /* TBD */ + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <337>; + qcom,min-residency-us = <717>; + qcom,min-child-idx = <1>; + qcom,reset-level = + <LPM_RESET_LVL_GDHS>; + }; + + qcom,pm-cluster-level@2 { + reg = <2>; + label = "pwr-l2-pc"; + qcom,psci-mode = <5>; + /* TBD */ + qcom,entry-latency-us = <800>; + qcom,exit-latency-us = <415>; + qcom,min-residency-us = <980>; + qcom,min-child-idx = <1>; + qcom,is-reset; + qcom,reset-level = + <LPM_RESET_LVL_PC>; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { + reg = <0>; + qcom,psci-cpu-mode = <0>; + label = "wfi"; + /* TBD */ + qcom,entry-latency-us = <49>; + qcom,exit-latency-us = <1>; + qcom,min-residency-us = <57>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + qcom,psci-cpu-mode = <3>; + label = "pc"; + /* TBD */ + qcom,entry-latency-us = <290>; + qcom,exit-latency-us = <221>; + qcom,min-residency-us = <400>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = + <LPM_RESET_LVL_PC>; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-master-stats@60150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x60150 0x5000>; + qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/qcom/msm8937-regulator.dtsi b/qcom/msm8937-regulator.dtsi new file mode 100644 index 00000000..c4ab6a51 --- /dev/null +++ b/qcom/msm8937-regulator.dtsi @@ -0,0 +1,444 @@ +&rpm_bus { + rpm-regulator-smpa1 { + status = "okay"; + pm8937_s1: regulator-s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + /* VDD_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + pm8937_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8937_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8937_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8937_cx_cdev: regulator-cx-cdev { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pm8937_s2_floor_level>; + regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_RETENTION>; + #cooling-cells = <2>; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8937_s3: regulator-s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1300000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8937_s4: regulator-s4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,init-voltage = <2050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8937_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + /* VDD_MX supply */ + rpm-regulator-ldoa3 { + status = "okay"; + pm8937_l3_level_ao: regulator-l3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + qcom,always-send-voltage; + }; + + pm8937_l3_level_so: regulator-l3-level-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l3_level_so"; + qcom,set = <2>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,init-voltage-level = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8937_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8937_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8937_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8937_l7_ao: regulator-l7-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l7_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8937_l8: regulator-l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8937_l9: regulator-l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8937_l10: regulator-l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8937_l11: regulator-l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8937_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8937_l13: regulator-l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8937_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8937_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8937_l16: regulator-l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8937_l17: regulator-l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8937_l19: regulator-l19 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1225000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8937_l22: regulator-l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8937_l23: regulator-l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; +}; + +/* SPM controlled regulators */ +&spmi_bus { + qcom,pm8937@1 { + /* PM8937 S5 + S6 = VDD_APC supply */ + pm8937_s5: spm-regulator@2000 { + compatible = "qcom,spm-regulator"; + reg = <0x2000 0x100>; + regulator-name = "pm8937_s5"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + }; + }; +}; + +&soc { + mem_acc_vreg_corner: regulator@01946004 { + compatible = "qcom,mem-acc-regulator"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-reg-addr-list = + <0x01942138 0x01942130 0x01942120 + 0x01942124 0x01946000 0x01946004>; + + qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>, <6 0x55>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + < 3 0x0>, < 4 0x0>, < 5 0x0>; + + qcom,corner2-reg-config = + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>, < 5 0x0>; + + qcom,corner3-reg-config = + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; + qcom,cpr-voltage-floor = <1050000 1050000 1090000>; + vdd-apc-supply = <&pm8937_s5>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <10>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <4>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,cpr-fuse-row = <67 0>; + qcom,cpr-fuse-target-quot = <42 24 6>; + qcom,cpr-fuse-ro-sel = <60 57 54>; + qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>; + qcom,cpr-fuse-init-voltage = + <67 36 6 0>, + <67 18 6 0>, + <67 0 6 0>; + qcom,cpr-fuse-quot-offset = + <71 26 6 0>, + <71 20 6 0>, + <70 54 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 960000000>, + <2 1094400000>, + <3 1209600000>, + <4 1248000000>, + <5 1344000000>, + <6 1401000000>, + <7 1497600000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 0 1 2 6>, + <1 0 1 2 7>, + <2 0 1 2 3>; + qcom,cpr-fuse-revision = <69 39 3 0>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-fuse-version-map = + <0 (-1) 1 (-1) (-1) (-1)>, + <(-1) (-1) 2 (-1) (-1) (-1)>, + <(-1) (-1) 3 (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1)>; + qcom,cpr-quotient-adjustment = + <(-20) (-40) (-20)>, + <0 (-40) (20)>, + <0 0 (20)>, + <0 0 0>; + qcom,cpr-init-voltage-adjustment = + <0 0 0>, + <(10000) (15000) (20000)>, + <0 0 0>, + <0 0 0>; + qcom,cpr-enable; + }; + + eldo2_pm8937: eldo2 { + compatible = "regulator-fixed"; + regulator-name = "eldo2_pm8937"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pm8937_gpios 7 0>; + regulator-always-on; + }; + + adv_vreg: adv_vreg { + compatible = "regulator-fixed"; + regulator-name = "adv_vreg"; + startup-delay-us = <400>; + enable-active-high; + gpio = <&pm8937_gpios 8 0>; + }; + +}; diff --git a/qcom/msm8937-thermal.dtsi b/qcom/msm8937-thermal.dtsi new file mode 100644 index 00000000..b1b40561 --- /dev/null +++ b/qcom/msm8937-thermal.dtsi @@ -0,0 +1,809 @@ +#include <dt-bindings/thermal/thermal.h> + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + lpass-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + apc1-cpu3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-step { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gpu_step_trip: gpu-step-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev0 { + trip = <&gpu_step_trip>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + hexa-cpu-max-step { + polling-delay-passive = <50>; + polling-delay = <100>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu_trip:cpu-trip { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu1_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu2_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu3_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu4_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu5_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu6_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + cpu7_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + }; + }; + + apc1-cpu0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + apc1_cpu0_trip: apc1-cpu0-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&apc1_cpu0_trip>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + apc1_cpu1_trip: apc1-cpu1-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&apc1_cpu1_trip>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + apc1_cpu2_trip: apc1-cpu2-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu2_cdev { + trip = <&apc1_cpu2_trip>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + apc1-cpu3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + apc1_cpu3_trip: apc1-cpu3-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu3_cdev { + trip = <&apc1_cpu3_trip>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpuss0_step_trip: cpuss0-step-trip { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu4_cdev { + trip = <&cpuss0_step_trip>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu5_cdev { + trip = <&cpuss0_step_trip>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu6_cdev { + trip = <&cpuss0_step_trip>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu7_cdev { + trip = <&cpuss0_step_trip>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + trips { + aoss0_trip: aoss-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + tracks-low; + trips { + mdm_core_trip: mdm-core-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + lpass-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + tracks-low; + trips { + qdsp_trip: qdsp-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&qdsp_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&qdsp_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&qdsp_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + cpuss1-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + tracks-low; + trips { + cpuss1_trip: cpuss1-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpuss1_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpuss1_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpuss1_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + apc1-cpu0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 5>; + wake-capable-sensor; + tracks-low; + trips { + cpu0_trip: apc1-cpu0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + apc1-cpu1-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + tracks-low; + trips { + cpu1_trip: apc1-cpu1-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpu1_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpu1_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpu1_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + apc1-cpu2-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + tracks-low; + trips { + cpu2_trip: apc1-cpu2-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpu2_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpu2_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpu2_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + apc1-cpu3-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + tracks-low; + trips { + cpu3_trip: apc1-cpu3-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpu3_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpu3_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpu3_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + cpuss0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + tracks-low; + trips { + cpuss0_lowf_trip: cpuss0-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&cpuss0_lowf_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&cpuss0_lowf_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&cpuss0_lowf_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + gpu-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + tracks-low; + trips { + gpu_lowf_trip: gpu-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + + cx_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&pm8937_cx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; +}; diff --git a/qcom/msm8937-vidc.dtsi b/qcom/msm8937-vidc.dtsi new file mode 100644 index 00000000..5cb28189 --- /dev/null +++ b/qcom/msm8937-vidc.dtsi @@ -0,0 +1,159 @@ +&soc { + qcom,vidc@1d00000 { + compatible = "qcom,msm-vidc"; + reg = <0x01d00000 0xff000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + qcom,hfi-version = "3xx"; + venus-supply = <&gdsc_venus>; + venus-core0-supply = <&gdsc_venus_core0>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core_clk", "core0_clk", "iface_clk", "bus_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x0>; + qcom,sw-power-collapse; + qcom,slave-side-cp; + qcom,dcvs-tbl = + <108000 108000 244800 0x00000004>, /* Encoder */ + <108000 108000 244800 0x0f00000c>; /* Decoder */ + qcom,dcvs-limit = + <8160 30>, /* Encoder */ + <8160 30>; /* Decoder */ + qcom,hfi = "venus"; + qcom,reg-presets = <0xe0020 0x05555556>, + <0xe0024 0x05555556>, + <0x80124 0x00000003>; + qcom,qdss-presets = <0x826000 0x1000>, + <0x827000 0x1000>, + <0x822000 0x1000>, + <0x803000 0x1000>, + <0x9180000 0x1000>, + <0x9181000 0x1000>; + qcom,max-hw-load = <352800>; /* 1080p@30 + 720p@30 */ + qcom,firmware-name = "venus"; + qcom,allowed-clock-rates = <360000000 320000000 + 308570000 240000000 166150000>; + qcom,clock-freq-tbl { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,cycles-per-mb = <2316>; + qcom,low-power-mode-factor = <32768>; + }; + + qcom,profile-dec { + qcom,codec-mask = <0xf3ffffff>; + qcom,cycles-per-mb = <788>; + }; + + qcom,profile-hevcdec { + qcom,codec-mask = <0x0c000000>; + qcom,cycles-per-mb = <1015>; + }; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_iommu 0x800 0x00>, + <&apps_iommu 0x807 0x00>, + <&apps_iommu 0x808 0x27>, + <&apps_iommu 0x811 0x20>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_iommu 0x900 0x00>, + <&apps_iommu 0x90a 0x04>, + <&apps_iommu 0x909 0x22>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x12c00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_iommu 0x90c 0x20>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_iommu 0x940 0x00>, + <&apps_iommu 0x907 0x08>, + <&apps_iommu 0x908 0x20>, + <&apps_iommu 0x90d 0x20>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + /* Buses */ + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>; + qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>; + qcom,bus-governor = "venus-ddr-gov"; + qcom,bus-range-kbps = <1000 917000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>; + qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + }; + + venus-ddr-gov { + compatible = "qcom,msm-vidc,governor,table"; + name = "venus-ddr-gov"; + status = "ok"; + qcom,bus-freq-table { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,load-busfreq-tbl = + <244800 841000>, /* 1080p30E */ + <216000 740000>, /* 720p60E */ + <194400 680000>, /* FWVGA120E */ + <144000 496000>, /* VGA120E */ + <108000 370000>, /* 720p30E */ + <97200 340000>, /* FWVGA60E */ + <48600 170000>, /* FWVGA30E */ + <72000 248000>, /* VGA60E */ + <36000 124000>, /* VGA30E */ + <18000 70000>, /* QVGA60E */ + <9000 35000>, /* QVGA30E */ + <0 0>; + }; + + qcom,profile-dec { + qcom,codec-mask = <0xffffffff>; + qcom,load-busfreq-tbl = + <244800 605000>, /* 1080p30D */ + <216000 540000>, /* 720p60D */ + <194400 484000>, /* FWVGA120D */ + <144000 360000>, /* VGA120D */ + <108000 270000>, /* 720p30D */ + <97200 242000>, /* FWVGA60D */ + <48600 121000>, /* FWVGA30D */ + <72000 180000>, /* VGA60D */ + <36000 90000>, /* VGA30D */ + <18000 45000>, /* HVGA30D */ + <0 0>; + }; + }; + }; +}; diff --git a/qcom/msm8937.dtsi b/qcom/msm8937.dtsi new file mode 100644 index 00000000..5bdb157d --- /dev/null +++ b/qcom/msm8937.dtsi @@ -0,0 +1,2226 @@ +#include "skeleton64.dtsi" +#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/clock/mdss-28nm-pll-clk.h> + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} + +/ { + model = "Qualcomm Technologies, Inc. MSM8937"; + compatible = "qcom,msm8937"; + qcom,msm-id = <294 0x0>; + interrupt-parent = <&wakegic>; + + chosen { + bootargs = "sched_enable_hmp=1 kpti=0"; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + other_ext_mem: other_ext_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85b00000 0x0 0xd00000>; + }; + + modem_mem: modem_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86800000 0x0 0x5000000>; + }; + + adsp_fw_mem: adsp_fw_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8b800000 0x0 0x1100000>; + }; + + wcnss_fw_mem: wcnss_fw_region@0 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8c900000 0x0 0x700000>; + }; + + + venus_mem: venus_region@0 { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; + alignment = <0 0x400000>; + size = <0 0x0800000>; + }; + + secure_mem: secure_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x7000000>; + }; + + qseecom_mem: qseecom_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + adsp_mem: adsp_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + cont_splash_mem: splash_region@83000000 { + reg = <0x0 0x90000000 0x0 0x1400000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x19d000>; + }; + }; + + aliases { + /* smdtty devices */ + smd1 = &smdtty_apps_fm; + smd2 = &smdtty_apps_riva_bt_acl; + smd3 = &smdtty_apps_riva_bt_cmd; + smd4 = &smdtty_mbalbridge; + smd5 = &smdtty_apps_riva_ant_cmd; + smd6 = &smdtty_apps_riva_ant_data; + smd7 = &smdtty_data1; + smd8 = &smdtty_data4; + smd11 = &smdtty_data11; + smd21 = &smdtty_data21; + smd36 = &smdtty_loopback; + i2c2 = &i2c_2; + i2c5 = &i2c_5; + spi3 = &spi_3; + spi6 = &spi_6; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 for SD card */ + }; + + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + soc: soc { }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + +}; + +#include "msm8937-pinctrl.dtsi" +#include "msm8937-cpu.dtsi" +#include "msm8937-ion.dtsi" +#include "msm-arm-smmu-8937.dtsi" +#include "msm8937-bus.dtsi" +#include "msm8937-vidc.dtsi" +#include "msm8937-pm.dtsi" +#include "msm8937-gpu.dtsi" +#include "msm8937-mdss.dtsi" +#include "msm8937-mdss-pll.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + dcc: dcc@b3000 { + compatible = "qcom,dcc"; + reg = <0xb3000 0x1000>, + <0xb4000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&gcc GCC_DCC_CLK>; + clock-names = "apb_pclk"; + qcom,save-reg; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; + reg = <0x601d0 0x1000>, + <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <64>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 2 0xff08>, + <1 3 0xff08>, + <1 4 0xff08>, + <1 1 0xff08>; + clock-frequency = <19200000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,rmtfs_sharedmem@00000000 { + compatible = "qcom,sharedmem-uio"; + reg = <0x00000000 0x00180000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4a3000 0x1000>; + clock-frequency = <32768>; + }; + + cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0xff00>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + thermal_zones: thermal-zones {}; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpm_sw_dump { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + vsense_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe9>; + }; + + tmc_etf_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + tmc_etr_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + tmc_etf_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + c_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0xeb>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c200_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c300_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c400_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x134>; + }; + + c500_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x135>; + }; + + c600_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x136>; + }; + + c700_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x137>; + }; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c101_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c102_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c103_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x63>; + }; + + l1_icache100 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x64>; + }; + + l1_icache101 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x65>; + }; + + l1_icache102 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x66>; + }; + + l1_icache103 { + qcom,dump-size = <0x8800>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache101 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache102 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache103 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x87>; + }; + + }; + + tsens0: tsens@4a8000 { + compatible = "qcom,msm8937-tsens"; + reg = <0x4a8000 0x1000>, + <0x4a9000 0x1000>, + <0xa4000 0x1000>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical", "tsens_eeprom_physical"; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tsens-upper-lower"; + #thermal-sensor-cells = <1>; + }; + + slim_msm: slim@c140000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xc140000 0x2c000>, + <0xc104000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x600000>; + qcom,ea-pc = <0x230>; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x1f000>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <10>; + }; + + dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7ac4000 0x1f000>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <10>; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-msm8937"; + #clock-cells = <1>; + }; + + gcc: qcom,gcc@1800000 { + compatible = "qcom,gcc-msm8937", "syscon"; + reg = <0x1800000 0x80000>; + <0x00a6018 0x00004>; + reg-names = "cc_base", "gpu-bin"; + qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>; + vdd_cx-supply = <&pm8937_s2_level>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,msm8937-debugcc"; + reg = <0x1874000 0x4>, + <0xb11101c 0x8>; + reg-names = "cc_base", "meas"; + qcom,gcc = <&gcc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + gcc_mdss: qcom,gcc-mdss@1800000 { + compatible = "qcom,gcc-mdss-msm8937"; + reg = <0x1800000 0x80000>; + clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; + clock-names = "pclk0_src", "byte0_src", "pclk1_src", + "byte1_src"; + #clock-cells = <1>; + }; + + clock_cpu: qcom,cpu-clock-8939@b111050 { + compatible = "qcom,cpu-clock-8939"; + reg = <0xb011050 0x8>, + <0xb111050 0x8>, + <0xb1d1050 0x8>, + <0x00a412c 0x8>; + reg-names = "apcs-c1-rcg-base", "apcs-c0-rcg-base", + "apcs-cci-rcg-base", "efuse"; + vdd-c0-supply = <&apc_vreg_corner>; + vdd-c1-supply = <&apc_vreg_corner>; + vdd-cci-supply = <&apc_vreg_corner>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0_AO_OUT_MAIN>; + clock-names = "xo_ao", "gpll0_ao" ; + qcom,speed0-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 902400000 2>, + < 998400000 4>, + < 1094400000 6>; + + qcom,speed0-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1248000000 4>, + < 1344000000 5>, + < 1401000000 6>; + + qcom,speed0-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed1-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 902400000 2>, + < 998400000 4>, + < 1094400000 6>, + < 1209600000 7>; + + qcom,speed1-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1248000000 4>, + < 1344000000 5>, + < 1401000000 6>, + < 1497600000 7>; + + qcom,speed1-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed2-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 902400000 2>, + < 998400000 3>; + + qcom,speed2-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1094400000 2>, + < 1209600000 3>; + + qcom,speed2-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + #clock-cells = <1>; + }; + + i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 6 64 0x20000020 0x20>, + <&dma_blsp1 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x78b8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <86>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0x7af5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,master-id = <84>; + dmas = <&dma_blsp2 4 64 0x20000020 0x20>, + <&dma_blsp2 5 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi_3: spi@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b7000 0x600>, + <0x7884000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi3_default &spi3_cs0_active>; + pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + status = "disabled"; + }; + + spi_6: spi@7af6000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x7af6000 0x600>, + <0x7ac4000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, + <0 239 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <19200000>; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi6_default &spi6_cs0_active>; + pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <84>; + status = "disabled"; + }; + + blsp2_uart2: uart@7af0000 { /* BLSP2 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x7af0000 0x200>, + <0x7ac4000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 307 0 + 1 &intc 0 239 0 + 2 &tlmm 21 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart2_sleep>; + pinctrl-1 = <&blsp2_uart2_active>; + qcom,msm-bus,name = "blsp2_uart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + status = "disabled"; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", + "cpu3_clk", "cpu4_clk", "cpu5_clk", + "cpu6_clk", "cpu7_clk"; + /* TODO + *clocks = <&clock_cpu clk_cci_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_lc_clk>, + * <&clock_cpu clk_a53_lc_clk>, + * <&clock_cpu clk_a53_lc_clk>, + * <&clock_cpu clk_a53_lc_clki>; + */ + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 960000 >, + < 1094400 >, + < 1209600 >, + < 1248000 >, + < 1344000 >, + < 1401000 >, + < 1497600 >; + + qcom,cpufreq-table-4 = + < 768000 >, + < 902400 >, + < 998400 >, + < 1094400 >, + < 1209600 >; + }; + + cci_cache: qcom,cci { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + /* TODO + * clocks = <&clock_cpu clk_cci_clk/>; + */ + governor = "cpufreq"; + freq-tbl-khz = + < 400000 >, + < 533333 >; + }; + + ddr_bw_opp_table: generic-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 100, 8); /* 769 MB/s */ + BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ + BW_OPP_ENTRY( 278, 8); /* 2124 MB/s */ + BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */ + BW_OPP_ENTRY( 537, 8); /* 4101 MB/s */ + BW_OPP_ENTRY( 556, 8); /* 4248 MB/s */ + BW_OPP_ENTRY( 662, 8); /* 5053 MB/s */ + BW_OPP_ENTRY( 748, 8); /* 5712 MB/s */ + BW_OPP_ENTRY( 806, 8); /* 6152 MB/s */ + BW_OPP_ENTRY( 921, 8); /* 7031 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@408000 { + compatible = "qcom,bimc-bwmon2"; + reg = <0x408000 0x300>, <0x401000 0x200>; + reg-names = "base", "global_base"; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + qcom,mport = <0>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + }; + + cpu_cpu_ddr_latfloor: qcom,cpu-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS(384, 8) >, + < 1497600 MHZ_TO_MBPS(557, 8) >; + }; + }; + + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 998400 MHZ_TO_MBPS(384, 8) >, + < 1209600 MHZ_TO_MBPS(557, 8) >; + }; + }; + + blsp2_uart1: uart@7aef000 { + compatible = "qcom,msm-hsuart-v14"; + reg = <0x7aef000 0x200>, + <0x7ac4000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 306 0 + 1 &intc 0 239 0 + 2 &tlmm 17 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + qcom,msm-bus,name = "blsp2_uart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + status = "disabled"; + }; + + qcom,ipc-spinlock@1905000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1905000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + usb_otg: usb@78db000 { + compatible = "qcom,hsusb-otg"; + reg = <0x78db000 0x400>, <0x6c000 0x200>; + reg-names = "core", "phy_csr"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 134 IRQ_TYPE_LEVEL_HIGH>, + <0 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core_irq", "async_irq"; + + hsusb_vdd_dig-supply = <&pm8937_l2>; + HSUSB_1p8-supply = <&pm8937_l7>; + HSUSB_3p3-supply = <&pm8937_l13>; + qcom,vdd-voltage-level = <0 1200000 1200000>; + vbus_otg-supply = <&smbcharger_charger_otg>; + + qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ + qcom,hsusb-otg-mode = <3>; /* OTG mode */ + qcom,hsusb-otg-otg-control = <2>; /* PMIC */ + qcom,dp-manual-pullup; + qcom,phy-dvdd-always-on; + qcom,boost-sysclk-with-streaming; + qcom,axi-prefetch-enable; + qcom,hsusb-otg-delay-lpm; + + qcom,msm-bus,name = "usb2"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 80000 0>, + <87 512 6000 6000>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>, + <&rpmcc BIMC_USB_A_CLK>, + <&rpmcc SNOC_USB_A_CLK>, + <&rpmcc PNOC_USB_A_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&rpmcc CXO_SMD_OTG_CLK>; + clock-names = "iface_clk", "core_clk", "sleep_clk", + "bimc_clk", "snoc_clk", "pcnoc_clk", + "phy_csr_clk", "xo"; + qcom,bus-clk-rate = <748800000 200000000 100000000>; + qcom,max-nominal-sysclk-rate = <133330000>; + + resets = <&gcc GCC_USB_HS_BCR>, + <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "core_reset", "phy_reset", "phy_por_reset"; + + qcom,usbbam@78c4000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x78c4000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 135 IRQ_TYPE_LEVEL_HIGH>; + + qcom,bam-type = <1>; + qcom,usb-bam-num-pipes = <4>; + qcom,usb-bam-fifo-baseaddr = <0x08605000>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,reset-bam-on-disconnect; + + qcom,pipe0 { + label = "hsusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6044000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0xe00>; + qcom,descriptor-fifo-offset = <0xe00>; + qcom,descriptor-fifo-size = <0x200>; + }; + }; + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + status = "okay"; + }; + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + qcom,threshold-arr = <0xb088094 0xb098094 0xb0a8094 + 0xb0b8094 0xb188094 0xb198094 0xb1a8094 0xb1a8094>; + qcom,config-arr = <0xb08809c 0xb09809c 0xb0a809c + 0xb0b809c 0xb18809c 0xb19809c 0xb1a809c 0xb1b809c>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */ + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-boot-time; + label = "modem"; + }; + }; + + jtag_mm0: jtagmm@61bc000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bc000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm1: jtagmm@61bd000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bd000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm2: jtagmm@61be000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61be000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm3: jtagmm@61bf000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x61bf000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm4: jtagmm@619c000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x619c000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm5: jtagmm@619d000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x619d000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm6: jtagmm@619e000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x619e000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + jtag_mm7: jtagmm@619f000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x619f000 0x1000>; + reg-names = "etm-base"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + }; + + apcs: syscon@0b011008 { + compatible = "syscon"; + reg = <0x0b011008 0x04>; + }; + + tcsr_mutex_block: syscon@01905000 { + compatible = "syscon"; + reg = <0x01905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + smem_mem: smem_region@86300000 { + no-map; + reg = <0x86300000 0x100000>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + modem { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 12>; + qcom,smd-edge = <0>; + qcom,remote-pid = <1>; + label = "mpss"; + + qcom,smd-channels = "IPCRTR"; + qcom,modem_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + adsp { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + label = "adsp"; + + qcom,smd-channels = "IPCRTR"; + qcom,adsp_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + wcnss { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 0 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + label = "wcnss"; + + qcom,smd-channels = "IPCRTR"; + qcom,wcnss_qrtr { + qcom,net-id = <1>; + qcom,low-latency; + }; + }; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 0>; + qcom,smd-edge = <15>; + label = "rpm"; + + rpm_requests: rpm_requests@0 { + compatible = "qcom,rpm-smd"; + qcom,smd-channels = "rpm_requests"; + }; + + }; + }; + + qcom,smdtty { + compatible = "qcom,smdtty"; + + smdtty_apps_fm: qcom,smdtty-apps-fm { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_FM"; + }; + + smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; + }; + + smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; + }; + + smdtty_mbalbridge: qcom,smdtty-mbalbridge { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "MBALBRIDGE"; + }; + + smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; + }; + + smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { + qcom,smdtty-remote = "wcnss"; + qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; + }; + + smdtty_data1: qcom,smdtty-data1 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA1"; + }; + + smdtty_data4: qcom,smdtty-data4 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA4"; + }; + + smdtty_data11: qcom,smdtty-data11 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA11"; + }; + + smdtty_data21: qcom,smdtty-data21 { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "DATA21"; + }; + + smdtty_loopback: smdtty-loopback { + qcom,smdtty-remote = "modem"; + qcom,smdtty-port-name = "LOOPBACK"; + qcom,smdtty-dev-name = "LOOPBACK_TTY"; + }; + }; + + qcom,smdpkt { + compatible = "qcom,smdpkt"; + + qcom,smdpkt-data5-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-dev-name = "smdcntl0"; + }; + + qcom,smdpkt-data22 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA22"; + qcom,smdpkt-dev-name = "smd22"; + }; + + qcom,smdpkt-data40-cntl { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA40_CNTL"; + qcom,smdpkt-dev-name = "smdcntl8"; + }; + + qcom,smdpkt-data2 { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "DATA2"; + qcom,smdpkt-dev-name = "at_mdm0"; + }; + + qcom,smdpkt-apr-apps2 { + qcom,smdpkt-remote = "adsp"; + qcom,smdpkt-port-name = "apr_apps2"; + qcom,smdpkt-dev-name = "apr_apps2"; + }; + + qcom,smdpkt-loopback { + qcom,smdpkt-remote = "modem"; + qcom,smdpkt-port-name = "LOOPBACK"; + qcom,smdpkt-dev-name = "smd_pkt_loopback"; + }; + }; + + qcom_tzlog: tz-log@08600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + qcom,adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-legacy-compute"; + qcom,msm_fastrpc_compute_cb { + compatible = "qcom,msm-fastrpc-legacy-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_iommu 0x2008 0x7>; + sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; + }; + }; + + sdcc1_ice: sdcc1ice@7803000 { + compatible = "qcom,ice"; + reg = <0x7803000 0x8000>; + interrupt-names = "sdcc_ice_nonsec_level_irq", + "sdcc_ice_sec_level_irq"; + interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>, + <0 313 IRQ_TYPE_LEVEL_HIGH>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&gcc SDCC1_ICE_CORE_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + qcom,op-freq-hz = <200000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <78 512 0 0>, /* No vote */ + <78 512 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm", "qcom,sdhci-msm-cqe"; + reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>, + <0x7803000 0x8000>; + reg-names = "hc_mem", "core_mem", "cqhci_mem", "cqhci_ice"; + + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <2 200>; + + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cmdq-latency-us = <2 200>, <2 200>; + + qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1046 3200>, /* 400 KB/s*/ + <78 512 52286 160000>, /* 20 MB/s */ + <78 512 65360 200000>, /* 25 MB/s */ + <78 512 130718 400000>, /* 50 MB/s */ + <78 512 130718 400000>, /* 100 MB/s */ + <78 512 261438 800000>, /* 200 MB/s */ + <78 512 261438 800000>, /* 400 MB/s */ + <78 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 + 50000000 100000000 200000000 400000000 4294967295>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + qcom,ice-clk-rates = <200000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + status = "disabled"; + }; + + sdhc_2: sdhci@7864900 { + compatible = "qcom,sdhci-msm"; + reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <2 200>; + + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1046 3200>, /* 400 KB/s*/ + <81 512 52286 160000>, /* 20 MB/s */ + <81 512 65360 200000>, /* 25 MB/s */ + <81 512 130718 400000>, /* 50 MB/s */ + <81 512 261438 800000>, /* 100 MB/s */ + <81 512 261438 800000>, /* 200 MB/s */ + <81 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,devfreq,freq-table = <50000000 200000000>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + status = "disabled"; + }; + + qcom_seecom: qseecom@85b00000 { + compatible = "qcom,qseecom"; + reg = <0x85b00000 0x800000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,support-bus-scaling; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 0 0>, + <55 512 120000 1200000>, + <55 512 393600 3936000>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_crypto: qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,ce-opp-freq = <100000000>; + }; + + qcom_cedev: qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clocks = <&gcc CRYPTO_CLK_SRC>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + qcom,ce-opp-freq = <100000000>; + }; + + pil_mss: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x04080000 0x100>, + <0x0194f000 0x010>, + <0x01950000 0x008>, + <0x01951000 0x008>, + <0x04020000 0x040>, + <0x01871000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", + "rmb_base", "restart_reg"; + + interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; + vdd_mss-supply = <&pm8937_s1>; + vdd_cx-supply = <&pm8937_s2_level>; + vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_mx-supply = <&pm8937_l3_level_ao>; + vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_pll-supply = <&pm8937_l7>; + qcom,vdd_pll = <1800000>; + vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + + clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>; + clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; + qcom,proxy-clock-names = "xo"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; + + qcom,pas-id = <5>; + qcom,pil-mss-memsetup; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sequential-fw-load; + qcom,override-acc-1 = <0x80800000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v56-1-8-inrush-current; + qcom,reset-clk; + + /* Inputs from mss */ + interrupts-extended = <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&modem_mem>; + }; + + qcom,lpass@c200000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xc200000 0x00100>; + interrupts = <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>; + + vdd_cx-supply = <&pm8937_s2_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; + + clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,scm_core_clk_src-freq = <80000000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + + /* Inputs from lpass */ + interrupts-extended = <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&adsp_fw_mem>; + }; + + qcom,pronto@a21b000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x0a21b000 0x3000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; + + vdd_pronto_pll-supply = <&pm8937_l7>; + proxy-reg-names = "vdd_pronto_pll"; + vdd_pronto_pll-uV-uA = <1800000 18000>; + clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + + clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,scm_core_clk_src = <80000000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <6>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <422>; + qcom,sysmon-id = <6>; + qcom,ssctl-instance-id = <0x13>; + qcom,firmware-name = "wcnss"; + + /* Inputs from wcnss */ + interrupts-extended = <&wcnss_smp2p_in 0 0>, + <&wcnss_smp2p_in 1 0>, + <&wcnss_smp2p_in 2 0>, + <&wcnss_smp2p_in 3 0>; + + interrupt-names = "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to wcnss */ + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + memory-region = <&wcnss_fw_mem>; + }; + + qcom,venus@1de0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1de0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + + clock-names = "core_clk", "iface_clk", "bus_clk", + "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "scm_core_clk", + "scm_iface_clk", "scm_bus_clk", + "scm_core_clk_src"; + qcom,scm_core_clk_src-freq = <80000000>; + + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + + qcom,mas-crypto = <&mas_crypto>; + qcom,pas-id = <9>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&venus_mem>; + }; + + qcom,wcnss-wlan@0a000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0x0a000000 0x280000>, + <0xb011008 0x04>, + <0x0a21b000 0x3000>, + <0x03204000 0x00000100>, + <0x03200800 0x00000200>, + <0x0a100400 0x00000200>, + <0x0a205050 0x00000200>, + <0x0a219000 0x00000020>, + <0x0a080488 0x00000008>, + <0x0a080fb0 0x00000008>, + <0x0a08040c 0x00000008>, + <0x0a0120a8 0x00000008>, + <0x0a012448 0x00000008>, + <0x0a080c00 0x00000001>; + + reg-names = "wcnss_mmio", "wcnss_fiq", + "pronto_phy_base", "riva_phy_base", + "riva_ccu_base", "pronto_a2xb_base", + "pronto_ccpu_base", "pronto_saw2_base", + "wlan_tx_phy_aborts","wlan_brdg_err_source", + "wlan_tx_status", "alarms_txctl", + "alarms_tactl", "pronto_mcu_base"; + + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>; + qcom,pronto-vddcx-supply = <&pm8937_s2_level>; + qcom,pronto-vddpx-supply = <&pm8937_l5>; + qcom,iris-vddxo-supply = <&pm8937_l7>; + qcom,iris-vddrfa-supply = <&pm8937_l19>; + qcom,iris-vddpa-supply = <&pm8937_l9>; + qcom,iris-vdddig-supply = <&pm8937_l5>; + + qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; + qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>; + qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; + qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; + + qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,vddpx-voltage-level = <1800000 0 1800000>; + + qcom,iris-vddxo-current = <10000>; + qcom,iris-vddrfa-current = <100000>; + qcom,iris-vddpa-current = <515000>; + qcom,iris-vdddig-current = <10000>; + + qcom,pronto-vddmx-current = <0>; + qcom,pronto-vddcx-current = <0>; + qcom,pronto-vddpx-current = <0>; + + pinctrl-names = "wcnss_default", "wcnss_sleep", + "wcnss_gpio_default"; + pinctrl-0 = <&wcnss_default>; + pinctrl-1 = <&wcnss_sleep>; + pinctrl-2 = <&wcnss_gpio_default>; + + gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>, + <&tlmm 79 0>, <&tlmm 80 0>; + + clocks = <&rpmcc CXO_SMD_WLAN_CLK>, + <&rpmcc RPM_SMD_RF_CLK2>, + <&rpmcc SNOC_WCNSS_A_CLK>; + + clock-names = "xo", "rf_clk", "snoc_wcnss"; + + qcom,snoc-wcnss-clock-freq = <200000000>; + + qcom,has-autodetect-xo; + qcom,is-pronto-v3; + qcom,has-pronto-hw; + qcom,has-vsys-adc-channel; + qcom,wcnss-adc_tm = <&pm8937_adc_tm>; + }; + + bam_dmux: qcom,bam_dmux@4044000 { + compatible = "qcom,bam_dmux"; + reg = <0x4044000 0x19000>; + interrupts = <0 162 1>; + qcom,rx-ring-size = <32>; + qcom,max-rx-mtu = <4096>; + qcom,fast-shutdown; + qcom,no-cpu-affinity; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + }; + +}; + +#include "pm8937-rpm-regulator.dtsi" +#include "msm8937-regulator.dtsi" +#include "pm8937.dtsi" +#include "msm8937-audio.dtsi" +#include "msm8937-camera.dtsi" +#include "msm-gdsc-8916.dtsi" +#include "msm8937-coresight.dtsi" +#include "msm8937-thermal.dtsi" + +&gdsc_venus { + clock-names = "bus_clk", "core_clk"; + clocks = <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_VENUS0_VCODEC0_CLK>; + status = "okay"; +}; + +&gdsc_venus_core0 { + qcom,support-hw-trigger; + clock-names ="core0_clk"; + clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>; + status = "okay"; +}; + +&gdsc_mdss { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AXI_CLK>; + qcom,disallow-clear; + status = "okay"; +}; + +&gdsc_jpeg { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>; + status = "okay"; +}; + +&gdsc_vfe { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>; + status = "okay"; +}; + +&gdsc_vfe1 { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + status = "okay"; +}; + +&gdsc_cpp { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>; + status = "okay"; +}; + +&gdsc_oxili_gx { + clock-names = "core_root_clk"; + clocks =<&gcc GFX3D_CLK_SRC>; + qcom,enable-root-clk; + qcom,clk-dis-wait-val = <0x5>; + status = "okay"; +}; + +&gdsc_oxili_cx { + reg = <0x1859044 0x4>; + clock-names = "core_clk"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>; + status = "okay"; +}; diff --git a/qcom/msm8953-wsa881x.dtsi b/qcom/msm8953-wsa881x.dtsi new file mode 100644 index 00000000..009521a7 --- /dev/null +++ b/qcom/msm8953-wsa881x.dtsi @@ -0,0 +1,34 @@ +&slim_msm { + tasha_codec { + swr_master { + compatible = "qcom,swr-wcd"; + qcom,swr-num-dev = <2>; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-gpio = <&tlmm 96 0>; + }; + + wsa881x_212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-gpio = <&tlmm 96 0>; + }; + + wsa881x_213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-gpio = <&tlmm 96 0>; + }; + + wsa881x_214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-gpio = <&tlmm 96 0>; + }; + }; + }; +}; diff --git a/qcom/pm8916-rpm-regulator.dtsi b/qcom/pm8916-rpm-regulator.dtsi new file mode 100644 index 00000000..b9a31fc0 --- /dev/null +++ b/qcom/pm8916-rpm-regulator.dtsi @@ -0,0 +1,371 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm8916.dtsi b/qcom/pm8916.dtsi new file mode 100644 index 00000000..45cc99ac --- /dev/null +++ b/qcom/pm8916.dtsi @@ -0,0 +1,573 @@ +&spmi_bus { + + qcom,pm8916@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + + pm8916_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pm8916_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0>, + <0x0 0x8 0x1>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,clear-warm-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <10256>; + qcom,s2-timer = <2000>; + qcom,s2-type = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pm8916_mpps: mpps { + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8916-mpp"; + + mpp@a000 { + reg = <0xa000 0x100>; + qcom,pin-num = <1>; + }; + + mpp@a100 { + reg = <0xa100 0x100>; + qcom,pin-num = <2>; + }; + + mpp@a200 { + reg = <0xa200 0x100>; + qcom,pin-num = <3>; + }; + + mpp@a300 { + reg = <0xa300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8916_gpios: gpios { + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8916-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + }; + }; + + pm8916_rtc: qcom,pm8916_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8916_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8916_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1>; + }; + }; + + pm8916_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,vadc-poll-eoc; + qcom,pmic-revid = <&pm8916_revid>; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + pm8916_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0>; + label = "pm8916_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + qcom,temp_alarm-vadc = <&pm8916_vadc>; + }; + + pm8916_adc_tm: vadc@3400 { + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0>, + <0x0 0x34 0x3>, + <0x0 0x34 0x4>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,adc_tm-vadc = <&pm8916_vadc>; + qcom,pmic-revid = <&pm8916_revid>; + }; + + pm8916_chg: qcom,charger { + #address-cells = <1>; + #size-cells = <1>; + + qcom,vddmax-mv = <4200>; + qcom,vddsafe-mv = <4200>; + qcom,vinmin-mv = <4308>; + qcom,ibatsafe-ma = <1440>; + qcom,thermal-mitigation = <1440 720 630 0>; + qcom,cool-bat-decidegc = <100>; + qcom,warm-bat-decidegc = <450>; + qcom,cool-bat-mv = <4100>; + qcom,warm-bat-mv = <4100>; + qcom,ibatmax-warm-ma = <360>; + qcom,ibatmax-cool-ma = <360>; + qcom,batt-hot-percentage = <25>; + qcom,batt-cold-percentage = <80>; + qcom,tchg-mins = <232>; + qcom,chg-vadc = <&pm8916_vadc>; + qcom,chg-adc_tm = <&pm8916_adc_tm>; + + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x7>, + <0x0 0x10 0x6>, + <0x0 0x10 0x5>, + <0x0 0x10 0x0>; + interrupt-names = "chg-done", + "chg-failed", + "fast-chg-on", + "vbat-det-lo"; + }; + + qcom,bat-if@1200 { + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x1>, + <0x0 0x12 0x0>; + interrupt-names = "bat-temp-ok", + "batt-pres"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300 0x100>; + interrupts = <0 0x13 0x4>, + <0 0x13 0x2>, + <0 0x13 0x1>; + interrupt-names = "usb-over-temp", + "chg-gone", + "usbin-valid"; + }; + + qcom,chg-misc@1600 { + reg = <0x1600 0x100>; + }; + }; + + pm8916_bms: qcom,vmbms { + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + qcom,v-cutoff-uv = <3400000>; + qcom,max-voltage-uv = <4200000>; + qcom,r-conn-mohm = <0>; + qcom,shutdown-soc-valid-limit = <100>; + qcom,low-soc-calculate-soc-threshold = <15>; + qcom,low-voltage-calculate-soc-ms = <1000>; + qcom,low-soc-calculate-soc-ms = <5000>; + qcom,calculate-soc-ms = <20000>; + qcom,volatge-soc-timeout-ms = <60000>; + qcom,low-voltage-threshold = <3450000>; + qcom,s3-ocv-tolerence-uv = <1200>; + qcom,s2-fifo-length = <5>; + qcom,low-soc-fifo-length = <2>; + qcom,bms-vadc = <&pm8916_vadc>; + qcom,bms-adc_tm = <&pm8916_adc_tm>; + qcom,pmic-revid = <&pm8916_revid>; + + qcom,force-s3-on-suspend; + qcom,force-s2-in-charging; + qcom,report-charger-eoc; + qcom,resume-soc = <99>; + + qcom,batt-pres-status@1208 { + reg = <0x1208 0x1>; + }; + + qcom,qpnp-chg-pres@1008 { + reg = <0x1008 0x1>; + }; + + qcom,vm-bms@4000 { + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0>, + <0x0 0x40 0x1>, + <0x0 0x40 0x2>, + <0x0 0x40 0x3>, + <0x0 0x40 0x4>, + <0x0 0x40 0x5>; + + interrupt-names = "leave_cv", + "enter_cv", + "good_ocv", + "ocv_thr", + "fifo_update_done", + "fsm_state_change"; + }; + }; + + pm8916_leds: qcom,leds@a100 { + reg = <0xa100 0x100>; + label = "mpp"; + }; + }; + + qcom,pm8916@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <1>; + + regulator@1400 { + regulator-name = "8916_s1"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700 0x300>; + status = "disabled"; + + qcom,ctl@1700 { + reg = <0x1700 0x100>; + }; + + qcom,ps@1800 { + reg = <0x1800 0x100>; + }; + + qcom,freq@1900 { + reg = <0x1900 0x100>; + }; + }; + + regulator@1a00 { + regulator-name = "8916_s3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1a00 0x300>; + status = "disabled"; + + qcom,ctl@1a00 { + reg = <0x1a00 0x100>; + }; + + qcom,ps@1b00 { + reg = <0x1b00 0x100>; + }; + + qcom,freq@1c00 { + reg = <0x1c00 0x100>; + }; + }; + + regulator@1d00 { + regulator-name = "8916_s4"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1d00 0x300>; + status = "disabled"; + + qcom,ctl@1d00 { + reg = <0x1d00 0x100>; + }; + + qcom,ps@1e00 { + reg = <0x1e00 0x100>; + }; + + qcom,freq@1f00 { + reg = <0x1f00 0x100>; + }; + + }; + + regulator@4000 { + regulator-name = "8916_l1"; + reg = <0x4000 0x100>; + status = "disabled"; + }; + + regulator@4100 { + regulator-name = "8916_l2"; + reg = <0x4100 0x100>; + status = "disabled"; + }; + + regulator@4200 { + regulator-name = "8916_l3"; + reg = <0x4200 0x100>; + status = "disabled"; + }; + + regulator@4300 { + regulator-name = "8916_l4"; + reg = <0x4300 0x100>; + status = "disabled"; + }; + + regulator@4400 { + regulator-name = "8916_l5"; + reg = <0x4400 0x100>; + status = "disabled"; + }; + + regulator@4500 { + regulator-name = "8916_l6"; + reg = <0x4500 0x100>; + status = "disabled"; + }; + + regulator@4600 { + regulator-name = "8916_l7"; + reg = <0x4600 0x100>; + status = "disabled"; + }; + + regulator@4700 { + regulator-name = "8916_l8"; + reg = <0x4700 0x100>; + status = "disabled"; + }; + + regulator@4800 { + regulator-name = "8916_l9"; + reg = <0x4800 0x100>; + status = "disabled"; + }; + + regulator@4900 { + regulator-name = "8916_l10"; + reg = <0x4900 0x100>; + status = "disabled"; + }; + + regulator@4a00 { + regulator-name = "8916_l11"; + reg = <0x4a00 0x100>; + status = "disabled"; + }; + + regulator@4b00 { + regulator-name = "8916_l12"; + reg = <0x4b00 0x100>; + status = "disabled"; + }; + + regulator@4c00 { + regulator-name = "8916_l13"; + reg = <0x4c00 0x100>; + status = "disabled"; + }; + + regulator@4d00 { + regulator-name = "8916_l14"; + reg = <0x4d00 0x100>; + status = "disabled"; + }; + + regulator@4e00 { + regulator-name = "8916_l15"; + reg = <0x4e00 0x100>; + status = "disabled"; + }; + + regulator@4f00 { + regulator-name = "8916_l16"; + reg = <0x4f00 0x100>; + status = "disabled"; + }; + + regulator@5000 { + regulator-name = "8916_l17"; + reg = <0x5000 0x100>; + status = "disabled"; + }; + + regulator@5100 { + regulator-name = "8916_l18"; + reg = <0x5100 0x100>; + status = "disabled"; + }; + + pm8916_pwm: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x100>; + reg-names = "qpnp-lpg-channel-base"; + qcom,channel-id = <0>; + qcom,supported-sizes = <6>, <9>; + #pwm-cells = <2>; + }; + + pm8916_vib: qcom,vibrator@c000 { + compatible = "qcom,qpnp-vibrator"; + reg = <0xc000 0x100>; + label = "vibrator"; + status = "disabled"; + }; + + pm8916_tombak_dig: msm8x16_wcd_codec@f000 { + reg = <0xf000 0x100>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0>, + <0x1 0xf0 0x1>, + <0x1 0xf0 0x2>, + <0x1 0xf0 0x3>, + <0x1 0xf0 0x4>, + <0x1 0xf0 0x5>, + <0x1 0xf0 0x6>, + <0x1 0xf0 0x7>; + interrupt-names = "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int"; + + cdc-vdda-cp-supply = <&pm8916_s4>; + qcom,cdc-vdda-cp-voltage = <1800000 2200000>; + qcom,cdc-vdda-cp-current = <770000>; + + cdc-vdda-h-supply = <&pm8916_l5>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <20000>; + + cdc-vdd-px-supply = <&pm8916_s4>; + qcom,cdc-vdd-px-voltage = <1800000 2200000>; + qcom,cdc-vdd-px-current = <770000>; + + cdc-vdd-pa-supply = <&pm8916_l5>; + qcom,cdc-vdd-pa-voltage = <1800000 1800000>; + qcom,cdc-vdd-pa-current = <5000>; + + cdc-vdd-mic-bias-supply = <&pm8916_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-mclk-clk-rate = <9600000>; + + qcom,cdc-static-supplies = "cdc-vdda-h", + "cdc-vdd-px", + "cdc-vdd-pa", + "cdc-vdda-cp"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + }; + + pm8916_tombak_analog: msm8x16_wcd_codec@f100 { + reg = <0xf100 0x100>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf1 0x0>, + <0x1 0xf1 0x1>, + <0x1 0xf1 0x2>, + <0x1 0xf1 0x3>, + <0x1 0xf1 0x4>, + <0x1 0xf1 0x5>; + interrupt-names = "ear_ocp_int", + "hphr_ocp_int", + "hphl_ocp_det", + "ear_cnp_int", + "hphr_cnp_int", + "hphl_cnp_int"; + }; + + pm8916_bcm: qpnp-buck-current-monitor@1800 { + reg = <0x1800 0x100>; + interrupts = <1 0x18 0>, <1 0x18 1>; + interrupt-names = "iwarning", "icritical"; + qcom,enable-current-monitor; + qcom,icrit-init-threshold-pc = <90>; + qcom,iwarn-init-threshold-pc = <70>; + qcom,icrit-polling-delay-msec = <1000>; + qcom,iwarn-polling-delay-msec = <2000>; + + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm8937-rpm-regulator.dtsi b/qcom/pm8937-rpm-regulator.dtsi new file mode 100644 index 00000000..8ecb8d0c --- /dev/null +++ b/qcom/pm8937-rpm-regulator.dtsi @@ -0,0 +1,371 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8937_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm8937.dtsi b/qcom/pm8937.dtsi new file mode 100644 index 00000000..2a9ed193 --- /dev/null +++ b/qcom/pm8937.dtsi @@ -0,0 +1,414 @@ +&spmi_bus { + + qcom,pm8937@0 { + compatible ="qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8937_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pm8937_temp_alarm: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8937_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + qcom,temp_alarm-vadc = <&pm8937_vadc>; + #thermal-sensor-cells = <0>; + }; + + + pm8937_rtc: qcom,pm8937_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8937_mpps: mpps { + compatible = "qcom,spmi-mpp"; + reg = <0xa000 0x400>; + interrupts = <0x0 0xa0 0 IRQ_TYPE_NONE>, + <0x0 0xa1 0 IRQ_TYPE_NONE>, + <0x0 0xa2 0 IRQ_TYPE_NONE>, + <0x0 0xa3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8937_mpp1", "pm8937_mpp2", + "pm8937_mpp3", "pm8937_mpp4"; + gpio-controller; + #gpio-cells = <2>; + + case_therm { + cas_therm_default: cas_therm_default { + pins = "mpp4"; + function = "analog"; + input-enable; + qcom,amux-route = <3>; + }; + }; + + pa_therm1 { + pa_therm1_default: pa_therm1_default { + pins = "mpp2"; + function = "analog"; + input-enable; + qcom,amux-route = <1>; + }; + }; + }; + + pm8937_gpios: gpios { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x800>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8937_gpio1", "pm8937_gpio2", + "pm8937_gpio5", "pmi8937_gpio7", + "pm8937_gpio8"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <3 4 6>; + }; + + pm8937_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,vadc-poll-eoc; + #thermal-sensor-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pa_therm1_default &cas_therm_default>; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@c { + label = "ref_buf_625mv"; + reg = <0xc>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@36 { + label = "pa_therm0"; + reg = <0x36>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@11 { + label = "pa_therm1"; + reg = <0x11>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@3c { + label = "xo_therm_buf"; + reg = <0x3c>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@13 { + label = "case_therm"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + }; + + pm8937_adc_tm: vadc@3400 { + compatible = "qcom,adc-tm-rev2"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,adc_tm-vadc = <&pm8937_vadc>; + #thermal-sensor-cells = <1>; + + chan@36 { + label = "pa_therm0"; + reg = <0x36>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x48>; + qcom,thermal-node; + }; + + chan@7 { + label = "vph_pwr"; + reg = <0x7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,btm-channel-number = <0x68>; + }; + }; + + }; + + pm8937_1: qcom,pm8937@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8937_pwm: pwm@bc00 { + status = "disabled"; + compatible = "qcom,qpnp-pwm"; + reg = <0xbc00 0x100>; + reg-names = "qpnp-lpg-channel-base"; + qcom,channel-id = <0>; + qcom,supported-sizes = <6>, <9>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pa-therm1-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8937_vadc 0x11>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8937_vadc 0x32>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-buf-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8937_vadc 0x3c>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + case-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8937_vadc 0x13>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8937_adc_tm 0x36>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pm8937_tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8937_temp_alarm>; + wake-capable-sensor; + + trips { + pm8937_trip0: pm8937-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8937_trip1: pm8937-trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8937_trip2: pm8937-trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8953-rpm-regulator.dtsi b/qcom/pm8953-rpm-regulator.dtsi new file mode 100644 index 00000000..3c10ed73 --- /dev/null +++ b/qcom/pm8953-rpm-regulator.dtsi @@ -0,0 +1,386 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <7>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + qcom,regulator-hw-type = "pmic4-ldo"; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* Regulator to notify APC corner to RPM */ + rpm-regulator-clk0 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "clk0"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-clk0 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "rpm_apc"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm8953.dtsi b/qcom/pm8953.dtsi new file mode 100644 index 00000000..d81ac710 --- /dev/null +++ b/qcom/pm8953.dtsi @@ -0,0 +1,399 @@ +&spmi_bus { + + qcom,pm8953@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8953_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pm8953_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8953_tz"; + qcom,channel-num = <8>; + qcom,threshold-set = <0>; + qcom,temp_alarm-vadc = <&pm8953_vadc>; + #thermal-sensor-cells = <0>; + }; + + pm8953_mpps: mpps { + compatible = "qcom,spmi-mpp"; + reg = <0xa000 0x400>; + + interrupts = <0x0 0xa0 0 IRQ_TYPE_NONE>, + <0x0 0xa1 0 IRQ_TYPE_NONE>, + <0x0 0xa2 0 IRQ_TYPE_NONE>, + <0x0 0xa3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8953_mpp1", "pm8953_mpp2", + "pm8953_mpp3", "pm8953_mpp4"; + + gpio-controller; + #gpio-cells = <2>; + + case_therm { + cas_therm_default: cas_therm_default { + pins = "mpp4"; + function = "analog"; + input-enable; + qcom,amux-route = <3>; + }; + }; + + pa_therm1 { + pa_therm1_default: pa_therm1_default { + pins = "mpp2"; + function = "analog"; + input-enable; + qcom,amux-route = <1>; + }; + }; + }; + + pm8953_gpios: gpios { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x800>; + + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8953_gpio1", "pm8953_gpio2", + "pm8953_gpio4", "pm8953_gpio5", + "pm8953_gpio7", "pm8953_gpio8"; + + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <3 6>; + }; + + pm8953_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,vadc-poll-eoc; + #thermal-sensor-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pa_therm1_default &cas_therm_default>; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@8 { + label = "die_temp"; + reg = <8>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@9 { + label = "ref_625mv"; + reg = <9>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@a { + label = "ref_1250v"; + reg = <0xa>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@c { + label = "ref_buf_625mv"; + reg = <0xc>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@36 { + label = "pa_therm0"; + reg = <0x36>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@11 { + label = "pa_therm1"; + reg = <0x11>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@3c { + label = "xo_therm_buf"; + reg = <0x3c>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@13 { + label = "case_therm"; + reg = <0x13>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + }; + + pm8953_adc_tm: vadc@3400 { + compatible = "qcom,adc-tm-rev2"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1800>; + qcom,adc_tm-vadc = <&pm8953_vadc>; + #thermal-sensor-cells = <1>; + + chan@36 { + label = "pa_therm0"; + reg = <0x36>; + qcom,pre-div-channel-scaling = <0>; + qcom,decimation = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x48>; + qcom,fast-avg-setup = <0>; + qcom,thermal-node; + }; + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,pre-div-channel-scaling = <0>; + qcom,decimation = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,fast-avg-setup = <0>; + qcom,thermal-node; + }; + }; + + pm8953_rtc: qcom,pm8953_rtc { + spmi-dev-container; + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8953_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm8953_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8953_typec: qcom,pm8953_typec@bf00 { + compatible = "qcom,qpnp-typec"; + reg = <0xbf00 0x100>; + interrupts = <0x0 0xbf 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0xbf 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "vrd-change", + "ufp-detect", + "ufp-detach", + "dfp-detect", + "dfp-detach", + "vbus-err", + "vconn-oc"; + }; + }; + + pm8953_1: qcom,pm8953@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8953_pwm: qcom,pwms@bc00 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x100>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8953_adc_tm 0x32>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-buf-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8953_vadc 0x3c>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pm8953_tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8953_tz>; + wake-capable-sensor; + + trips { + pm8953_trip0: pm8953-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8953_trip1: pm8953-trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8953_trip2: pm8953-trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index 26464cc7..92636bd2 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -331,6 +331,9 @@ "ilim2-s2", "vreg-ok"; }; + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; }; pmi632_qg: qpnp,qg { diff --git a/qcom/qcm2150-qrd-overlay.dts b/qcom/qcm2150-qrd-overlay.dts new file mode 100644 index 00000000..67fbe50e --- /dev/null +++ b/qcom/qcm2150-qrd-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "qcm2150-qrd.dtsi" + +/ { + model = "QRD"; + qcom,board-id = <0x01000b 4>; +}; diff --git a/qcom/qcm2150-qrd.dts b/qcom/qcm2150-qrd.dts new file mode 100644 index 00000000..5dbd00ed --- /dev/null +++ b/qcom/qcm2150-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "qcm2150.dtsi" +#include "qcm2150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCM2150 QRD"; + compatible = "qcom,qcm2150-qrd", "qcom,qcm2150", "qcom,qrd"; + qcom,board-id = <0x01000b 4>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/qcm2150-qrd.dtsi b/qcom/qcm2150-qrd.dtsi new file mode 100644 index 00000000..ae36bce3 --- /dev/null +++ b/qcom/qcm2150-qrd.dtsi @@ -0,0 +1,5 @@ +#include "qm215-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCM2150 QRD"; +}; diff --git a/qcom/qcm2150.dts b/qcom/qcm2150.dts new file mode 100644 index 00000000..3285ef44 --- /dev/null +++ b/qcom/qcm2150.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "qcm2150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCM2150"; + compatible = "qcom,qcm2150"; + qcom,pmic-name = "PM8916"; +}; diff --git a/qcom/qcm2150.dtsi b/qcom/qcm2150.dtsi new file mode 100644 index 00000000..07091d40 --- /dev/null +++ b/qcom/qcm2150.dtsi @@ -0,0 +1,11 @@ +#include "qm215.dtsi" +#include "qm215-pm8916.dtsi" +/* TBD */ +/* #include "qm215-audio.dtsi" */ + +/ { + model = "Qualcomm Technologies, Inc. QCM2150"; + compatible = "qcom,qcm2150"; + qcom,msm-id = <436 0x0>; + qcom,msm-name = "QCM2150"; +}; diff --git a/qcom/qg-batterydata-ascent-3450mah.dtsi b/qcom/qg-batterydata-ascent-3450mah.dtsi new file mode 100644 index 00000000..ee06816b --- /dev/null +++ b/qcom/qg-batterydata-ascent-3450mah.dtsi @@ -0,0 +1,1031 @@ +qcom,ascent_3450mah { + /* Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018 */ + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,fastchg-current-ma = <3450>; + qcom,batt-id-kohm = <60>; + qcom,battery-beta = <3435>; + qcom,battery-therm-kohm = <68>; + qcom,battery-type = + "Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 100 1725000 + 101 400 3450000 + 401 450 2760000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 101 400 4350000 + 401 450 4250000>; + qcom,step-chg-ranges = <3600000 4200000 3450000 + 4201000 4300000 2760000 + 4301000 4350000 2070000>; + + /* COOL = 5 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x44bd 0x1fc4>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x4aa5 0x1bfb>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3377 3428 3481 3496 3500>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3480 3482 3476 3492 3478 3466>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43212 43315 43370 43380 43383>, + <42963 43071 43141 43149 43152>, + <42723 42832 42902 42916 42922>, + <42488 42597 42662 42683 42693>, + <42262 42367 42430 42454 42465>, + <42043 42143 42202 42225 42238>, + <41832 41924 41976 41999 42013>, + <41624 41709 41754 41775 41791>, + <41419 41497 41536 41556 41571>, + <41220 41288 41322 41341 41355>, + <41039 41091 41113 41132 41143>, + <40866 40911 40916 40928 40936>, + <40676 40732 40729 40729 40734>, + <40449 40526 40541 40538 40541>, + <40230 40302 40340 40351 40355>, + <40061 40115 40146 40170 40176>, + <39918 39974 39984 40002 40007>, + <39787 39846 39843 39845 39846>, + <39672 39712 39697 39690 39689>, + <39560 39579 39548 39536 39538>, + <39426 39419 39388 39376 39384>, + <39271 39170 39192 39187 39198>, + <39112 38928 38961 38960 38967>, + <38934 38809 38788 38776 38775>, + <38764 38736 38674 38650 38646>, + <38660 38665 38581 38546 38539>, + <38589 38587 38491 38448 38439>, + <38533 38513 38408 38359 38347>, + <38487 38444 38334 38278 38263>, + <38448 38381 38265 38204 38187>, + <38407 38323 38204 38138 38118>, + <38364 38269 38149 38078 38055>, + <38322 38219 38099 38026 37999>, + <38284 38175 38053 37975 37942>, + <38249 38137 38014 37930 37889>, + <38211 38098 37974 37884 37834>, + <38174 38061 37930 37831 37767>, + <38129 38020 37882 37771 37691>, + <38055 37954 37816 37698 37610>, + <37946 37848 37718 37605 37524>, + <37825 37726 37602 37497 37426>, + <37689 37595 37474 37372 37301>, + <37541 37451 37332 37231 37156>, + <37372 37290 37178 37080 36999>, + <37271 37162 37061 36964 36886>, + <37191 37093 36992 36897 36819>, + <37157 37064 36970 36870 36798>, + <37128 37039 36949 36844 36770>, + <37084 37007 36903 36788 36714>, + <36927 36851 36683 36562 36488>, + <36555 36481 36290 36180 36108>, + <36071 35999 35771 35687 35620>, + <35450 35376 35098 35050 34994>, + <34604 34523 34174 34184 34150>, + <33275 33138 32725 32851 32862>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43425 43415 43385 43360 43315 43295>, + <43070 43109 43097 43094 43052 43033>, + <42748 42821 42826 42838 42799 42781>, + <42462 42555 42571 42594 42557 42541>, + <42208 42308 42333 42361 42326 42312>, + <41968 42072 42101 42133 42099 42086>, + <41736 41844 41872 41904 41872 41860>, + <41516 41625 41649 41680 41649 41637>, + <41303 41405 41431 41460 41430 41419>, + <41100 41186 41217 41243 41215 41204>, + <40896 40979 41012 41034 41005 40994>, + <40694 40796 40826 40840 40802 40789>, + <40482 40616 40642 40648 40604 40590>, + <40220 40407 40432 40445 40411 40399>, + <39903 40175 40199 40233 40222 40214>, + <39636 39954 39996 40043 40042 40036>, + <39443 39759 39844 39886 39877 39868>, + <39272 39570 39700 39736 39717 39706>, + <39091 39370 39511 39573 39556 39547>, + <38908 39162 39283 39399 39396 39391>, + <38742 38973 39072 39208 39217 39217>, + <38591 38806 38886 38975 38988 38994>, + <38460 38655 38721 38760 38766 38771>, + <38358 38519 38585 38613 38613 38614>, + <38274 38396 38468 38496 38494 38494>, + <38201 38287 38362 38390 38388 38387>, + <38138 38189 38265 38294 38291 38288>, + <38080 38106 38177 38206 38202 38198>, + <38027 38039 38096 38126 38120 38114>, + <37980 37983 38021 38051 38044 38037>, + <37934 37935 37954 37984 37976 37967>, + <37889 37895 37891 37921 37915 37905>, + <37843 37856 37838 37862 37856 37846>, + <37795 37815 37799 37803 37790 37781>, + <37746 37774 37768 37746 37720 37707>, + <37692 37727 37728 37685 37643 37621>, + <37633 37677 37677 37620 37554 37517>, + <37568 37618 37617 37550 37465 37411>, + <37491 37546 37548 37475 37387 37327>, + <37404 37459 37466 37395 37313 37256>, + <37310 37360 37369 37301 37226 37174>, + <37206 37243 37246 37187 37117 37069>, + <37103 37111 37106 37050 36988 36945>, + <37005 36964 36946 36900 36839 36796>, + <36909 36860 36837 36818 36761 36712>, + <36808 36782 36769 36775 36718 36673>, + <36746 36740 36732 36741 36690 36651>, + <36670 36688 36684 36692 36649 36612>, + <36553 36594 36591 36575 36542 36528>, + <36329 36380 36368 36272 36271 36278>, + <35961 35991 35957 35796 35833 35867>, + <35436 35452 35401 35193 35271 35340>, + <34709 34745 34680 34409 34550 34676>, + <33672 33759 33677 33330 33585 33791>, + <31857 32191 32244 31867 32001 32517>, + <28160 28896 29014 27510 28586 29617>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <13703 12983 12375 12138 12079>, + <13647 12967 12370 12145 12092>, + <13621 12953 12363 12143 12093>, + <13606 12942 12357 12142 12093>, + <13594 12927 12349 12140 12093>, + <13585 12916 12342 12137 12093>, + <13577 12905 12339 12136 12092>, + <13569 12898 12337 12135 12092>, + <13560 12896 12337 12135 12091>, + <13551 12895 12339 12135 12091>, + <13540 12896 12342 12136 12091>, + <13527 12899 12342 12136 12091>, + <13512 12901 12342 12137 12093>, + <13488 12896 12342 12139 12095>, + <13469 12887 12343 12141 12097>, + <13469 12883 12347 12144 12098>, + <13473 12891 12352 12147 12101>, + <13478 12904 12360 12151 12103>, + <13489 12912 12369 12155 12106>, + <13502 12919 12378 12160 12109>, + <13514 12927 12387 12165 12113>, + <13525 12937 12396 12171 12117>, + <13538 12948 12404 12177 12122>, + <13555 12957 12412 12184 12127>, + <13572 12965 12422 12189 12131>, + <13578 12971 12431 12195 12135>, + <13580 12978 12440 12200 12139>, + <13582 12985 12448 12206 12143>, + <13594 12992 12456 12212 12147>, + <13613 13004 12464 12218 12151>, + <13625 13010 12472 12224 12156>, + <13631 13010 12479 12230 12160>, + <13632 13010 12486 12237 12165>, + <13627 13015 12494 12244 12171>, + <13618 13033 12505 12253 12177>, + <13619 13047 12517 12262 12183>, + <13629 13056 12529 12271 12190>, + <13640 13065 12541 12280 12196>, + <13647 13068 12553 12290 12203>, + <13654 13070 12565 12301 12210>, + <13663 13071 12577 12311 12217>, + <13678 13085 12588 12322 12224>, + <13694 13098 12598 12332 12232>, + <13718 13107 12607 12344 12239>, + <13717 13110 12621 12356 12248>, + <13717 13111 12638 12367 12256>, + <13693 13110 12640 12374 12262>, + <13712 13131 12642 12382 12269>, + <13714 13118 12659 12395 12280>, + <13717 13140 12677 12408 12291>, + <13717 13160 12678 12422 12303>, + <13740 13166 12691 12436 12316>, + <13739 13183 12711 12456 12332>, + <13754 13201 12735 12479 12355>, + <13754 13201 12735 12479 12355>, + <13754 13201 12735 12479 12355>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9983 10351 10639 10481 10418>, + <10020 10341 10669 10329 10279>, + <10051 10333 10528 10319 10282>, + <10083 10331 10397 10312 10281>, + <10100 10329 10358 10299 10263>, + <10094 10325 10328 10285 10234>, + <10081 10303 10324 10279 10227>, + <10069 10281 10328 10277 10237>, + <10058 10278 10330 10276 10251>, + <10050 10280 10326 10276 10266>, + <10044 10285 10321 10281 10280>, + <10039 10298 10323 10288 10285>, + <10038 10310 10324 10308 10284>, + <10045 10309 10318 10321 10285>, + <10054 10304 10304 10319 10295>, + <10056 10302 10291 10314 10309>, + <10056 10312 10297 10316 10321>, + <10058 10329 10320 10326 10335>, + <10070 10353 10339 10334 10341>, + <10090 10386 10349 10339 10346>, + <10111 10400 10358 10343 10354>, + <10138 10396 10373 10334 10340>, + <10157 10388 10395 10289 10270>, + <10169 10381 10400 10243 10212>, + <10178 10372 10354 10197 10174>, + <10183 10364 10306 10161 10144>, + <10190 10352 10304 10160 10141>, + <10194 10341 10307 10170 10149>, + <10185 10335 10310 10181 10158>, + <10169 10332 10311 10196 10169>, + <10165 10332 10314 10216 10183>, + <10168 10343 10327 10238 10202>, + <10171 10357 10356 10267 10226>, + <10175 10368 10381 10298 10253>, + <10180 10376 10405 10333 10288>, + <10183 10384 10422 10367 10326>, + <10186 10393 10431 10393 10358>, + <10189 10403 10438 10416 10387>, + <10187 10410 10442 10437 10405>, + <10181 10419 10455 10461 10418>, + <10175 10423 10465 10476 10426>, + <10164 10407 10466 10476 10430>, + <10152 10385 10468 10474 10428>, + <10142 10373 10453 10473 10402>, + <10064 10371 10455 10479 10389>, + <10173 10285 10486 10517 10402>, + <10003 10290 10490 10530 10416>, + <10151 10295 10531 10566 10477>, + <10255 10515 10588 10612 10540>, + <10077 10376 10556 10524 10421>, + <9948 10240 10480 10454 10314>, + <9854 10122 10384 10398 10256>, + <9640 9998 10319 10342 10182>, + <9440 9830 10255 10261 10065>, + <9440 9830 10255 10261 10065>, + <9440 9830 10255 10261 10065>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19441 19367 19362 19326 19316>, + <19560 19428 19358 19334 19329>, + <19615 19467 19373 19341 19335>, + <19645 19480 19383 19346 19340>, + <19658 19487 19385 19351 19344>, + <19657 19488 19387 19354 19347>, + <19657 19486 19386 19355 19348>, + <19655 19483 19384 19354 19347>, + <19651 19481 19382 19352 19346>, + <19647 19479 19380 19350 19345>, + <19645 19477 19378 19347 19344>, + <19642 19470 19377 19345 19342>, + <19642 19464 19374 19345 19342>, + <19642 19464 19372 19344 19341>, + <19643 19467 19372 19343 19338>, + <19639 19467 19372 19342 19336>, + <19626 19460 19371 19340 19334>, + <19615 19450 19369 19338 19332>, + <19604 19448 19368 19337 19330>, + <19596 19446 19368 19337 19328>, + <19597 19447 19369 19337 19326>, + <19605 19452 19372 19340 19328>, + <19612 19460 19378 19350 19341>, + <19619 19462 19386 19357 19350>, + <19626 19464 19394 19361 19353>, + <19627 19466 19401 19364 19355>, + <19626 19472 19400 19364 19355>, + <19624 19480 19398 19362 19352>, + <19620 19480 19395 19359 19349>, + <19615 19476 19391 19356 19346>, + <19611 19473 19388 19353 19343>, + <19609 19469 19384 19350 19340>, + <19606 19466 19381 19347 19336>, + <19604 19463 19379 19343 19332>, + <19601 19461 19377 19338 19327>, + <19597 19458 19375 19335 19324>, + <19592 19454 19373 19334 19325>, + <19587 19451 19370 19334 19329>, + <19584 19448 19368 19334 19330>, + <19582 19446 19366 19334 19328>, + <19579 19443 19364 19334 19326>, + <19575 19441 19362 19334 19326>, + <19571 19438 19360 19334 19327>, + <19565 19434 19359 19336 19329>, + <19361 19423 19353 19335 19328>, + <19262 19382 19344 19323 19324>, + <19263 19371 19336 19321 19317>, + <19261 19361 19332 19317 19313>, + <19261 19273 19326 19317 19309>, + <19262 19274 19335 19327 19319>, + <19263 19303 19337 19330 19324>, + <19263 19274 19357 19333 19327>, + <19266 19275 19361 19337 19335>, + <19272 19280 19368 19349 19345>, + <19272 19280 19368 19349 19345>, + <19272 19280 19368 19349 19345>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15627 15107 14765 14761 14758>, + <15711 15099 14864 14812 14796>, + <15693 15080 14843 14798 14788>, + <15530 15036 14821 14778 14775>, + <15355 14952 14794 14760 14761>, + <15246 14887 14764 14740 14745>, + <15155 14845 14741 14726 14731>, + <15085 14812 14721 14713 14719>, + <15031 14784 14710 14705 14711>, + <14985 14760 14705 14700 14707>, + <14938 14745 14702 14697 14705>, + <14895 14735 14696 14693 14702>, + <14876 14729 14689 14688 14699>, + <14872 14730 14686 14684 14697>, + <14869 14735 14686 14681 14694>, + <14856 14737 14686 14680 14692>, + <14830 14720 14682 14677 14689>, + <14808 14702 14673 14672 14684>, + <14790 14701 14669 14669 14681>, + <14778 14706 14676 14670 14679>, + <14782 14717 14687 14675 14677>, + <14805 14815 14716 14690 14685>, + <14835 14927 14778 14733 14726>, + <14898 14927 14803 14755 14750>, + <14965 14883 14774 14738 14735>, + <14974 14842 14741 14715 14712>, + <14963 14813 14728 14705 14703>, + <14950 14789 14721 14700 14699>, + <14932 14778 14717 14696 14696>, + <14910 14771 14715 14693 14692>, + <14892 14767 14713 14691 14688>, + <14878 14766 14712 14688 14683>, + <14867 14765 14712 14684 14677>, + <14856 14764 14710 14681 14673>, + <14847 14763 14709 14676 14668>, + <14838 14761 14706 14673 14666>, + <14826 14756 14703 14673 14669>, + <14816 14748 14700 14674 14680>, + <14809 14744 14697 14674 14683>, + <14804 14742 14695 14673 14677>, + <14797 14739 14693 14671 14673>, + <14787 14730 14687 14667 14673>, + <14774 14718 14678 14663 14675>, + <14753 14708 14673 14662 14682>, + <14897 14683 14660 14653 14674>, + <14965 14689 14638 14630 14635>, + <14964 14694 14635 14621 14624>, + <14958 14699 14630 14614 14617>, + <14951 14794 14633 14616 14620>, + <14945 14795 14637 14644 14655>, + <14957 14769 14642 14654 14664>, + <14968 14805 14636 14660 14668>, + <14977 14809 14655 14668 14668>, + <14993 14817 14684 14674 14665>, + <14993 14817 14684 14674 14665>, + <14993 14817 14684 14674 14665>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11983 12740 15393 15537 15330>, + <13357 14824 16249 17310 17529>, + <14286 16482 17811 18377 18523>, + <14945 17642 19175 19223 19510>, + <15486 18555 20024 20275 20513>, + <15957 19327 20723 21346 21540>, + <16368 19918 21568 22345 22519>, + <16781 20541 22514 23454 23469>, + <17187 21683 23120 24074 24236>, + <17674 23224 23449 23971 24698>, + <18442 24060 23713 23757 25052>, + <19483 24549 23914 23816 25554>, + <20437 24925 24207 24637 26312>, + <21361 25257 24451 25542 26851>, + <22105 25909 24697 26092 27021>, + <22478 26475 25087 26614 27131>, + <22735 27141 26348 27394 27470>, + <23076 28081 28954 28566 28331>, + <23809 29715 30229 29356 28825>, + <24938 32251 30431 29724 28646>, + <27176 33544 30446 29885 28135>, + <31932 33025 28578 28445 26783>, + <35226 31860 23567 23249 22747>, + <36819 29994 21621 20580 20432>, + <37874 26035 23092 21806 21763>, + <37147 24128 25214 23841 23948>, + <34993 26078 27156 25488 25430>, + <32825 29127 29386 27105 26647>, + <30980 31187 31134 28441 27481>, + <29376 32887 32400 29515 28206>, + <28873 34208 33430 30375 28775>, + <28786 35400 34311 31101 29161>, + <28801 36250 35051 31824 29873>, + <28836 36325 35497 32045 30283>, + <28862 36122 35938 31861 30590>, + <28907 35854 36221 31646 31106>, + <28980 35186 35497 31570 32686>, + <29132 34291 33694 31549 35494>, + <29670 33796 32315 31543 36261>, + <30652 33516 31332 31469 34185>, + <30992 33114 30388 31412 32325>, + <29938 32130 29262 32046 32870>, + <29033 30867 28327 33225 34089>, + <28928 29512 27958 34867 35083>, + <16971 28826 27177 35407 35456>, + <11113 18542 25875 28236 38118>, + <11084 16735 22486 31621 32274>, + <11037 15601 21798 36765 39261>, + <11035 11499 20071 40032 37713>, + <11055 11574 22201 35765 26327>, + <11017 12415 21829 29484 22484>, + <10951 11419 39496 26044 20817>, + <10890 11348 40899 24307 20580>, + <10822 11392 37952 25288 21070>, + <10822 11392 37952 25288 21070>, + <10822 11392 37952 25288 21070>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15711 15103 14773 14710 14694>, + <15778 15117 14813 14736 14718>, + <15776 15120 14809 14733 14717>, + <15702 15106 14804 14728 14716>, + <15620 15065 14793 14722 14713>, + <15561 15031 14779 14715 14707>, + <15508 15007 14768 14709 14701>, + <15467 14987 14758 14703 14696>, + <15435 14971 14751 14698 14692>, + <15407 14959 14748 14695 14689>, + <15379 14949 14746 14692 14687>, + <15353 14940 14743 14689 14685>, + <15339 14935 14739 14687 14684>, + <15332 14935 14736 14685 14682>, + <15326 14938 14737 14684 14680>, + <15316 14939 14738 14683 14678>, + <15302 14930 14736 14681 14676>, + <15293 14921 14733 14679 14673>, + <15289 14921 14732 14677 14671>, + <15286 14926 14736 14678 14670>, + <15291 14936 14744 14682 14669>, + <15312 14986 14761 14691 14674>, + <15338 15040 14795 14718 14702>, + <15373 15042 14808 14732 14717>, + <15408 15027 14802 14727 14713>, + <15415 15016 14795 14720 14706>, + <15414 15011 14791 14717 14702>, + <15412 15007 14788 14714 14699>, + <15408 15006 14786 14712 14697>, + <15402 15004 14785 14710 14694>, + <15399 15004 14784 14708 14691>, + <15398 15005 14784 14706 14688>, + <15397 15006 14784 14704 14684>, + <15397 15009 14784 14701 14680>, + <15398 15012 14784 14699 14677>, + <15400 15015 14785 14696 14674>, + <15402 15016 14785 14697 14677>, + <15405 15017 14786 14699 14684>, + <15410 15020 14787 14700 14687>, + <15416 15026 14789 14702 14685>, + <15423 15031 14791 14703 14683>, + <15430 15034 14791 14703 14684>, + <15437 15037 14791 14704 14687>, + <15444 15040 14792 14706 14693>, + <15425 15039 14789 14704 14690>, + <15419 15030 14781 14691 14673>, + <15424 15030 14778 14688 14665>, + <15425 15032 14777 14685 14661>, + <15431 15036 14780 14688 14662>, + <15438 15047 14792 14708 14685>, + <15458 15060 14801 14718 14695>, + <15477 15072 14815 14726 14702>, + <15501 15088 14835 14737 14710>, + <15534 15114 14862 14753 14720>, + <15534 15114 14862 14753 14720>, + <15534 15114 14862 14753 14720>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6963 6363 6007 5630 5512 5470>, + <6945 6361 6003 5629 5510 5471>, + <6934 6357 5999 5628 5508 5471>, + <6929 6354 5995 5627 5506 5471>, + <6928 6353 5992 5626 5505 5470>, + <6928 6357 5988 5625 5503 5470>, + <6934 6366 5985 5624 5502 5469>, + <6942 6374 5981 5624 5501 5467>, + <6939 6374 5982 5623 5500 5467>, + <6920 6366 5984 5624 5499 5467>, + <6910 6360 5985 5624 5498 5466>, + <6919 6357 5980 5623 5498 5466>, + <6931 6356 5973 5622 5498 5465>, + <6935 6362 5973 5622 5499 5465>, + <6938 6380 5978 5625 5500 5466>, + <6939 6390 5981 5628 5501 5467>, + <6942 6389 5985 5631 5501 5468>, + <6946 6387 5990 5634 5502 5469>, + <6943 6388 5989 5637 5503 5470>, + <6932 6391 5988 5639 5506 5471>, + <6929 6394 5987 5643 5508 5472>, + <6957 6397 5989 5647 5510 5473>, + <6985 6400 5994 5653 5513 5475>, + <6976 6405 6001 5658 5515 5478>, + <6942 6414 6012 5663 5518 5480>, + <6928 6418 6018 5668 5522 5483>, + <6934 6419 6019 5674 5525 5486>, + <6942 6418 6020 5681 5529 5488>, + <6951 6418 6021 5687 5533 5491>, + <6972 6418 6023 5692 5537 5493>, + <6978 6418 6025 5698 5541 5497>, + <6971 6422 6028 5705 5545 5500>, + <6961 6425 6032 5712 5550 5504>, + <6947 6422 6038 5720 5554 5507>, + <6929 6416 6048 5727 5559 5509>, + <6925 6416 6055 5734 5563 5512>, + <6932 6428 6059 5741 5569 5516>, + <6939 6438 6062 5748 5575 5522>, + <6939 6433 6063 5757 5580 5526>, + <6942 6422 6064 5767 5585 5529>, + <6944 6417 6067 5775 5591 5533>, + <6946 6416 6077 5783 5596 5537>, + <6941 6418 6083 5787 5603 5541>, + <6923 6429 6090 5790 5610 5546>, + <6953 6428 6086 5808 5622 5555>, + <6932 6433 6091 5813 5631 5561>, + <6928 6433 6099 5818 5635 5565>, + <6933 6442 6113 5834 5640 5567>, + <6932 6430 6105 5835 5645 5571>, + <6936 6436 6106 5848 5654 5578>, + <6965 6440 6099 5858 5666 5585>, + <6990 6464 6110 5873 5684 5600>, + <7027 6445 6123 5887 5704 5613>, + <7064 6471 6136 5914 5726 5633>, + <7064 6471 6136 5914 5726 5633>, + <7064 6471 6136 5914 5726 5633>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9643 10780 11037 11216 11097 11009>, + <9653 10747 10993 11177 11076 11016>, + <9867 10710 10945 11129 11053 11018>, + <10082 10673 10898 11080 11031 11018>, + <10246 10642 10860 11037 11010 11015>, + <10308 10624 10837 11007 10992 11010>, + <10281 10616 10826 10987 10977 10981>, + <10241 10610 10820 10968 10962 10937>, + <10275 10600 10816 10953 10942 10920>, + <10440 10586 10802 10939 10913 10908>, + <10531 10580 10792 10927 10894 10901>, + <10522 10610 10786 10915 10881 10897>, + <10502 10665 10780 10900 10869 10890>, + <10430 10721 10797 10878 10869 10877>, + <10226 10789 10873 10846 10876 10849>, + <10115 10817 10940 10834 10878 10831>, + <9949 10805 10988 10876 10871 10840>, + <9749 10791 11021 10939 10863 10860>, + <9704 10791 11014 10991 10869 10866>, + <9683 10795 10979 11041 10898 10870>, + <9677 10801 10965 11063 10936 10877>, + <9676 10808 10997 11078 11004 10940>, + <9676 10820 11042 11093 11066 11026>, + <9674 10836 11062 11099 11074 11055>, + <9670 10861 11077 11105 11063 11066>, + <9667 10915 11082 11111 11064 11068>, + <9665 11341 11085 11126 11092 11072>, + <9663 11748 11091 11149 11125 11083>, + <9661 11516 11099 11179 11148 11096>, + <9659 10816 11110 11217 11174 11118>, + <9658 10376 11118 11236 11190 11131>, + <9657 10155 11117 11245 11208 11140>, + <9656 10000 11109 11252 11224 11152>, + <9655 9892 11094 11259 11233 11175>, + <9654 9812 11060 11260 11250 11208>, + <9654 9762 11020 11250 11255 11218>, + <9653 9725 10915 11227 11244 11186>, + <9653 9701 10784 11207 11227 11146>, + <9653 9688 10695 11192 11211 11135>, + <9652 9678 10615 11172 11194 11131>, + <9652 9671 10480 11143 11192 11126>, + <9652 9665 10201 11106 11216 11112>, + <9651 9661 10108 11076 11220 11105>, + <9651 9658 10159 11042 11183 11120>, + <9651 9656 9965 10929 11157 11073>, + <9651 9654 9856 10889 11090 11023>, + <9651 9653 9796 10823 11057 10968>, + <9650 9653 9741 10794 11051 10955>, + <9650 9652 9696 10740 11029 10918>, + <9650 9652 9680 10652 10968 10907>, + <9650 9651 9670 10540 10916 10868>, + <9649 9651 9663 10397 10801 10776>, + <9648 9650 9657 10262 10712 10696>, + <9648 9650 9654 10448 10584 10596>, + <9648 9650 9654 10448 10584 10596>, + <9648 9650 9654 10448 10584 10596>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13491 13351 13296 13276 13275 13272>, + <13481 13348 13297 13278 13275 13272>, + <13476 13346 13298 13280 13275 13273>, + <13476 13347 13300 13282 13276 13274>, + <13480 13349 13302 13283 13276 13274>, + <13486 13352 13303 13283 13276 13275>, + <13513 13358 13303 13283 13276 13275>, + <13546 13363 13304 13283 13276 13275>, + <13543 13365 13306 13283 13277 13275>, + <13505 13365 13310 13284 13278 13275>, + <13476 13366 13315 13285 13278 13276>, + <13465 13371 13319 13285 13278 13276>, + <13456 13377 13322 13285 13278 13276>, + <13446 13376 13322 13286 13278 13276>, + <13434 13369 13321 13288 13279 13277>, + <13428 13363 13320 13290 13279 13277>, + <13428 13359 13318 13291 13280 13278>, + <13428 13354 13316 13292 13282 13278>, + <13414 13349 13313 13292 13283 13279>, + <13377 13343 13308 13291 13283 13281>, + <13356 13338 13304 13290 13284 13281>, + <13351 13336 13301 13286 13280 13278>, + <13349 13333 13299 13283 13276 13274>, + <13354 13323 13298 13282 13275 13273>, + <13374 13301 13297 13281 13275 13273>, + <13397 13289 13297 13281 13275 13273>, + <13424 13273 13297 13280 13275 13273>, + <13457 13259 13297 13280 13275 13273>, + <13494 13259 13296 13280 13275 13273>, + <13537 13259 13296 13280 13275 13273>, + <13586 13260 13295 13280 13274 13272>, + <13644 13261 13291 13280 13274 13272>, + <13708 13262 13288 13279 13274 13272>, + <13777 13264 13289 13279 13274 13272>, + <13853 13268 13293 13279 13273 13272>, + <13939 13274 13295 13279 13273 13272>, + <14040 13285 13294 13279 13274 13272>, + <14153 13299 13292 13280 13274 13273>, + <14276 13317 13292 13279 13274 13273>, + <14412 13340 13293 13279 13274 13273>, + <14564 13372 13291 13279 13274 13273>, + <14738 13423 13271 13280 13275 13273>, + <14925 13493 13262 13280 13275 13273>, + <15128 13598 13261 13280 13274 13273>, + <15354 13729 13263 13279 13275 13274>, + <15547 13885 13266 13284 13276 13275>, + <15700 13996 13270 13284 13277 13277>, + <15883 14139 13280 13288 13279 13277>, + <16098 14305 13309 13290 13280 13277>, + <16340 14489 13343 13292 13280 13276>, + <16656 14726 13389 13294 13281 13277>, + <17634 15025 13481 13299 13283 13278>, + <19636 15401 13635 13309 13286 13283>, + <22946 16005 13899 13335 13293 13287>, + <22946 16005 13899 13335 13293 13287>, + <22946 16005 13899 13335 13293 13287>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <16973 16623 16526 16458 16452 16456>, + <16999 16632 16525 16457 16452 16456>, + <17030 16641 16525 16457 16452 16456>, + <17060 16652 16526 16457 16452 16456>, + <17082 16663 16528 16457 16452 16456>, + <17089 16674 16531 16457 16452 16456>, + <17077 16687 16535 16459 16452 16456>, + <17059 16701 16539 16462 16453 16456>, + <17098 16711 16545 16465 16453 16456>, + <17276 16720 16552 16468 16454 16457>, + <17396 16735 16563 16473 16455 16457>, + <17426 16824 16584 16480 16458 16458>, + <17443 16930 16612 16490 16461 16460>, + <17384 16951 16638 16498 16465 16462>, + <17155 16958 16663 16504 16470 16465>, + <17028 16959 16695 16515 16476 16469>, + <17014 16934 16758 16539 16486 16475>, + <17005 16887 16816 16571 16502 16486>, + <16980 16831 16800 16609 16530 16506>, + <16933 16754 16713 16656 16576 16541>, + <16886 16692 16635 16664 16593 16558>, + <16837 16644 16572 16570 16535 16521>, + <16797 16610 16522 16475 16468 16470>, + <16783 16607 16507 16460 16455 16458>, + <16776 16623 16498 16454 16451 16455>, + <16770 16632 16494 16453 16449 16454>, + <16765 16645 16493 16454 16449 16453>, + <16761 16659 16493 16455 16448 16453>, + <16761 16662 16492 16457 16449 16453>, + <16761 16663 16493 16461 16452 16454>, + <16762 16667 16493 16466 16456 16455>, + <16764 16677 16492 16474 16464 16461>, + <16767 16687 16492 16479 16471 16470>, + <16770 16690 16494 16478 16474 16476>, + <16775 16693 16500 16474 16474 16483>, + <16778 16693 16505 16467 16471 16482>, + <16782 16689 16508 16455 16458 16467>, + <16784 16685 16510 16448 16447 16453>, + <16783 16685 16511 16449 16450 16455>, + <16781 16683 16512 16452 16456 16465>, + <16779 16681 16517 16455 16459 16471>, + <16770 16670 16558 16460 16458 16470>, + <16768 16654 16579 16464 16456 16468>, + <16776 16634 16584 16465 16448 16452>, + <16801 16629 16593 16474 16448 16444>, + <16819 16647 16617 16493 16467 16470>, + <16856 16669 16641 16507 16488 16496>, + <16905 16699 16672 16536 16520 16521>, + <16944 16754 16675 16565 16529 16536>, + <16949 16780 16683 16555 16503 16488>, + <16941 16767 16681 16554 16495 16479>, + <17078 16794 16695 16582 16508 16485>, + <17565 16874 16751 16646 16545 16510>, + <19162 17124 16888 16859 16671 16581>, + <19162 17124 16888 16859 16671 16581>, + <19162 17124 16888 16859 16671 16581>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <11501 16034 14767 13793 19407 15565>, + <11603 15822 15156 15683 19413 16938>, + <11875 15497 15333 17017 19416 18058>, + <12285 15152 15352 17855 19416 18894>, + <12803 14881 15266 18259 19413 19416>, + <13403 14778 15128 18284 19405 19590>, + <14551 14807 14793 17405 18933 19301>, + <15710 14848 14419 16236 18269 18809>, + <15425 14688 14471 15943 18195 18561>, + <13533 13983 14951 15873 18327 18385>, + <12513 13556 15219 15744 18394 18198>, + <13803 13493 14892 15050 17832 17726>, + <15473 13460 14418 14306 16921 17099>, + <15394 13744 14254 14381 16318 16821>, + <14258 14851 14181 14869 15815 16673>, + <13562 15643 14199 15070 15556 16471>, + <13428 15965 14556 14786 15450 15954>, + <13274 16199 15160 14490 15387 15465>, + <12936 16398 15863 14755 15446 15449>, + <12423 16588 16824 15793 15777 15650>, + <11952 16732 17460 16919 16267 15980>, + <11476 16879 17821 18292 17600 16933>, + <11117 16964 18087 19430 19112 18163>, + <11033 16245 18242 19821 19838 19000>, + <11009 14141 18325 19945 20331 19696>, + <11024 12876 18331 19914 20756 20093>, + <11056 11798 18517 19842 21457 20297>, + <11084 10948 18759 19785 21999 20418>, + <11132 10879 18828 19716 21658 20286>, + <11232 10862 18868 19575 20509 19563>, + <11269 10868 18768 19409 19604 18813>, + <11345 11005 17096 19184 18920 18072>, + <11421 11165 15478 19049 18499 17524>, + <11456 11261 16038 19331 18661 17776>, + <11520 11350 17571 20041 19331 19034>, + <11543 11387 18037 20606 20274 20444>, + <11613 11553 17270 21412 23017 22060>, + <11678 11697 16300 21789 25208 23225>, + <11640 11640 15861 20914 24442 22731>, + <11545 11511 15530 19618 22425 21047>, + <11506 11463 14798 19274 21559 20283>, + <11457 11412 12697 19217 21506 20308>, + <11415 11500 11853 18717 21719 20486>, + <11368 11742 11779 17923 22443 22679>, + <11364 11818 11639 16687 21754 22971>, + <11379 11581 11310 17555 18408 18279>, + <11464 11576 11214 16686 17313 17483>, + <11729 11969 11315 17033 16467 15409>, + <12142 11899 11677 16717 15881 14424>, + <11979 11895 11966 17491 17177 15372>, + <11649 12007 11983 17478 18213 16253>, + <11017 11938 11964 17190 17836 15973>, + <10265 11845 11923 16780 17343 17751>, + <9626 11312 12185 16916 17400 17911>, + <9626 11312 12185 16916 17400 17911>, + <9626 11312 12185 16916 17400 17911>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6106 5405 5178 5064 5046 5042>, + <6097 5401 5177 5064 5046 5042>, + <6092 5400 5176 5065 5046 5042>, + <6089 5400 5176 5066 5047 5043>, + <6088 5401 5176 5067 5047 5044>, + <6088 5403 5176 5067 5047 5044>, + <6090 5407 5176 5068 5047 5044>, + <6094 5413 5177 5068 5047 5044>, + <6102 5416 5178 5069 5047 5044>, + <6117 5418 5182 5071 5048 5044>, + <6129 5422 5187 5073 5049 5045>, + <6135 5450 5195 5075 5050 5045>, + <6139 5483 5204 5078 5051 5046>, + <6123 5488 5211 5081 5052 5047>, + <6059 5490 5218 5085 5054 5048>, + <6027 5490 5226 5089 5056 5050>, + <6030 5484 5243 5097 5060 5052>, + <6034 5472 5259 5107 5066 5055>, + <6032 5457 5253 5118 5075 5062>, + <6027 5435 5225 5131 5088 5073>, + <6025 5421 5201 5133 5093 5078>, + <6031 5414 5182 5104 5074 5065>, + <6042 5409 5169 5075 5052 5048>, + <6061 5410 5167 5071 5048 5044>, + <6095 5412 5166 5069 5047 5043>, + <6132 5415 5166 5069 5046 5042>, + <6169 5421 5168 5070 5047 5042>, + <6210 5431 5171 5071 5047 5042>, + <6254 5444 5175 5073 5048 5043>, + <6302 5464 5178 5075 5049 5043>, + <6354 5486 5181 5078 5050 5044>, + <6411 5511 5183 5081 5052 5046>, + <6471 5539 5185 5083 5055 5048>, + <6535 5569 5192 5084 5056 5050>, + <6602 5603 5205 5084 5056 5053>, + <6677 5640 5216 5084 5056 5053>, + <6759 5681 5225 5083 5053 5049>, + <6849 5727 5234 5083 5051 5046>, + <6948 5778 5244 5084 5052 5047>, + <7058 5835 5257 5087 5055 5050>, + <7178 5899 5273 5091 5057 5052>, + <7313 5971 5295 5095 5058 5052>, + <7461 6060 5322 5099 5058 5052>, + <7625 6170 5355 5104 5056 5049>, + <7801 6295 5404 5112 5059 5048>, + <7952 6438 5465 5127 5066 5057>, + <8083 6542 5513 5135 5074 5067>, + <8233 6666 5574 5150 5086 5075>, + <8404 6813 5646 5166 5090 5080>, + <8597 6972 5725 5172 5084 5066>, + <8831 7159 5819 5184 5085 5065>, + <9655 7408 5955 5214 5093 5070>, + <11356 7725 6149 5262 5110 5083>, + <14260 8288 6430 5374 5157 5109>, + <14260 8288 6430 5374 5157 5109>, + <14260 8288 6430 5374 5157 5109>; + }; +}; diff --git a/qcom/qg-batterydata-mlp356477-2800mah.dtsi b/qcom/qg-batterydata-mlp356477-2800mah.dtsi new file mode 100644 index 00000000..c64ba574 --- /dev/null +++ b/qcom/qg-batterydata-mlp356477-2800mah.dtsi @@ -0,0 +1,1028 @@ +qcom,mlp356477_2800mah { + /* mlp356477_2800mah_averaged_MasterSlave_Mar13th2018 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,fastchg-current-ma = <4200>; + qcom,batt-id-kohm = <82>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "mlp356477_2800mah_averaged_MasterSlave_Mar13th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 150 560000 + 151 450 4200000 + 451 550 2380000>; + qcom,jeita-fv-ranges = <0 150 4150000 + 151 450 4400000 + 451 550 4150000>; + + /* COOL = 15 DegC, WARM = 45 DegC */ + qcom,jeita-soft-thresholds = <0x4621 0x20b8>; + /* COLD = 0 DegC, HOT = 55 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <2715 2788 2861 2898 2908>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <2864 2846 2860 2868 2865 2865>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43494 43682 43812 43865 43879>, + <43243 43420 43582 43645 43659>, + <42984 43174 43350 43418 43434>, + <42737 42940 43115 43191 43208>, + <42506 42710 42878 42958 42978>, + <42287 42479 42641 42722 42746>, + <42087 42250 42407 42489 42514>, + <41903 42027 42175 42255 42281>, + <41709 41807 41948 42023 42050>, + <41489 41592 41723 41794 41822>, + <41265 41381 41502 41568 41596>, + <41069 41176 41286 41348 41374>, + <40898 40982 41074 41131 41155>, + <40720 40799 40871 40921 40942>, + <40501 40613 40673 40716 40735>, + <40269 40405 40482 40518 40534>, + <40088 40193 40295 40329 40343>, + <39955 40022 40116 40148 40162>, + <39834 39894 39952 39975 39988>, + <39708 39765 39807 39818 39827>, + <39583 39577 39645 39659 39667>, + <39447 39345 39420 39461 39475>, + <39277 39148 39173 39221 39239>, + <39089 38991 38991 39014 39028>, + <38930 38860 38851 38860 38868>, + <38794 38758 38733 38728 38732>, + <38683 38676 38628 38611 38612>, + <38607 38602 38535 38507 38505>, + <38548 38529 38451 38414 38409>, + <38501 38462 38373 38327 38317>, + <38466 38407 38305 38251 38234>, + <38437 38360 38245 38182 38160>, + <38405 38317 38193 38121 38092>, + <38366 38277 38147 38067 38030>, + <38329 38240 38109 38022 37980>, + <38300 38203 38069 37977 37929>, + <38273 38170 38027 37921 37863>, + <38236 38130 37980 37857 37784>, + <38162 38057 37912 37781 37700>, + <38062 37946 37816 37690 37609>, + <37947 37830 37704 37585 37507>, + <37801 37713 37578 37463 37382>, + <37644 37575 37436 37322 37239>, + <37473 37394 37270 37162 37082>, + <37320 37251 37129 37032 36959>, + <37220 37161 37058 36960 36899>, + <37185 37129 37033 36942 36880>, + <37156 37103 37014 36927 36865>, + <37120 37070 36988 36902 36835>, + <37014 36957 36885 36755 36652>, + <36682 36593 36544 36398 36287>, + <36204 36109 36077 35921 35807>, + <35597 35486 35476 35307 35181>, + <34771 34630 34656 34460 34321>, + <33460 33262 33379 33128 32955>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43865 43850 43830 43805 43740 43725>, + <43432 43429 43514 43528 43481 43467>, + <43037 43064 43219 43264 43228 43216>, + <42685 42767 42948 43012 42983 42973>, + <42369 42526 42700 42773 42744 42738>, + <42075 42296 42458 42537 42509 42505>, + <41776 42059 42213 42303 42277 42272>, + <41517 41822 41972 42071 42047 42041>, + <41353 41571 41739 41843 41820 41814>, + <41239 41298 41515 41619 41595 41589>, + <41095 41069 41297 41398 41374 41368>, + <40895 40928 41088 41181 41158 41151>, + <40650 40808 40884 40967 40946 40938>, + <40329 40611 40677 40763 40742 40734>, + <39941 40284 40461 40566 40541 40534>, + <39654 39989 40259 40373 40348 40342>, + <39456 39811 40087 40180 40164 40158>, + <39278 39662 39920 39993 39985 39980>, + <39086 39459 39722 39821 39814 39808>, + <38900 39184 39492 39664 39651 39646>, + <38740 38924 39264 39483 39469 39466>, + <38598 38721 39048 39237 39230 39230>, + <38480 38546 38846 38982 38986 38989>, + <38386 38403 38678 38799 38809 38813>, + <38308 38282 38535 38654 38669 38674>, + <38240 38189 38406 38530 38547 38552>, + <38182 38125 38286 38419 38438 38442>, + <38127 38075 38179 38320 38341 38343>, + <38076 38030 38090 38229 38250 38250>, + <38028 37992 38012 38144 38166 38164>, + <37978 37955 37949 38066 38089 38086>, + <37927 37916 37900 37993 38019 38016>, + <37875 37875 37857 37925 37953 37949>, + <37820 37832 37817 37860 37884 37875>, + <37763 37788 37781 37801 37812 37795>, + <37699 37738 37740 37738 37728 37702>, + <37630 37680 37688 37671 37625 37587>, + <37555 37613 37625 37600 37519 37469>, + <37475 37537 37552 37525 37430 37374>, + <37392 37448 37465 37446 37352 37292>, + <37308 37349 37363 37353 37263 37200>, + <37222 37237 37238 37238 37151 37088>, + <37133 37114 37101 37106 37022 36960>, + <37035 36989 36957 36952 36870 36813>, + <36935 36875 36859 36862 36807 36758>, + <36817 36792 36792 36828 36785 36734>, + <36752 36754 36762 36812 36769 36719>, + <36667 36707 36710 36780 36736 36687>, + <36541 36633 36613 36721 36656 36581>, + <36342 36472 36411 36517 36379 36276>, + <36024 36149 36031 36113 35946 35829>, + <35575 35650 35485 35584 35386 35258>, + <34953 34964 34771 34884 34643 34500>, + <34073 34007 33739 33902 33598 33440>, + <32647 32474 32144 32393 32025 31829>, + <30018 28051 26513 28737 27554 26991>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14442 13243 12339 11979 11839>, + <14411 13218 12328 11916 11773>, + <14392 13199 12294 11893 11756>, + <14384 13180 12273 11879 11745>, + <14381 13174 12263 11870 11738>, + <14377 13179 12257 11863 11735>, + <14369 13182 12253 11858 11731>, + <14358 13175 12250 11851 11726>, + <14349 13158 12248 11847 11722>, + <14339 13146 12242 11845 11720>, + <14332 13143 12237 11845 11719>, + <14327 13144 12237 11844 11718>, + <14321 13142 12238 11840 11716>, + <14313 13135 12234 11837 11715>, + <14306 13128 12222 11835 11714>, + <14299 13120 12215 11834 11714>, + <14293 13113 12211 11833 11713>, + <14293 13111 12203 11830 11714>, + <14297 13119 12202 11828 11715>, + <14304 13129 12210 11831 11716>, + <14312 13133 12215 11837 11718>, + <14318 13130 12221 11841 11721>, + <14319 13125 12230 11843 11726>, + <14320 13135 12234 11846 11730>, + <14324 13151 12236 11852 11734>, + <14340 13158 12238 11860 11737>, + <14358 13165 12247 11865 11741>, + <14373 13167 12258 11870 11747>, + <14389 13165 12260 11873 11752>, + <14394 13167 12258 11877 11757>, + <14373 13169 12256 11880 11760>, + <14334 13168 12253 11886 11764>, + <14321 13167 12247 11892 11768>, + <14348 13170 12248 11897 11772>, + <14378 13177 12260 11901 11778>, + <14371 13182 12271 11905 11783>, + <14343 13188 12277 11910 11788>, + <14331 13194 12283 11917 11792>, + <14346 13205 12290 11924 11797>, + <14369 13219 12300 11931 11803>, + <14389 13228 12307 11937 11809>, + <14412 13237 12311 11941 11815>, + <14410 13245 12315 11945 11820>, + <14367 13259 12315 11949 11823>, + <14429 13239 12311 11954 11824>, + <14440 13243 12333 11959 11830>, + <14452 13241 12320 11961 11828>, + <14443 13243 12329 11964 11831>, + <14484 13241 12332 11968 11836>, + <14448 13263 12343 11977 11845>, + <14473 13293 12346 11988 11856>, + <14501 13300 12357 12000 11864>, + <14521 13333 12374 12015 11879>, + <14603 13373 12420 12034 11897>, + <14603 13373 12420 12034 11897>, + <14603 13373 12420 12034 11897>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9070 11213 10264 10349 10299>, + <9403 10211 10276 10386 10313>, + <9826 10116 10342 10430 10322>, + <9983 10114 10362 10447 10350>, + <9978 10115 10368 10437 10342>, + <9967 10120 10372 10407 10282>, + <9846 10126 10371 10393 10237>, + <9534 10132 10368 10388 10217>, + <9372 10137 10365 10382 10206>, + <9574 10141 10365 10378 10208>, + <9873 10143 10365 10386 10216>, + <9940 10145 10357 10384 10231>, + <9908 10147 10346 10370 10273>, + <9890 10148 10344 10357 10310>, + <9864 10149 10352 10353 10325>, + <9749 10147 10354 10353 10336>, + <9714 10144 10347 10355 10342>, + <10069 10146 10343 10360 10343>, + <10530 10156 10344 10366 10344>, + <10637 10166 10343 10378 10353>, + <10631 10154 10344 10396 10363>, + <10605 10119 10374 10405 10360>, + <10392 10103 10415 10412 10326>, + <10061 10118 10414 10414 10294>, + <9958 10135 10371 10402 10266>, + <9962 10132 10339 10387 10241>, + <9968 10117 10335 10377 10241>, + <9971 10107 10337 10360 10253>, + <9975 10109 10342 10353 10270>, + <9977 10112 10351 10373 10299>, + <9855 10116 10359 10397 10330>, + <9628 10123 10362 10398 10343>, + <9563 10131 10365 10389 10349>, + <9597 10143 10370 10392 10366>, + <9647 10159 10379 10443 10415>, + <9714 10166 10389 10499 10464>, + <9809 10169 10397 10520 10486>, + <9844 10172 10405 10533 10511>, + <9756 10186 10432 10548 10531>, + <9631 10212 10505 10586 10563>, + <9541 10225 10551 10621 10587>, + <9445 10161 10538 10637 10540>, + <9378 10144 10527 10646 10468>, + <9335 10322 10539 10611 10495>, + <9269 13378 10554 10627 10491>, + <9218 14361 10475 10629 10534>, + <9220 14794 10469 10642 10588>, + <9212 15070 10496 10651 10586>, + <9188 13785 10469 10739 10647>, + <9170 13219 10622 10694 10458>, + <9151 12652 10655 10557 10325>, + <9135 12236 10610 10495 10272>, + <9116 11644 10496 10432 10195>, + <9081 11027 10456 10300 10139>, + <9081 11027 10456 10300 10139>, + <9081 11027 10456 10300 10139>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19308 19258 19367 19369 19345>, + <19567 19611 19463 19395 19370>, + <19850 19705 19512 19411 19381>, + <19967 19740 19520 19416 19385>, + <19987 19749 19515 19414 19384>, + <19996 19735 19507 19405 19379>, + <19860 19713 19499 19400 19373>, + <19484 19698 19492 19395 19369>, + <19288 19687 19483 19391 19365>, + <19508 19679 19473 19388 19362>, + <19829 19673 19467 19382 19358>, + <19858 19667 19463 19378 19357>, + <19678 19660 19461 19372 19355>, + <19567 19648 19461 19369 19353>, + <19627 19641 19463 19369 19353>, + <19647 19646 19465 19368 19355>, + <19577 19654 19458 19367 19355>, + <19415 19653 19447 19366 19345>, + <19268 19631 19443 19365 19337>, + <19258 19613 19443 19365 19337>, + <19258 19623 19446 19366 19337>, + <19260 19652 19459 19374 19342>, + <19450 19665 19480 19393 19364>, + <19797 19666 19494 19403 19379>, + <19919 19667 19506 19402 19379>, + <19924 19671 19511 19400 19378>, + <19927 19681 19507 19400 19374>, + <19922 19686 19499 19400 19366>, + <19906 19684 19492 19399 19360>, + <19891 19680 19487 19397 19359>, + <19798 19673 19482 19393 19359>, + <19639 19661 19476 19390 19359>, + <19579 19650 19470 19386 19357>, + <19566 19644 19465 19382 19355>, + <19553 19639 19460 19380 19352>, + <19468 19636 19457 19378 19348>, + <19316 19630 19455 19375 19346>, + <19261 19624 19453 19373 19344>, + <19262 19618 19450 19371 19343>, + <19263 19609 19443 19369 19345>, + <19264 19576 19437 19368 19347>, + <19267 19367 19435 19368 19350>, + <19269 19261 19432 19367 19353>, + <19270 19260 19421 19365 19353>, + <19274 19257 19413 19361 19354>, + <19278 19257 19368 19354 19332>, + <19278 19257 19367 19346 19332>, + <19279 19257 19362 19331 19323>, + <19282 19257 19368 19326 19327>, + <19284 19257 19354 19338 19350>, + <19287 19257 19361 19346 19348>, + <19290 19257 19368 19356 19347>, + <19295 19257 19370 19353 19356>, + <19308 19258 19392 19382 19373>, + <19308 19258 19392 19382 19373>, + <19308 19258 19392 19382 19373>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16598 15992 15337 14972 14879>, + <16815 16035 15386 15059 14940>, + <16561 15923 15277 14982 14899>, + <16283 15657 15173 14901 14842>, + <15982 15436 15082 14879 14824>, + <15774 15304 15020 14868 14816>, + <15800 15207 14988 14856 14809>, + <15941 15154 14966 14843 14802>, + <16005 15119 14946 14830 14794>, + <15750 15094 14928 14818 14785>, + <15383 15076 14912 14807 14775>, + <15316 15063 14897 14797 14766>, + <15433 15048 14884 14788 14757>, + <15501 15033 14874 14778 14748>, + <15463 15025 14866 14769 14737>, + <15509 15037 14860 14760 14725>, + <15596 15057 14852 14751 14718>, + <15677 15056 14841 14742 14715>, + <15729 15002 14835 14738 14712>, + <15708 14951 14832 14736 14709>, + <15684 15017 14833 14735 14707>, + <15650 15207 14923 14756 14718>, + <15508 15302 15068 14837 14777>, + <15298 15313 15091 14879 14814>, + <15235 15319 15040 14870 14809>, + <15282 15294 14989 14855 14800>, + <15330 15200 14962 14841 14793>, + <15320 15131 14943 14826 14787>, + <15270 15105 14932 14814 14780>, + <15232 15088 14926 14805 14771>, + <15276 15076 14923 14798 14761>, + <15373 15065 14921 14794 14754>, + <15397 15057 14920 14791 14747>, + <15385 15051 14919 14789 14742>, + <15376 15043 14916 14787 14738>, + <15430 15036 14914 14786 14736>, + <15544 15016 14915 14794 14745>, + <15577 14998 14918 14811 14767>, + <15550 14991 14917 14816 14774>, + <15520 14987 14909 14811 14768>, + <15502 14998 14896 14803 14760>, + <15491 15139 14873 14788 14752>, + <15475 15211 14850 14774 14747>, + <15445 15195 14842 14774 14750>, + <15345 15130 14813 14764 14741>, + <15318 15079 14802 14736 14721>, + <15308 15066 14777 14720 14700>, + <15301 15057 14757 14705 14684>, + <15285 15045 14739 14698 14668>, + <15274 15053 14775 14717 14688>, + <15294 15076 14782 14719 14696>, + <15311 15080 14778 14712 14701>, + <15326 15091 14779 14719 14701>, + <15354 15108 14768 14706 14703>, + <15354 15108 14768 14706 14703>, + <15354 15108 14768 14706 14703>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <10764 10957 12110 13794 13670>, + <11745 12925 13686 14768 14977>, + <12716 14010 14746 16056 16445>, + <13404 14718 15521 16744 17361>, + <13905 15321 16180 16789 17415>, + <14200 15933 16545 16568 17166>, + <13611 16455 16653 16420 16940>, + <11869 16730 16710 16364 16838>, + <10978 16895 16699 16401 16763>, + <12521 17062 16594 16402 16659>, + <14783 17315 16549 16292 16587>, + <15011 17507 16656 16178 16634>, + <13819 17490 16845 16003 16770>, + <13134 17527 17100 15977 16943>, + <13823 17638 17538 16159 17435>, + <14192 17626 17786 16425 18421>, + <13660 17482 17557 16723 18632>, + <12194 17384 17254 17131 17493>, + <10877 17447 17366 17305 16542>, + <10795 17704 18253 17609 16717>, + <10808 18910 18937 18108 17070>, + <10857 21136 18167 17900 17037>, + <13850 21892 16713 16569 16529>, + <19285 19957 16394 15708 16174>, + <21102 17736 16736 15560 16006>, + <20977 17560 17186 15557 15832>, + <20752 18050 17734 15845 15773>, + <20272 18693 18431 16567 15708>, + <19413 19705 19132 17289 15707>, + <18772 20743 19927 17959 16182>, + <17386 21034 20581 18611 16967>, + <15327 21059 21018 19179 17620>, + <14631 21034 21355 19699 18403>, + <14512 21133 21507 20256 19056>, + <14338 21373 21604 21000 19675>, + <13329 21460 21643 21494 20064>, + <11563 21322 21601 20994 19488>, + <10927 21163 21493 19730 18023>, + <10937 21134 21270 19156 17559>, + <10948 21040 20651 18991 17865>, + <10942 20318 20135 18929 18319>, + <10912 14582 19994 18903 18925>, + <10885 11608 19761 18788 19444>, + <10861 11587 18126 17802 18686>, + <10871 11314 17978 17266 18426>, + <10857 11130 15054 17271 15914>, + <10841 11088 15214 17078 16658>, + <10831 11067 15184 16484 17071>, + <10841 11046 15966 16365 19357>, + <10877 11142 14378 15551 19427>, + <10922 11156 14140 15626 17699>, + <10887 11109 14272 16679 16814>, + <10848 11069 14202 15606 17668>, + <10790 10995 15166 19180 19716>, + <10790 10995 15166 19180 19716>, + <10790 10995 15166 19180 19716>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <17029 15901 15123 14807 14723>, + <17156 16022 15165 14844 14750>, + <17081 15990 15131 14815 14734>, + <16977 15851 15090 14780 14711>, + <16818 15720 15039 14766 14700>, + <16645 15630 15000 14756 14693>, + <16486 15560 14978 14746 14686>, + <16331 15519 14962 14737 14680>, + <16255 15490 14945 14728 14674>, + <16244 15468 14929 14720 14668>, + <16238 15452 14916 14712 14662>, + <16217 15438 14905 14704 14656>, + <16172 15422 14897 14697 14651>, + <16139 15401 14891 14691 14646>, + <16146 15390 14887 14686 14642>, + <16166 15395 14883 14681 14638>, + <16163 15403 14876 14677 14633>, + <16120 15402 14866 14672 14627>, + <16076 15372 14862 14670 14622>, + <16063 15345 14862 14670 14621>, + <16057 15380 14865 14671 14621>, + <16055 15480 14915 14684 14629>, + <16092 15533 14991 14732 14668>, + <16168 15543 15006 14757 14692>, + <16218 15549 14992 14753 14691>, + <16251 15541 14976 14746 14687>, + <16270 15511 14964 14741 14683>, + <16266 15488 14954 14735 14676>, + <16246 15479 14948 14730 14671>, + <16227 15473 14944 14726 14666>, + <16204 15467 14942 14722 14662>, + <16176 15459 14941 14719 14659>, + <16164 15454 14939 14716 14657>, + <16159 15453 14938 14715 14654>, + <16154 15453 14937 14714 14651>, + <16145 15453 14936 14714 14649>, + <16133 15450 14939 14717 14652>, + <16130 15447 14943 14725 14662>, + <16133 15449 14943 14727 14665>, + <16139 15454 14940 14725 14664>, + <16147 15454 14936 14723 14663>, + <16161 15429 14929 14718 14662>, + <16171 15417 14922 14712 14662>, + <16178 15424 14918 14713 14664>, + <16162 15408 14909 14708 14663>, + <16165 15399 14883 14694 14643>, + <16168 15398 14875 14684 14633>, + <16172 15401 14867 14670 14622>, + <16179 15405 14866 14665 14618>, + <16193 15425 14881 14682 14641>, + <16228 15451 14892 14690 14645>, + <16262 15468 14902 14695 14650>, + <16300 15497 14912 14700 14657>, + <16361 15535 14930 14716 14672>, + <16361 15535 14930 14716 14672>, + <16361 15535 14930 14716 14672>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7929 6704 6050 5566 5322 5235>, + <8028 6701 6050 5560 5320 5234>, + <8101 6693 6051 5554 5318 5233>, + <8151 6684 6051 5548 5316 5231>, + <8179 6676 6052 5543 5313 5230>, + <8186 6673 6053 5540 5311 5228>, + <8157 6667 6054 5539 5308 5225>, + <8120 6659 6054 5538 5305 5222>, + <8110 6663 6055 5536 5302 5222>, + <8104 6693 6056 5529 5299 5222>, + <8099 6717 6055 5525 5298 5222>, + <8120 6716 6050 5525 5297 5220>, + <8146 6707 6044 5526 5296 5217>, + <8147 6706 6044 5528 5295 5216>, + <8147 6707 6049 5533 5293 5217>, + <8146 6709 6052 5536 5291 5217>, + <8135 6705 6053 5534 5290 5219>, + <8119 6699 6055 5532 5288 5221>, + <8100 6700 6057 5532 5289 5221>, + <8079 6708 6062 5531 5290 5220>, + <8070 6715 6065 5531 5292 5219>, + <8070 6712 6067 5532 5294 5220>, + <8076 6706 6071 5532 5296 5222>, + <8117 6703 6071 5532 5297 5223>, + <8170 6702 6070 5532 5298 5225>, + <8167 6702 6069 5532 5299 5227>, + <8118 6700 6068 5535 5301 5229>, + <8084 6699 6065 5539 5305 5232>, + <8087 6697 6062 5540 5309 5236>, + <8100 6691 6059 5541 5311 5240>, + <8092 6688 6059 5542 5314 5243>, + <8059 6691 6063 5546 5317 5244>, + <8043 6695 6069 5550 5320 5245>, + <8027 6693 6072 5553 5324 5247>, + <8011 6677 6077 5556 5329 5251>, + <8021 6667 6080 5558 5333 5255>, + <8050 6679 6081 5563 5336 5258>, + <8082 6697 6082 5568 5339 5261>, + <8123 6698 6085 5570 5342 5263>, + <8148 6684 6094 5571 5348 5265>, + <8101 6675 6101 5572 5352 5268>, + <8041 6691 6098 5581 5353 5271>, + <8104 6707 6096 5586 5356 5275>, + <8088 6704 6102 5586 5363 5282>, + <8048 6708 6104 5593 5368 5284>, + <8055 6725 6098 5595 5370 5288>, + <8059 6724 6114 5601 5370 5288>, + <8092 6743 6089 5598 5376 5290>, + <8157 6750 6086 5605 5374 5291>, + <8197 6722 6104 5609 5381 5293>, + <8269 6738 6105 5608 5384 5292>, + <8288 6759 6112 5624 5392 5304>, + <8380 6766 6128 5643 5400 5313>, + <8422 6779 6149 5656 5417 5324>, + <8422 6779 6149 5656 5417 5324>, + <8422 6779 6149 5656 5417 5324>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9654 9643 10639 11070 11121 11086>, + <9654 9643 10662 11056 11097 11058>, + <9655 9643 10675 11037 11063 11029>, + <9655 9871 10680 11014 11027 11001>, + <9656 10190 10680 10988 10997 10976>, + <9656 10325 10677 10959 10981 10958>, + <9657 10308 10664 10918 10973 10946>, + <9657 10282 10644 10881 10967 10935>, + <9657 10301 10632 10875 10959 10916>, + <9658 10440 10623 10874 10933 10882>, + <9658 10534 10619 10874 10919 10864>, + <9658 10489 10626 10869 10936 10874>, + <9659 10417 10643 10861 10961 10888>, + <9658 10413 10676 10856 10952 10885>, + <9657 10487 10748 10851 10897 10860>, + <9657 10553 10801 10851 10866 10840>, + <9657 10580 10826 10885 10876 10837>, + <9657 10597 10843 10946 10896 10845>, + <9657 10521 10842 11018 10943 10884>, + <9656 10042 10822 11115 11060 10984>, + <9656 9696 10809 11159 11120 11034>, + <9656 9682 10815 11129 11098 11013>, + <9656 9676 10826 11091 11071 10987>, + <9656 9675 10835 11085 11079 11009>, + <9656 9676 10846 11088 11121 11106>, + <9655 9676 10848 11093 11154 11162>, + <9655 9675 10684 11108 11176 11166>, + <9655 9671 10460 11130 11199 11168>, + <9655 9668 10652 11152 11224 11182>, + <9654 9665 11565 11178 11263 11214>, + <9654 9662 12069 11192 11286 11238>, + <9654 9660 11796 11199 11310 11257>, + <9654 9659 11319 11203 11338 11277>, + <9654 9657 10963 11202 11344 11307>, + <9654 9656 10643 11198 11320 11345>, + <9654 9655 10423 11189 11299 11359>, + <9653 9654 10140 11148 11294 11325>, + <9653 9653 9828 11108 11301 11280>, + <9653 9653 9733 11099 11301 11271>, + <9653 9653 9707 11096 11290 11278>, + <9653 9652 9692 11071 11287 11277>, + <9653 9652 9681 10975 11329 11250>, + <9653 9652 9674 10939 11356 11231>, + <9653 9652 9668 10913 11303 11229>, + <9653 9652 9664 10802 11253 11135>, + <9653 9652 9663 10839 11180 11044>, + <9653 9652 9661 10832 11146 11009>, + <9652 9652 9660 10811 11105 10962>, + <9652 9651 9659 10794 11061 10965>, + <9651 9651 9658 10764 11053 10938>, + <9650 9651 9658 10711 10981 10871>, + <9650 9651 9656 10651 10927 10829>, + <9649 9651 9654 10594 10851 10747>, + <9648 9651 9654 10531 10798 10659>, + <9648 9651 9654 10531 10798 10659>, + <9648 9651 9654 10531 10798 10659>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <14501 13677 13390 13309 13301 13279>, + <14412 13657 13393 13309 13294 13279>, + <14328 13634 13397 13311 13289 13279>, + <14249 13612 13400 13312 13285 13279>, + <14179 13596 13403 13314 13283 13279>, + <14117 13590 13406 13315 13282 13279>, + <14063 13594 13408 13315 13283 13280>, + <14017 13600 13410 13316 13286 13281>, + <13976 13594 13412 13317 13287 13282>, + <13939 13548 13416 13319 13287 13282>, + <13929 13515 13419 13321 13287 13282>, + <13957 13513 13421 13322 13289 13282>, + <13986 13512 13423 13323 13291 13282>, + <13945 13509 13422 13325 13291 13283>, + <13843 13504 13414 13328 13291 13284>, + <13803 13497 13407 13329 13291 13286>, + <13797 13488 13401 13328 13292 13287>, + <13793 13478 13395 13325 13294 13288>, + <13788 13470 13387 13324 13297 13290>, + <13783 13465 13376 13323 13301 13294>, + <13783 13458 13367 13322 13303 13296>, + <13788 13428 13360 13315 13297 13290>, + <13796 13384 13354 13306 13287 13281>, + <13814 13362 13349 13303 13283 13278>, + <13843 13349 13346 13300 13281 13277>, + <13874 13344 13341 13299 13280 13277>, + <13910 13351 13308 13299 13280 13277>, + <13952 13369 13266 13299 13282 13277>, + <13999 13391 13259 13298 13282 13277>, + <14052 13422 13259 13299 13283 13277>, + <14110 13460 13258 13299 13283 13277>, + <14174 13503 13258 13298 13283 13277>, + <14243 13554 13259 13298 13283 13277>, + <14318 13615 13263 13298 13283 13277>, + <14398 13690 13285 13299 13283 13278>, + <14481 13777 13302 13299 13283 13278>, + <14568 13879 13294 13296 13281 13277>, + <14658 13996 13281 13292 13279 13276>, + <14750 14118 13282 13292 13278 13276>, + <14850 14247 13299 13292 13277 13277>, + <14963 14377 13319 13293 13277 13277>, + <15082 14502 13343 13295 13277 13278>, + <15198 14624 13368 13298 13277 13278>, + <15302 14737 13402 13303 13278 13276>, + <15264 14824 13470 13304 13280 13278>, + <15439 14801 13476 13307 13284 13280>, + <15557 14824 13517 13316 13291 13286>, + <15783 14890 13560 13319 13292 13287>, + <16058 14961 13607 13332 13295 13287>, + <16423 15021 13665 13332 13292 13286>, + <16935 15095 13703 13333 13294 13286>, + <17701 15215 13779 13341 13296 13289>, + <18847 15382 13934 13350 13299 13292>, + <20636 15571 14143 13370 13308 13299>, + <20636 15571 14143 13370 13308 13299>, + <20636 15571 14143 13370 13308 13299>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17448 17305 16798 16610 16483 16470>, + <17520 17330 16862 16610 16486 16469>, + <17601 17378 16934 16609 16489 16468>, + <17679 17433 17001 16608 16491 16467>, + <17744 17479 17051 16607 16493 16467>, + <17783 17501 17070 16605 16493 16466>, + <17798 17503 17059 16603 16493 16466>, + <17813 17504 17041 16601 16492 16466>, + <17918 17511 17030 16599 16493 16466>, + <18180 17550 17023 16599 16497 16470>, + <18279 17608 17020 16599 16500 16473>, + <18148 17742 17034 16602 16502 16478>, + <17945 17902 17062 16609 16506 16483>, + <17736 17876 17086 16619 16512 16487>, + <17506 17547 17110 16638 16523 16492>, + <17399 17320 17134 16659 16535 16498>, + <17363 17344 17161 16679 16546 16506>, + <17328 17386 17183 16703 16560 16518>, + <17266 17370 17170 16748 16586 16537>, + <17193 17216 17080 16821 16630 16569>, + <17141 17060 16974 16852 16651 16585>, + <17100 16974 16865 16754 16602 16552>, + <17077 16908 16761 16616 16529 16502>, + <17070 16873 16703 16567 16502 16483>, + <17066 16851 16662 16543 16489 16473>, + <17066 16841 16647 16535 16485 16469>, + <17066 16841 16681 16535 16485 16470>, + <17067 16842 16727 16535 16487 16471>, + <17070 16843 16732 16537 16489 16474>, + <17074 16844 16721 16543 16497 16482>, + <17079 16845 16716 16549 16507 16491>, + <17088 16852 16721 16554 16521 16504>, + <17095 16866 16730 16558 16535 16515>, + <17099 16879 16732 16556 16540 16518>, + <17103 16893 16714 16549 16540 16515>, + <17111 16906 16704 16540 16534 16509>, + <17124 16920 16735 16528 16505 16492>, + <17134 16932 16784 16517 16477 16475>, + <17142 16941 16805 16517 16476 16471>, + <17149 16947 16815 16522 16479 16469>, + <17157 16950 16818 16530 16481 16469>, + <17167 16948 16818 16544 16482 16469>, + <17187 16945 16817 16555 16481 16467>, + <17208 16947 16815 16561 16471 16454>, + <17140 16965 16826 16575 16477 16456>, + <17176 16961 16849 16584 16493 16477>, + <17202 16977 16893 16606 16503 16495>, + <17281 17046 16954 16635 16528 16531>, + <17390 17107 17025 16679 16557 16532>, + <17524 17131 17054 16682 16515 16493>, + <17690 17101 17038 16673 16527 16498>, + <17978 17060 17051 16712 16548 16514>, + <18577 17063 17124 16764 16588 16554>, + <20156 17135 17255 16879 16727 16719>, + <20156 17135 17255 16879 16727 16719>, + <20156 17135 17255 16879 16727 16719>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10030 8712 14223 14774 19943 16308>, + <10448 8888 14349 15148 18667 15835>, + <10794 10562 14526 15365 17009 15457>, + <11054 12204 14713 15466 15353 15176>, + <11214 13579 14867 15489 14086 14997>, + <11260 14452 14948 15472 13593 14920>, + <11143 14948 14973 15335 13800 15003>, + <11001 15270 14986 15151 14123 15144>, + <11151 15028 14986 15098 14118 15087>, + <11850 13370 14973 15056 13826 14716>, + <12871 12246 14930 14978 13664 14315>, + <15188 13353 14287 14743 13788 13961>, + <17100 15163 13386 14398 13870 13634>, + <15786 15495 13334 14078 13643 13482>, + <12439 15197 13853 13740 13191 13549>, + <11406 14993 14346 13497 12887 13638>, + <11547 15443 14672 13207 12793 13546>, + <11662 16191 15006 12923 12796 13423>, + <11574 16138 15417 13004 13001 13548>, + <11364 14708 15994 13654 13569 14033>, + <11181 13284 16419 14434 14193 14440>, + <10986 12599 16670 15491 14905 14826>, + <10835 12068 16832 16433 15541 15160>, + <10734 11544 16827 16644 15650 15196>, + <10666 10962 16682 16591 15306 15346>, + <10655 10655 16390 16622 15048 15474>, + <10654 10648 14341 16597 15293 15494>, + <10654 10645 11728 16540 15744 15472>, + <10689 10665 11156 16578 15865 15229>, + <10734 10802 11032 16695 15749 14663>, + <10745 10946 10959 16756 15607 14352>, + <10765 11017 10901 16831 15502 14290>, + <10797 11076 10865 16959 15400 14311>, + <10882 11177 11054 17363 15705 14665>, + <10953 11367 12196 18097 16573 15740>, + <10940 11520 13011 18310 16919 16424>, + <10897 11584 12496 17269 16620 16376>, + <10863 11627 11602 15914 16091 16215>, + <10835 11630 11486 15213 15448 16327>, + <10820 11595 11681 14700 14692 16543>, + <10867 11570 11787 14330 14365 16550>, + <10955 11579 11797 14105 14243 16259>, + <11030 11596 11778 14219 14209 16346>, + <11029 11509 11647 14611 15058 16893>, + <11044 11331 11779 14198 14882 16382>, + <11143 11388 11508 14156 14882 14589>, + <11321 11488 11654 14603 16012 16142>, + <11356 11493 11662 14001 15040 14960>, + <11206 11613 11939 14918 15399 14828>, + <10932 11747 12726 15439 17093 17327>, + <10539 11665 12655 15981 17753 17255>, + <10263 11585 12280 16288 17881 17960>, + <9994 11459 12118 16141 17436 18200>, + <9668 11818 11932 16090 17352 17825>, + <9668 11818 11932 16090 17352 17825>, + <9668 11818 11932 16090 17352 17825>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7467 6132 5538 5158 5055 5027>, + <7418 6176 5550 5158 5053 5026>, + <7371 6205 5557 5158 5050 5025>, + <7326 6223 5561 5157 5048 5025>, + <7283 6232 5562 5156 5046 5025>, + <7242 6234 5562 5154 5046 5025>, + <7194 6227 5555 5152 5046 5025>, + <7159 6211 5540 5150 5047 5026>, + <7167 6191 5531 5149 5047 5027>, + <7202 6161 5522 5149 5048 5028>, + <7216 6144 5519 5149 5049 5029>, + <7195 6170 5520 5150 5051 5030>, + <7155 6214 5522 5151 5053 5031>, + <7075 6207 5523 5154 5055 5033>, + <6953 6119 5523 5160 5058 5035>, + <6899 6058 5522 5167 5061 5038>, + <6884 6060 5524 5172 5065 5041>, + <6872 6065 5527 5177 5070 5045>, + <6853 6054 5521 5188 5079 5052>, + <6834 5986 5487 5208 5095 5064>, + <6828 5923 5449 5216 5102 5070>, + <6826 5892 5413 5184 5083 5056>, + <6825 5871 5381 5138 5056 5035>, + <6839 5868 5365 5122 5045 5028>, + <6867 5872 5355 5114 5040 5024>, + <6893 5878 5349 5111 5038 5023>, + <6923 5895 5343 5112 5039 5023>, + <6956 5926 5339 5113 5040 5024>, + <6991 5960 5339 5115 5042 5026>, + <7030 5999 5342 5118 5045 5028>, + <7074 6044 5346 5121 5048 5031>, + <7122 6096 5354 5124 5053 5034>, + <7175 6156 5367 5126 5057 5038>, + <7232 6222 5383 5127 5059 5039>, + <7293 6297 5405 5127 5060 5039>, + <7357 6380 5430 5127 5058 5038>, + <7425 6470 5458 5124 5049 5032>, + <7495 6568 5491 5120 5041 5027>, + <7567 6667 5530 5121 5040 5027>, + <7643 6768 5579 5127 5041 5027>, + <7727 6867 5632 5133 5042 5028>, + <7816 6963 5689 5144 5044 5028>, + <7908 7053 5751 5155 5044 5028>, + <7994 7135 5817 5167 5043 5024>, + <7959 7206 5905 5181 5046 5026>, + <8096 7192 5921 5188 5056 5034>, + <8195 7214 5976 5205 5063 5044>, + <8412 7280 6034 5219 5072 5055>, + <8678 7350 6096 5248 5083 5055>, + <9031 7405 6155 5252 5069 5043>, + <9521 7454 6196 5257 5074 5046>, + <10251 7535 6282 5285 5084 5053>, + <11352 7666 6442 5320 5100 5069>, + <13075 7846 6646 5385 5148 5123>, + <13075 7846 6646 5385 5148 5123>, + <13075 7846 6646 5385 5148 5123>; + }; +}; diff --git a/qcom/qm215-audio.dtsi b/qcom/qm215-audio.dtsi new file mode 100644 index 00000000..05859267 --- /dev/null +++ b/qcom/qm215-audio.dtsi @@ -0,0 +1,199 @@ +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + iommus = <&apps_iommu 0x2001 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&soc { + qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + msm_audio_apr_dummy { + compatible = "qcom,msm-audio-apr-dummy"; + }; + }; + + qcom,avtimer@c0a300c { + compatible = "qcom,avtimer"; + reg = <0x0c0a300c 0x4>, + <0x0c0a3010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <27>; + }; + + int_codec: sound { + status = "okay"; + compatible = "qcom,msm8952-audio-codec"; + qcom,model = "msm8952-snd-card-mtp"; + reg = <0xc051000 0x4>, + <0xc051004 0x4>, + <0xc055000 0x4>, + <0xc052000 0x4>; + reg-names = "csr_gp_io_mux_mic_ctl", + "csr_gp_io_mux_spkr_ctl", + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel", + "csr_gp_io_mux_quin_ctl"; + + qcom,msm-ext-pa = "primary"; + qcom,msm-mclk-freq = <9600000>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-hs-micbias-type = "external"; + qcom,msm-micbias1-ext-cap; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "SPK_RX_BIAS", "MCLK", + "INT_LDO_H", "MCLK", + "RX_I2S_CLK", "MCLK", + "TX_I2S_CLK", "MCLK", + "MIC BIAS External", "Handset Mic", + "MIC BIAS External2", "Headset Mic", + "MIC BIAS External", "Secondary Mic", + "AMIC1", "MIC BIAS External", + "AMIC2", "MIC BIAS External2", + "AMIC3", "MIC BIAS External", + "ADC1_IN", "ADC1_OUT", + "ADC2_IN", "ADC2_OUT", + "ADC3_IN", "ADC3_OUT", + "PDM_IN_RX1", "PDM_OUT_RX1", + "PDM_IN_RX2", "PDM_OUT_RX2", + "PDM_IN_RX3", "PDM_OUT_RX3"; + + qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>; + qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_pri_auxpcm>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_mi2s5>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, + <&bt_sco_rx>, <&bt_sco_tx>, + <&int_fm_rx>, <&int_fm_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>; + + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6", + "msm-dai-q6-dev.16384", "msmdai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", + "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195"; + + asoc-codec = <&stub_codec>, <&msm_digital_codec>, + <&pmic_analog_codec>; + asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec", + "analog-codec"; + }; + + cdc_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cross_conn_det_act>; + pinctrl-1 = <&cross_conn_det_sus>; + }; + + cdc_pri_mi2s_gpios: msm_cdc_pinctrl_pri { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_pdm_lines_act &cdc_pdm_lines_2_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &cdc_pdm_lines_2_sus>; + }; + + cdc_quin_mi2s_gpios: msm_cdc_pinctrl_quin { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_tlmm_lines_act &pri_tlmm_ws_act>; + pinctrl-1 = <&pri_tlmm_lines_sus &pri_tlmm_ws_sus>; + }; +}; + +&pm8916_1 { + pmic_analog_codec: analog-codec@f000 { + status = "okay"; + compatible = "qcom,pmic-analog-codec"; + reg = <0xf000 0x200>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int", + "ear_ocp_int", + "hphr_ocp_int", + "hphl_ocp_det", + "ear_cnp_int", + "hphr_cnp_int", + "hphl_cnp_int"; + + cdc-vdd-pa-cp-supply = <&pm8916_s4>; + qcom,cdc-vdd-pa-cp-voltage = <2050000 2050000>; + qcom,cdc-vdd-pa-cp-current = <550000>; + + cdc-vdd-io-supply = <&pm8916_l5>; + qcom,cdc-vdd-io-voltage = <1800000 1800000>; + qcom,cdc-vdd-io-current = <5000>; + + cdc-vdda-h-supply = <&pm8916_l5>; + qcom,cdc-vdda-h-voltage = <1800000 1800000>; + qcom,cdc-vdda-h-current = <10000>; + + cdc-vdd-mic-bias-supply = <&pm8916_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <5000>; + + qcom,cdc-mclk-clk-rate = <9600000>; + + qcom,cdc-static-supplies = "cdc-vdd-io", + "cdc-vdd-pa-cp", + "cdc-vdda-h"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + + msm_digital_codec: msm-dig-codec { + compatible = "qcom,msm-digital-codec"; + reg = <0xc0f0000 0x0>; + }; + }; +}; diff --git a/qcom/qm215-camera-sensor-qrd.dtsi b/qcom/qm215-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..7b068f7b --- /dev/null +++ b/qcom/qm215-camera-sensor-qrd.dtsi @@ -0,0 +1,191 @@ +&cci { + #address-cells = <1>; + #size-cells = <0>; + + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&pm8916_l10>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + qcom,cci-master = <0>; + reg = <0x0>; + cam_vana-supply = <&pm8916_l16>; + cam_vio-supply = <&pm8916_l6>; + cam_vaf-supply = <&pm8916_l10>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf"; + qcom,cam-vreg-min-voltage = <0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <0 2800000 2850000>; + qcom,cam-vreg-op-mode = <0 80000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_vdig_qm215 + &cam_sensor_rear_default>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_vdig_sleep_qm215 + &cam_sensor_rear_sleep>; + gpios = <&tlmm 25 0>, + <&tlmm 26 0>, + <&tlmm 36 0>; + qcom,gpio-reset = <2>; + qcom,gpio-vdig = <0>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <0 1 0>; + qcom,gpio-req-tbl-label = "CAM_VDIG", + "CAMIF_MCLK0", + "CAM_RESET0"; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + reg = <0x02>; + cam_vana-supply = <&pm8916_l16>; + cam_vio-supply = <&pm8916_l6>; + cam_vaf-supply = <&pm8916_l10>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf"; + qcom,cam-vreg-min-voltage = <0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <0 2800000 2850000>; + qcom,cam-vreg-op-mode = <0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_rear_vdig_qm215 + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_rear_vdig_sleep_qm215 + &cam_sensor_front1_sleep>; + gpios = <&tlmm 25 0>, + <&tlmm 28 0>, + <&tlmm 40 0>; + qcom,gpio-reset = <2>; + qcom,gpio-standby = <0>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0 >; + qcom,gpio-req-tbl-label = "CAM_VDIG", + "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + flash0: qcom,camera-flash { + cell-index = <0>; + compatible = "qcom,qm215-gpio-flash"; + qcom,flash-type = <2>; + gpios = <&tlmm 34 0>, + <&tlmm 33 0>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-flash-en = <0>; + qcom,gpio-flash-now = <1>; + qcom,gpio-req-tbl-label = "CAM_FLASH", + "CAM_TORCH"; + status = "ok"; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,led-flash-src = <&flash0>; + qcom,actuator-src = <&actuator0>; + qcom,eeprom-src = <&eeprom0>; + cam_vana-supply = <&pm8916_l16>; + cam_vio-supply = <&pm8916_l6>; + cam_vaf-supply = <&pm8916_l10>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf"; + qcom,cam-vreg-min-voltage = <0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <0 2800000 2850000>; + qcom,cam-vreg-op-mode = <0 80000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_vdig_qm215 + &cam_sensor_rear_default>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_vdig_sleep_qm215 + &cam_sensor_rear_sleep>; + gpios = <&tlmm 25 0>, + <&tlmm 26 0>, + <&tlmm 36 0>; + + qcom,gpio-reset = <2>; + qcom,gpio-vdig = <0>; + qcom,gpio-req-tbl-num = <0 1 2 >; + qcom,gpio-req-tbl-flags = <1 0 0 >; + qcom,gpio-req-tbl-label = "CAM_VDIG", + "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x01>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,eeprom-src = <&eeprom2>; + qcom,mount-angle = <270>; + cam_vana-supply = <&pm8916_l16>; + cam_vio-supply = <&pm8916_l6>; + cam_vaf-supply = <&pm8916_l10>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf"; + qcom,cam-vreg-min-voltage = <0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <0 2800000 2850000>; + qcom,cam-vreg-op-mode = <0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_rear_vdig_qm215 + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_rear_vdig_sleep_qm215 + &cam_sensor_front1_sleep>; + gpios = <&tlmm 25 0>, + <&tlmm 28 0>, + <&tlmm 40 0>; + qcom,gpio-reset = <2>; + qcom,gpio-vdig = <0>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAM_VDIG", + "CAMIF_MCLK2", + "CAM_RESET2"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; diff --git a/qcom/qm215-camera.dtsi b/qcom/qm215-camera.dtsi new file mode 100644 index 00000000..aad0017e --- /dev/null +++ b/qcom/qm215-camera.dtsi @@ -0,0 +1,514 @@ +&soc { + qcom,msm-cam@1b00000 { + compatible = "qcom,msm-cam"; + reg = <0x1b00000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 160000000 320000000 320000000>; + }; + + qcom,csiphy@1b34000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b34000 0x1000>, + <0x1b00030 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "csi_phy_clk", + "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0 0>; + }; + + qcom,csiphy@1b35000 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy"; + reg = <0x1b35000 0x1000>, + <0x1b00038 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ahb_src", "csi_phy_clk", + "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 200000000 0 0 0 0>; + }; + + qcom,csid@1b30000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30000 0x400>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1088000>; + qcom,mipi-csi-vdd-supply = <&pm8916_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,csid@1b30400 { + status = "ok"; + cell-index = <1>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30400 0x400>; + reg-names = "csid"; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1088000>; + qcom,mipi-csi-vdd-supply = <&pm8916_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,csid@1b30800 { + status = "ok"; + cell-index = <2>; + compatible = "qcom,csid-v3.4.3", "qcom,csid"; + reg = <0x1b30800 0x400>; + reg-names = "csid"; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1088000>; + qcom,mipi-csi-vdd-supply = <&pm8916_l2>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk", + "csi_clk", "csi_pix_clk", + "csi_rdi_clk", "camss_ahb_clk"; + qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>; + }; + + qcom,ispif@1b31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0x1b31000 0x500>, + <0x1b00020 0x10>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + vfe0-vdd-supply = <&gdsc_vfe>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "vfe0-vdd", "vfe1-vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc CAMSS_TOP_AHB_CLK_SRC>, + <&gcc CSI0_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc CSI1_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc CSI2_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "ispif_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_ahb_src", + "csi0_src_clk", "csi0_clk", + "csi0_rdi_clk", "csi0_pix_clk", + "csi1_src_clk", "csi1_clk", + "csi1_rdi_clk", "csi1_pix_clk", + "csi2_src_clk", "csi2_clk", + "csi2_rdi_clk", "csi2_pix_clk", + "vfe0_clk_src", "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", "vfe1_clk_src", + "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; + qcom,clock-rates = <61540000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 200000000 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-cntl-support; + qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "SET_RATE", "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE"; + }; + + vfe0: qcom,vfe0@1b10000 { + cell-index = <0>; + compatible = "qcom,vfe40"; + reg = <0x1b10000 0x1000>, + <0x1b40000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE0_CLK_SRC>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk", "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + vfe1: qcom,vfe1@1b14000 { + cell-index = <1>; + compatible = "qcom,vfe40"; + reg = <0x1b14000 0x1000>, + <0x1ba0000 0x200>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc VFE1_CLK_SRC>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>; + clock-names = "camss_top_ahb_clk" , "camss_ahb_clk", + "vfe_clk_src", "camss_vfe_vfe_clk", + "camss_csi_vfe_clk", "iface_clk", + "bus_clk", "iface_ahb_clk"; + qcom,clock-rates = <0 0 266670000 0 0 0 0 0>; + qos-entries = <8>; + qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8 + 0x2dc 0x2e0>; + qos-settings = <0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55 0xaa55aa55 + 0xaa55aa55>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x988 0x98c 0x990 0x994 0x998 + 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0 + 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>; + ds-settings = <0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0xcccc1111 + 0xcccc1111 0x00000110>; + max-clk-nominal = <400000000>; + max-clk-turbo = <432000000>; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + qcom,cam_smmu { + status = "ok"; + compatible = "qcom,msm-cam-smmu"; + msm_cam_smmu_cb1: msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x400 0x00>, + <&apps_iommu 0x2400 0x00>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2: msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + label = "vfe_secure"; + qcom,secure-context; + }; + + msm_cam_smmu_cb3: msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1c00 0x00>; + label = "cpp"; + }; + + msm_cam_smmu_cb4: msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_iommu 0x1800 0x00>; + label = "jpeg_enc0"; + }; + }; + + qcom,jpeg@1b1c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0x1b1c000 0x400>, + <0x1b60000 0xc30>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "jpeg"; + vdd-supply = <&gdsc_jpeg>; + qcom,vdd-names = "vdd"; + clock-names = "core_clk", "iface_clk", "bus_clk0", + "camss_top_ahb_clk", "camss_ahb_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + qcom,clock-rates = <266670000 0 0 0 0>; + qcom,qos-reg-settings = <0x28 0x0000555e>, + <0xc8 0x00005555>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 800000 800000>; + qcom,vbif-reg-settings = <0xc0 0x10101000>, + <0xb0 0x10100010>; + }; + + qcom,cpp@1b04000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0x1b04000 0x100>, + <0x1b80000 0x200>, + <0x1b18000 0x018>, + <0x1858078 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpp"; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "vdd"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CPP_CLK_SRC>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AHB_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>, + <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cpp_core_clk", + "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk", + "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk", + "micro_iface_clk", "camss_ahb_clk"; + qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>; + qcom,min-clock-rate = <133000000>; + resets = <&gcc GCC_CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,bus-master = <1>; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <156>; + qcom,plane-base = <141>; + qcom,stripe-size = <27>; + qcom,plane-size = <5>; + qcom,fe-ptr-off = <5>; + qcom,we-ptr-off = <11>; + }; + }; + + cci: qcom,cci@1b0c000 { + status = "ok"; + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0x1b0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cci"; + clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc CCI_CLK_SRC>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-names = "ispif_ahb_clk", "cci_src_clk", + "cci_ahb_clk", "camss_cci_clk", + "camss_ahb_clk", "camss_top_ahb_clk"; + qcom,clock-rates = <61540000 19200000 0 0 0 0>, + <61540000 37500000 0 0 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 30 0>, + <&tlmm 31 0>, + <&tlmm 32 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <78>; + qcom,hw-tlow = <114>; + qcom,hw-tsu-sto = <28>; + qcom,hw-tsu-sta = <28>; + qcom,hw-thd-dat = <10>; + qcom,hw-thd-sta = <77>; + qcom,hw-tbuf = <118>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <1>; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <20>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <32>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <15>; + qcom,hw-tlow = <28>; + qcom,hw-tsu-sto = <21>; + qcom,hw-tsu-sta = <21>; + qcom,hw-thd-dat = <13>; + qcom,hw-thd-sta = <18>; + qcom,hw-tbuf = <25>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <19>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/qcom/qm215-pm8916.dtsi b/qcom/qm215-pm8916.dtsi new file mode 100644 index 00000000..fa08b0f8 --- /dev/null +++ b/qcom/qm215-pm8916.dtsi @@ -0,0 +1,596 @@ +/* delete PMIC specific nodes */ +&soc { + /* delete rpm-smd base node to delete all regulator in one shot */ + /delete-node/ qcom,rpm-smd; + + /* add rpm-smd node again */ + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + /* delete all pmic nodes */ + qcom,spmi@200f000 { + /delete-node/ qcom,pm8937@0; + /delete-node/ qcom,pm8937@1; + }; +}; + +/* delete all node referring PM8937 */ +&soc { + thermal-zones { + /delete-node/ pa-therm1-adc; + /delete-node/ xo-therm-adc; + /delete-node/ xo-therm-buf-adc; + /delete-node/ case-therm-adc; + /delete-node/ pa-therm0-adc; + /delete-node/ pm8937_tz; + + aoss0-lowf { + cooling-maps { + cx_vdd_cdev { + /delete-property/ cooling-device; + }; + }; + }; + }; + + qcom,cpu-clock-8939@b111050 { + /delete-property/ vdd-c1-supply; + }; + + qcom,gcc@1800000 { + /delete-property/ vdd_cx-supply; + /delete-property/ vdd_hf_dig-supply; + /delete-property/ vdd_hf_pll-supply; + }; + + usb@78db000 { + /delete-property/ hsusb_vdd_dig-supply; + /delete-property/ HSUSB_1p8-supply; + /delete-property/ HSUSB_3p3-supply; + /delete-property/ vbus_otg-supply; + }; + + qcom,mss@4080000 { + /delete-property/ vdd_mss-supply; + /delete-property/ vdd_cx-supply; + /delete-property/ vdd_mx-supply; + /delete-property/ vdd_pll-supply; + vdd_mss-supply = <&pm8916_s1_level>; + vdd_cx-supply = <&pm8916_s1_level>; + vdd_mx-supply = <&pm8916_l2_level_ao>; + vdd_pll-supply = <&pm8916_l7>; + }; + + qcom,lpass@c200000 { + /delete-property/ vdd_cx-supply; + vdd_cx-supply = <&pm8916_s1_level>; + }; + + qcom,pronto@a21b000 { + /delete-property/ vdd_pronto_pll-supply; + vdd_pronto_pll-supply = <&pm8916_l7>; + }; + + qcom,wcnss-wlan@a000000 { + /delete-property/ qcom,has-vsys-adc-channel; + qcom,wcnss-adc_tm = <&pm8916_adc_tm>; + qcom,pronto-vddmx-supply = <&pm8916_l2_level_ao>; + qcom,pronto-vddcx-supply = <&pm8916_s1_level>; + qcom,pronto-vddpx-supply = <&pm8916_l7>; + qcom,iris-vddxo-supply = <&pm8916_l7>; + qcom,iris-vddrfa-supply = <&pm8916_l3>; + qcom,iris-vddpa-supply = <&pm8916_l9>; + qcom,iris-vdddig-supply = <&pm8916_l7>; + + qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; + qcom,iris-vddrfa-voltage-level = <1325000 0 1325000>; + qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; + qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; + + qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NONE + RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,vddpx-voltage-level = <1800000 0 1800000>; + + qcom,iris-vddxo-current = <10000>; + qcom,iris-vddrfa-current = <100000>; + qcom,iris-vddpa-current = <515000>; + qcom,iris-vdddig-current = <10000>; + + qcom,pronto-vddmx-current = <0>; + qcom,pronto-vddcx-current = <0>; + qcom,pronto-vddpx-current = <0>; + }; + + /* mem_acc */ + /delete-node/ regulator@01946004; + /* apc vreg */ + /delete-node/ regulator@b018000; + /delete-node/ eldo2; + /delete-node/ adv_vreg; +}; + +#include "pm8916-rpm-regulator.dtsi" +#include "pm8916.dtsi" +#include "qm215-regulator.dtsi" + +&spmi_bus { + pm8916@1 { + /delete-node/ msm8x16_wcd_codec@f000; + }; +}; + +&pm8916_gpios { + disp_vdda_en_default: disp_vdda_en_default { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + drive-strength = <8>; + output-high; + }; +}; + +&soc { + disp_vdda_eldo1: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "disp_vdda_eldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm8916_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&disp_vdda_en_default>; + vin-supply = <&pm8916_s3>; + }; +}; + +&mdss_dsi0_pll { + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi0 { + /delete-property/ vdd-supply; + vddio-supply = <&pm8916_l6>; +}; + +&mdss_dsi { + vdda-supply = <&pm8916_l6>; + vddio-supply = <&pm8916_l6>; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1744000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda"; + qcom,supply-min-voltage = <1744000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; +}; + +&clock_cpu { + vdd-c1-supply = <&apc_vreg_corner>; +}; + +&gcc { + vdd_cx-supply = <&pm8916_s1_level>; + vdd_hf_dig-supply = <&pm8916_s1_level_ao>; + vdd_hf_pll-supply = <&pm8916_l7_ao>; +}; + +&pm8916_vadc { + chan@0 { + label = "usb_in"; + reg = <0>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <7>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@2 { + label = "ireg_fb"; + reg = <2>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <6>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@5 { + label = "vcoin"; + reg = <5>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@7 { + label = "vph_pwr"; + reg = <7>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@b { + label = "chg_temp"; + reg = <0xb>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@11 { + label = "skin_therm"; + reg = <0x11>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <26>; + qcom,hw-settle-time = <0xb>; + qcom,fast-avg-setup = <0>; + }; + + chan@31 { + label = "batt_id"; + reg = <0x31>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0xb>; + qcom,fast-avg-setup = <0>; + }; + + chan@36 { + label = "pa_therm0"; + reg = <0x36>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@32 { + label = "xo_therm"; + reg = <0x32>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; + + chan@3c { + label = "xo_therm_buf"; + reg = <0x3c>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + qcom,vadc-thermal-node; + }; +}; + +&pm8916_adc_tm { + /* Channel Node */ + chan@30 { + label = "batt_therm"; + reg = <0x30>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <8>; + qcom,hw-settle-time = <0xb>; + qcom,fast-avg-setup = <0x2>; + qcom,btm-channel-number = <0x48>; + }; + + chan@6 { + label = "vbat_sns"; + reg = <0x6>; + qcom,decimation = <0>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0xb>; + qcom,fast-avg-setup = <0x2>; + qcom,btm-channel-number = <0x68>; + }; +}; + +&soc { + thermal-zones { + xo-therm-buf-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm8916_vadc 0x3c>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm8916_vadc 0x32>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm8916_vadc 0x36>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm8916_vadc 0x11>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss0-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8916_cx_cdev 0 0>; + }; + }; + }; + + pm8916_tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8916_tz>; + + trips { + pm8916_trip0: pm8916-trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8916_trip1: pm8916-trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8916_trip2: pm8916-trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + xo-therm-step { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&pm8916_vadc 0x32>; + thermal-governor = "step_wise"; + + trips { + qm215_batt_trip0: qm215-batt-trip0 { + temperature = <41000>; + hysteresis = <2000>; + type = "passive"; + }; + + qm215_modem_trip0: qm215-modem-trip0 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + qm215_batt_trip1: qm215-batt-trip1 { + temperature = <45000>; + hysteresis = <4000>; + type = "passive"; + }; + + qm215_modem_trip1: qm215-modem-trip1 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + qm215_cpu_trip: qm215-cpu-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + qm215_gpu_trip: qm215-gpu-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + qm215_modem_trip2: qm215-modem-trip2 { + temperature = <60000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + skin_cpu0 { + trip = <&qm215_cpu_trip>; + /* throttle from fmax to 1094400KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + skin_cpu1 { + trip = <&qm215_cpu_trip>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + skin_cpu2 { + trip = <&qm215_cpu_trip>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + skin_cpu3 { + trip = <&qm215_cpu_trip>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + skin_gpu { + trip = <&qm215_gpu_trip>; + /* throttle from fmax to 400000000Hz */ + cooling-device = <&msm_gpu + THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + modem_lvl1 { + trip = <&qm215_modem_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem_lvl2 { + trip = <&qm215_modem_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem_lvl3 { + trip = <&qm215_modem_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + + battery_lvl1 { + trip = <&qm215_batt_trip0>; + cooling-device = <&pm8916_chg 1 1>; + }; + + battery_lvl2 { + trip = <&qm215_batt_trip1>; + cooling-device = <&pm8916_chg 2 2>; + }; + }; + }; + }; +}; + +&soc { + usb_vdig_supply: usb_vdig_supply { + compatible = "regulator-fixed"; + regulator-name = "usb_vdig_supply"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; +}; + +&usb_otg { + hsusb_vdd_dig-supply = <&usb_vdig_supply>; + HSUSB_1p8-supply = <&pm8916_l7>; + HSUSB_3p3-supply = <&pm8916_l13>; + extcon = <&pm8916_chg>; +}; diff --git a/qcom/qm215-qrd-overlay.dts b/qcom/qm215-qrd-overlay.dts new file mode 100644 index 00000000..6927ecf8 --- /dev/null +++ b/qcom/qm215-qrd-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "qm215-qrd.dtsi" + +/ { + model = "QRD"; + qcom,board-id = <0x01000b 4>; +}; diff --git a/qcom/qm215-qrd-smb1360-overlay.dts b/qcom/qm215-qrd-smb1360-overlay.dts new file mode 100644 index 00000000..a42539af --- /dev/null +++ b/qcom/qm215-qrd-smb1360-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "qm215-qrd-smb1360.dtsi" + +/ { + model = "QRD + SMB1360"; + qcom,board-id = <0x0b 5>; +}; diff --git a/qcom/qm215-qrd-smb1360.dts b/qcom/qm215-qrd-smb1360.dts new file mode 100644 index 00000000..b2e9e15d --- /dev/null +++ b/qcom/qm215-qrd-smb1360.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "qm215.dtsi" +#include "qm215-pm8916.dtsi" +#include "qm215-qrd-smb1360.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. qm215 SMB1360 QRD"; + compatible = "qcom,qm215-qrd", "qcom,qm215", "qcom,qrd"; + qcom,board-id = <0x0b 5>; +}; diff --git a/qcom/qm215-qrd-smb1360.dtsi b/qcom/qm215-qrd-smb1360.dtsi new file mode 100644 index 00000000..84e9e78b --- /dev/null +++ b/qcom/qm215-qrd-smb1360.dtsi @@ -0,0 +1,80 @@ +#include "qm215-qrd.dtsi" + +&pm8916_chg { + qcom,use-external-charger; +}; + +&pm8916_bms { + qcom,disable-bms; +}; + +&tlmm { + /* SMB interrupt pin */ + smb_int_pin { + smb_int_default: smb_int_default { + mux { + pins = "gpio13"; + function ="gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP*/ + input-enable; + }; + }; + }; +}; + +&pm8916_gpios { + usb_id { + usb_id_default: usb_id_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&i2c_2 { + #address-cells = <1>; + #size-cells = <0>; + + status ="ok"; + smb1360_otg_supply: smb1360-chg-fg@14 { + compatible = "qcom,smb1360-chg-fg"; + reg = <0x14>; + interrupts-extended = <&tlmm 13 8>, + <&spmi_bus 0 0xc3 0 3>; + interrupt-names = "smb1360_stat_irq", + "smb1360_usb_id_irq"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>, + <&usb_id_default>; + qcom,empty-soc-disabled; + qcom,chg-inhibit-disabled; + qcom,float-voltage-mv = <4400>; + qcom,iterm-ma = <100>; + qcom,recharge-thresh-mv = <100>; + qcom,thermal-mitigation = <1500 700 600 0>; + qcom,fg-batt-capacity-mah = <2800>; + qcom,fg-cutoff-voltage-mv = <3400>; + qcom,fg-iterm-ma = <130>; + qcom,fg-delta-soc = <1>; + qcom,usb-id-gpio = <&pm8916_gpios 4 0>; + qcom,soft-jeita-supported; + qcom,warm-bat-decidegc = <450>; + qcom,cool-bat-decidegc = <150>; + qcom,warm-bat-mv = <4200>; + qcom,cool-bat-mv = <4200>; + qcom,warm-bat-ma = <1000>; + qcom,cool-bat-ma = <1000>; + status= "okay"; + }; +}; + +&usb_otg { + extcon = <&smb1360_otg_supply>; +}; diff --git a/qcom/qm215-qrd.dts b/qcom/qm215-qrd.dts new file mode 100644 index 00000000..b8f63e43 --- /dev/null +++ b/qcom/qm215-qrd.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "qm215.dtsi" +#include "qm215-pm8916.dtsi" +#include "qm215-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. qm215 QRD"; + compatible = "qcom,qm215-qrd", "qcom,qm215", "qcom,qrd"; + qcom,board-id = <0x01000b 4>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/qm215-qrd.dtsi b/qcom/qm215-qrd.dtsi new file mode 100644 index 00000000..ab48a9ed --- /dev/null +++ b/qcom/qm215-qrd.dtsi @@ -0,0 +1,243 @@ +#include <dt-bindings/clock/qcom,rpmcc.h> + +&blsp1_uart2 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include "qm215-camera-sensor-qrd.dtsi" + +&pm8916_chg { + status = "ok"; + qcom,chgr-led-support; + qcom,vddmax-mv = <4400>; + qcom,vddsafe-mv = <4400>; + qcom,batt-hot-percentage = <35>; +}; + +&pm8916_bms { + status = "ok"; + qcom,battery-data = <&qrd_batterydata>; + qcom,batt-aging-comp; + qcom,resume-soc = <99>; +}; + +&pm8916_vib { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_active>; + + vol_up { + label = "volume_up"; + gpios = <&tlmm 91 0x1>; + linux,input-type = <1>; + linux,code = <115>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + fpc1020 { + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <48 0>; + fpc,gpio_rst = <&tlmm 124 0x0>; + fpc,gpio_irq = <&tlmm 48 0>; + vcc_spi-supply = <&pm8916_l5>; + vdd_io-supply = <&pm8916_l5>; + vdd_ana-supply = <&pm8916_l5>; + fpc,enable-on-boot; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + pinctrl-0 = <&fpc_reset_low>; + pinctrl-1 = <&fpc_reset_high>; + pinctrl-2 = <&fpc_int_low>; + }; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm8916_l8>; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 400000>; + + /* + * device communication power is an external + * regulator eLDO3, which is enabled via L5A + */ + vdd-io-supply = <&pm8916_l5>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm8916_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 800000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8916_l12>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 67 0x0>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + status = "ok"; +}; + +&mdss_dsi_active { + mux { + pins = "gpio60", "gpio93", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio93", "gpio94"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; +}; + +&mdss_dsi_suspend { + mux { + pins = "gpio60", "gpio93", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio93", "gpio94"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; +}; + +#include "msm8937-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1744000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + /delete-node/ qcom,panel-supply-entry@1; + /delete-node/ qcom,panel-supply-entry@2; + /delete-node/ qcom,panel-supply-entry@3; +}; + +&pm8916_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio2"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&i2c_5 { /* BLSP2 QUP1 (NFC) */ + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 17 0x00>; + qcom,nq-ven = <&tlmm 16 0x00>; + qcom,nq-firm = <&tlmm 130 0x00>; + qcom,nq-clkreq = <&pm8916_gpios 2 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK2"; + interrupts = <17 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_disable_active + &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>; + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + clock-names = "ref_clk"; + }; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 24 0>; + qcom,platform-reset-gpio = <&tlmm 60 0>; + qcom,platform-bklight-en-gpio = <&tlmm 93 0>; + qcom,platform-enable-gpio = <&tlmm 94 0>; +}; + +&dsi_hx8399c_hd_vid { + qcom,mdss-dsi-panel-timings = + [e7 1c 12 00 42 42 18 20 17 03 04 00]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8916_mpps 4 0>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; diff --git a/qcom/qm215-regulator.dtsi b/qcom/qm215-regulator.dtsi new file mode 100644 index 00000000..834859d4 --- /dev/null +++ b/qcom/qm215-regulator.dtsi @@ -0,0 +1,552 @@ +/* RPM controlled regulators */ + +&rpm_bus { + /* PM8916 S1 VDD_CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + pm8916_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8916_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8916_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8916_cx_cdev: regulator-cx-cdev { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pm8916_s1_floor_level>; + regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_RETENTION>; + #cooling-cells = <2>; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8916_s3: regulator-s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1448000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8916_s4: regulator-s4 { + regulator-min-microvolt = <1992000>; + regulator-max-microvolt = <2160000>; + qcom,init-voltage = <1992000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8916_l1: regulator-l1 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1152000>; + qcom,init-voltage = <968000>; + status = "okay"; + }; + }; + + /* PM8916 L2 VDD_MX supply */ + rpm-regulator-ldoa2 { + status = "okay"; + pm8916_l2: regulator-l2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1088000>; + status = "okay"; + }; + + pm8916_l2_level_ao: regulator-l2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm8916_l2_level_so: regulator-l2-level-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l2_level_so"; + qcom,set = <2>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + qcom,init-voltage-level = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8916_l3: regulator-l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1384000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pm8916_l4: regulator-l4 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1744000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8916_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8916_l6: regulator-l6 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1744000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8916_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8916_l7_ao: regulator-l7-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l7_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + }; + + pm8916_l7_so: regulator-l7-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8916_l7_so"; + qcom,set = <2>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-enable = <0>; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8916_l8: regulator-l8 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2696000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8916_l9: regulator-l9 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <3376000>; + qcom,init-voltage = <2904000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8916_l10: regulator-l10 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8916_l11: regulator-l11 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2696000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8916_l12: regulator-l12 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8916_l13: regulator-l13 { + regulator-min-microvolt = <2968000>; + regulator-max-microvolt = <3080000>; + qcom,init-voltage = <2968000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8916_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3056000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8916_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3056000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8916_l16: regulator-l16 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2840000>; + qcom,init-voltage = <2696000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8916_l17: regulator-l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8916_l18: regulator-l18 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2600000>; + status = "okay"; + }; + }; +}; + +/* SPM controlled regulators */ +&spmi_bus { + pm8916@1 { + pm8916_s2: spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8916_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + }; + }; +}; + +/* CPR controlled regulator */ + +&soc { + mem_acc_vreg_corner: regulator@01946004 { + compatible = "qcom,mem-acc-regulator"; + reg = <0xa4000 0x1000>; + reg-names = "efuse_addr"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-reg-addr-list = + <0x01942138 0x01942130 0x01942120 0x01942124>; + + qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x0>, + < 4 0x0>; + + qcom,corner2-reg-config = + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>; + + qcom,corner3-reg-config = + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>; + + qcom,override-acc-fuse-sel = <71 17 3 0>; + qcom,override-fuse-version-map = <1>, + <2>, + <3>, + <4>; + qcom,override-corner1-addr-val-map = + /* 1st fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x1>, + < 4 0x0>, + + /* 2nd fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x3>, + < 4 0x0>, + + /* 3rd fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x0>, + < 4 0x0>, + + /* 4th fuse version tuple matched */ + /* SVS+ => SVS+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* SVS+ => TURBO/NOM+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x1>, + < 4 0x0>; + + qcom,override-corner2-addr-val-map = + /* 1st fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x1>, < 4 0x0>, + + /* 2nd fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x3>, < 4 0x0>, + + /* 3rd fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x0>, < 4 0x0>, + + /* 4th fuse version tuple matched */ + /* NOM => SVS+ */ + < 3 0x30c30c3>, < 4 0x30c3>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>, + /* NOM => TURBO/NOM+ */ + < 3 0x1>, < 4 0x0>; + + qcom,override-corner3-addr-val-map = + /* 1st fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 2nd fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 3rd fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>, + + /* 4th fuse version tuple matched */ + /* TURBO/NOM+ => SVS+ */ + < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>, + < 4 0x30c3>, + /* TURBO/NOM+ => NOM */ + < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>, + <(-1) (-1)>, + /* TURBO/NOM+ => TURBO/NOM+ */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, + <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <5>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>; + qcom,cpr-voltage-floor = <1050000 1050000 1090000>; + vdd-apc-supply = <&pm8916_s2>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <26>; + qcom,cpr-up-threshold = <0>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <12500>; + + qcom,cpr-fuse-row = <67 0>; + qcom,cpr-fuse-target-quot = <42 24 6>; + qcom,cpr-fuse-ro-sel = <60 57 54>; + qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>; + qcom,cpr-fuse-init-voltage = + <67 36 6 0>, + <67 18 6 0>, + <67 0 6 0>; + qcom,cpr-fuse-quot-offset = + <71 26 6 0>, + <71 20 6 0>, + <70 54 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 960000000>, + <2 1094400000>, + <3 1248000000>, + <4 1305600000>, + <5 1401000000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 (-1) 1 2 5>, + <3 (-1) 1 2 5>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-fuse-revision = <69 39 3 0>; + qcom,pvs-version-fuse-sel = <37 40 3 0>; /* foundry */ + qcom,cpr-fuse-version-map = + <(-1) 1 (-1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1)>; + qcom,cpr-quotient-adjustment = + <30 20 0>, + <50 40 50>; + qcom,cpr-init-voltage-adjustment = + <0 0 0>, + <30000 5000 10000>; + qcom,cpr-enable; + }; +}; diff --git a/qcom/qm215.dts b/qcom/qm215.dts new file mode 100644 index 00000000..7d6f0477 --- /dev/null +++ b/qcom/qm215.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "qm215.dtsi" +#include "qm215-pm8916.dtsi" +/* TBD */ +/* #include "qm215-audio.dtsi" */ + +/ { + model = "Qualcomm Technologies, Inc. QM215"; + compatible = "qcom,qm215"; + qcom,pmic-name = "PM8916"; +}; diff --git a/qcom/qm215.dtsi b/qcom/qm215.dtsi new file mode 100644 index 00000000..93e1afcb --- /dev/null +++ b/qcom/qm215.dtsi @@ -0,0 +1,255 @@ +#include "msm8917.dtsi" +#include "qm215-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. QM215"; + compatible = "qcom,qm215"; + qcom,msm-id = <386 0x0>; + qcom,msm-name = "QM215"; +}; + +/ { + qrd_batterydata: qcom,batterydata { + qcom,rpull-up-kohm = <100>; + qcom,vref-batt-therm = <1800000>; + + #include "vbms-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&soc { + qcom,vidc@1d00000 { + qcom,allowed-clock-rates = <329140000 329140000 + 308570000 270000000 200000000>; + }; +}; + +&rpmcc { + compatible = "qcom,rpmcc-qm215"; +}; + +&gcc { + compatible = "qcom,gcc-qm215", "syscon"; +}; + +&debugcc { + compatible = "qcom,qm215-debugcc"; +}; + +/* GPU overrides */ +&msm_gpu { + + qcom,gpu-speed-bin = <0x0164 0x00000600 9>; + /delete-property/qcom,gpu-speed-bin-vectors; + /delete-node/qcom,gpu-pwrlevel-bins; + + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <598000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <7>; + qcom,bus-max = <7>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <523200000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <484800000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <6>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <2>; + + /* NOM+ */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <2>; + qcom,initial-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <3>; + qcom,initial-pwrlevel = <0>; + + /* SVS+ */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <6>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; + +&thermal_zones { + gpu0-step { + trips { + gpu-step-trip { + temperature = <85000>; + }; + }; + }; +}; diff --git a/qcom/sda429-cdp.dts b/qcom/sda429-cdp.dts new file mode 100644 index 00000000..a83064d3 --- /dev/null +++ b/qcom/sda429-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sda429.dtsi" +#include "sdm429-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA429 CDP"; + compatible = "qcom,sda429-cdp", "qcom,sda429", "qcom,cdp"; + qcom,board-id = <1 3>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sda429-mtp.dts b/qcom/sda429-mtp.dts new file mode 100644 index 00000000..737da2b4 --- /dev/null +++ b/qcom/sda429-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sda429.dtsi" +#include "sdm429-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA429 MTP"; + compatible = "qcom,sda429-mtp", "qcom,sda429", "qcom,mtp"; + qcom,board-id = <8 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sda429.dts b/qcom/sda429.dts new file mode 100644 index 00000000..dbc2e7da --- /dev/null +++ b/qcom/sda429.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sda429.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA429 CDP"; + compatible = "qcom,sda429-cdp", "qcom,sda429", "qcom,cdp"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/sda429.dtsi b/qcom/sda429.dtsi new file mode 100644 index 00000000..b1d8c977 --- /dev/null +++ b/qcom/sda429.dtsi @@ -0,0 +1,8 @@ +#include "sdm429.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA429"; + compatible = "qcom,sda429"; + qcom,msm-id = <364 0x0>; + qcom,msm-name = "SDA429"; +}; diff --git a/qcom/sda439-cdp.dts b/qcom/sda439-cdp.dts new file mode 100644 index 00000000..65606ba2 --- /dev/null +++ b/qcom/sda439-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sda439.dtsi" +#include "sdm439-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA439 CDP"; + compatible = "qcom,sda439-cdp", "qcom,sda439", "qcom,cdp"; + qcom,board-id = <1 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sda439-mtp.dts b/qcom/sda439-mtp.dts new file mode 100644 index 00000000..e68aa384 --- /dev/null +++ b/qcom/sda439-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sda439.dtsi" +#include "sdm439-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA439 MTP"; + compatible = "qcom,sda439-mtp", "qcom,sda439", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sda439.dts b/qcom/sda439.dts new file mode 100644 index 00000000..b20984dd --- /dev/null +++ b/qcom/sda439.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sda439.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA439"; + compatible = "qcom,sda439"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/sda439.dtsi b/qcom/sda439.dtsi new file mode 100644 index 00000000..179250bf --- /dev/null +++ b/qcom/sda439.dtsi @@ -0,0 +1,8 @@ +#include "sdm439.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA439"; + compatible = "qcom,sda439"; + qcom,msm-id = <363 0x0>; + qcom,msm-name = "SDA439"; +}; diff --git a/qcom/sdm429-cdp-overlay.dts b/qcom/sdm429-cdp-overlay.dts new file mode 100644 index 00000000..dfd4b9f1 --- /dev/null +++ b/qcom/sdm429-cdp-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm429-cdp.dtsi" + +/ { + model = "CDP"; + qcom,board-id = <1 3>; +}; diff --git a/qcom/sdm429-cdp.dts b/qcom/sdm429-cdp.dts new file mode 100644 index 00000000..0620e571 --- /dev/null +++ b/qcom/sdm429-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm429.dtsi" +#include "sdm429-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM429 CDP"; + compatible = "qcom,sdm429-cdp", "qcom,sdm429", "qcom,cdp"; + qcom,board-id = <1 3>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm429-cdp.dtsi b/qcom/sdm429-cdp.dtsi new file mode 100644 index 00000000..c40c41fe --- /dev/null +++ b/qcom/sdm429-cdp.dtsi @@ -0,0 +1,5 @@ +#include "sdm439-cdp.dtsi" + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>; +}; diff --git a/qcom/sdm429-cpu.dtsi b/qcom/sdm429-cpu.dtsi new file mode 100644 index 00000000..d1749dc7 --- /dev/null +++ b/qcom/sdm429-cpu.dtsi @@ -0,0 +1,149 @@ +/ { + /delete-node/ cpus; + /delete-node/ energy-costs; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + efficiency = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + /* A53 L2 dump not supported */ + qcom,dump-size = <0x0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + efficiency = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + efficiency = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + efficiency = <1024>; + sched-energy-costs = <&CPU_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + }; + + energy_costs: energy-costs { + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 960000 159 + 1305600 207 + 1497600 256 + 1708800 327 + 1804800 343 + 1958400 445 + 2016000 470 + >; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l2_dump0; + /delete-node/ qcom,l1_i_cache0; + /delete-node/ qcom,l1_i_cache1; + /delete-node/ qcom,l1_i_cache2; + /delete-node/ qcom,l1_i_cache3; + /delete-node/ qcom,l1_d_cache0; + /delete-node/ qcom,l1_d_cache1; + /delete-node/ qcom,l1_d_cache2; + /delete-node/ qcom,l1_d_cache3; + }; +}; diff --git a/qcom/sdm429-mtp-overlay.dts b/qcom/sdm429-mtp-overlay.dts new file mode 100644 index 00000000..af05bb54 --- /dev/null +++ b/qcom/sdm429-mtp-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm429-mtp.dtsi" + +/ { + model = "MTP"; + qcom,board-id = <8 2>; +}; diff --git a/qcom/sdm429-mtp.dts b/qcom/sdm429-mtp.dts new file mode 100644 index 00000000..a51f6aa4 --- /dev/null +++ b/qcom/sdm429-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm429.dtsi" +#include "sdm429-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM429 MTP"; + compatible = "qcom,sdm429-mtp", "qcom,sdm429", "qcom,mtp"; + qcom,board-id = <8 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm429-mtp.dtsi b/qcom/sdm429-mtp.dtsi new file mode 100644 index 00000000..0a637d0e --- /dev/null +++ b/qcom/sdm429-mtp.dtsi @@ -0,0 +1,5 @@ +#include "sdm439-mtp.dtsi" + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>; +}; diff --git a/qcom/sdm429-qrd-overlay.dts b/qcom/sdm429-qrd-overlay.dts new file mode 100644 index 00000000..7e4e5996 --- /dev/null +++ b/qcom/sdm429-qrd-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm429-qrd.dtsi" + +/ { + model = "QRD"; + qcom,board-id = <0xb 3>; +}; diff --git a/qcom/sdm429-qrd.dts b/qcom/sdm429-qrd.dts new file mode 100644 index 00000000..ff82315e --- /dev/null +++ b/qcom/sdm429-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm429.dtsi" +#include "sdm429-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM429 QRD"; + compatible = "qcom,sdm429-qrd", "qcom,sdm429", "qcom,qrd"; + qcom,board-id = <0xb 3>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm429-qrd.dtsi b/qcom/sdm429-qrd.dtsi new file mode 100644 index 00000000..8598b220 --- /dev/null +++ b/qcom/sdm429-qrd.dtsi @@ -0,0 +1,5 @@ +#include "sdm439-qrd.dtsi" + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>; +}; diff --git a/qcom/sdm429.dts b/qcom/sdm429.dts new file mode 100644 index 00000000..bd795bb0 --- /dev/null +++ b/qcom/sdm429.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdm429.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM429 MTP"; + compatible = "qcom,sdm429"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/sdm429.dtsi b/qcom/sdm429.dtsi new file mode 100644 index 00000000..6c42cd19 --- /dev/null +++ b/qcom/sdm429.dtsi @@ -0,0 +1,245 @@ +#include "sdm439.dtsi" +#include "sdm429-cpu.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM429"; + compatible = "qcom,sdm429"; + qcom,msm-id = <354 0x0>; +}; + +&soc { + /delete-node/ etm@619c000; + /delete-node/ etm@619d000; + /delete-node/ etm@619e000; + /delete-node/ etm@619f000; + /delete-node/ cti@6198000; + /delete-node/ cti@6199000; + /delete-node/ cti@619a000; + /delete-node/ cti@619b000; + /delete-node/ jtagmm@619c000; + /delete-node/ jtagmm@619d000; + /delete-node/ jtagmm@619e000; + /delete-node/ jtagmm@619f000; + + qcom,spm@b1d2000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0 { + /delete-node/qcom,pm-cluster@1; + }; + }; + + /delete-node/ qcom,msm-cpufreq; + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = + "l2_clk", + "cpu0_clk"; + /* TODO + * clocks = <&clock_cpu clk_cci_clk>, + * <&clock_cpu clk_a53_bc_clk>; + */ + + qcom,governor-per-policy; + + qcom,cpufreq-table = + < 960000 >, + < 1305600 >, + < 1497600 >, + < 1708800 >, + < 1804800 >, + < 1958400 >, + < 2016000 >; + }; + + /delete-node/ qcom,cpu0-cpugrp; + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1305600 MHZ_TO_MBPS(384, 8) >, + < 1804800 MHZ_TO_MBPS(557, 8) >; + }; + }; + + /delete-node/ qcom,cpu4-cpugrp; + +}; + +&funnel_apss { + ports { + /delete-node/ port@1; + /delete-node/ port@2; + /delete-node/ port@3; + /delete-node/ port@4; + }; +}; + +&thermal_zones { + hexa-cpu-max-step { + cooling-maps { + /delete-node/ cpu4_cdev; + /delete-node/ cpu5_cdev; + /delete-node/ cpu6_cdev; + /delete-node/ cpu7_cdev; + }; + }; + + /delete-node/ cpuss0-step; + + quiet-therm-step { + cooling-maps { + /delete-node/ skin_cpu4; + /delete-node/ skin_cpu5; + /delete-node/ skin_cpu6; + /delete-node/ skin_cpu7; + }; + }; +}; + +&gcc { + compatible = "qcom,gcc-sdm429"; + reg = <0x1800000 0x80000>, + <0xb016000 0x00040>; + reg-names = "cc_base", "apcs_c1_base"; + vdd_cx-supply = <&pm8953_s2_level>; + vdd_hf_dig-supply = <&pm8953_s2_level_ao>; + vdd_hf_pll-supply = <&pm8953_l7_ao>; +}; + +&debugcc { + compatible = "qcom,msm8937-debugcc"; + reg = <0x1874000 0x4>, + <0xb01101c 0x8>; + reg-names = "cc_base", "meas"; + #clock-cells = <1>; +}; + +&soc { + /delete-node/ qcom,cpu-clock-8939@b111050; + clock_cpu: qcom,cpu-clock-8939@b111050 { + compatible = "qcom,cpu-clock-sdm429"; + + reg = <0xb011050 0x8>, + <0xb1d1050 0x8>, + <0x00a412c 0x8>; + reg-names = "apcs-c1-rcg-base", + "apcs-cci-rcg-base", "efuse"; + + qcom,num-cluster; + vdd-c1-supply = <&apc_vreg_corner>; + vdd-cci-supply = <&apc_vreg_corner>; + + clocks = <&gcc GPLL0_AO_CLK_SRC>, + /* TODO + * <&gcc A53SS_C1_PLL TODO>, + */ + <&gcc GPLL0_AO_CLK_SRC>, + <&gcc GPLL0_AO_CLK_SRC>; + clock-names = "clk-c1-4", "clk-c1-5", + "clk-cci-4", "clk-cci-2"; + + qcom,speed0-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>; + + qcom,speed0-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed1-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1804800000 5>; + + qcom,speed1-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed4-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>, + < 2016000000 6>; + + qcom,speed4-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed5-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>; + + qcom,speed5-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + #clock-cells = <1>; + }; + + /* Disable secure_mem node */ + qcom,ion { + /delete-node/ qcom,ion-heap@8; + }; + /* delete hypervisor node for GPU*/ + /delete-node/ qcom,kgsl-hyp; +}; + +&secure_mem { + status = "disabled"; +}; + +&qseecom_ta_mem { + size = <0 0x400000>; +}; + +&gcc_mdss { + compatible = "qcom,gcc-mdss-sdm429"; + /* TODO + * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; + */ + clock-names = "pclk0_src", "byte0_src", "pclk1_src", + "byte1_src"; + #clock-cells = <1>; +}; + +/* GPU overrides */ +&msm_gpu { + /* Update GPU chip ID*/ + qcom,chipid = <0x05000400>; + + /* disable mem pools */ + /delete-node/qcom,gpu-mempools; +}; + +/* Disable secure context for Graphics*/ +&kgsl_msm_iommu { + /delete-node/ gfx3d_secure; +}; diff --git a/qcom/sdm439-audio.dtsi b/qcom/sdm439-audio.dtsi new file mode 100644 index 00000000..3f0e9e29 --- /dev/null +++ b/qcom/sdm439-audio.dtsi @@ -0,0 +1,142 @@ +&soc { + int_codec: sound { + qcom,model = "sdm439-snd-card-mtp"; + qcom,msm-hs-micbias-type = "internal"; + qcom,msm-micbias2-ext-cap; + + asoc-codec = <&stub_codec>, <&msm_digital_codec>, + <&pmic_analog_codec>; + asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec", + "analog-codec"; + msm-vdd-wsa-switch-supply = <&pm8953_l5>; + qcom,msm-vdd-wsa-switch-voltage = <1800000>; + qcom,msm-vdd-wsa-switch-current = <10000>; + }; + + clock_audio_native: audio_ext_clk_native { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + #clock-cells = <1>; + qcom,codec-mclk-clk-freq = <11289600>; + qcom,audio-ref-clk-gpio = <&tlmm 66 0>; + qcom,lpass-mclk-id = "pri_mclk"; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&cdc_mclk2_sleep>; + pinctrl-1 = <&cdc_mclk2_active>; + }; +}; + + +&clock_audio { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&tasha_mclk_default>; + pinctrl-1 = <&tasha_mclk_default>; + qcom,audio-ref-clk-gpio = <&pm8953_gpios 1 0>; +}; + +&wcd9335 { + cdc-vdd-buck-supply = <&dbu1>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&dbu1>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <150000>; + + cdc-vdd-tx-h-supply = <&dbu1>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&dbu1>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vdd-px-supply = <&dbu1>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <10000>; + + cdc-vdd-mic-bias-supply = <&pm8953_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <15000>; +}; + +&pm8953_gpios { + tasha_mclk { + tasha_mclk_default: tasha_mclk_default { + pins = "gpio1"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&pm8953_1 { + pmic_analog_codec: analog-codec@f000 { + status = "okay"; + compatible = "qcom,pmic-analog-codec"; + reg = <0xf000 0x200>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int", + "ear_ocp_int", + "hphr_ocp_int", + "hphl_ocp_det", + "ear_cnp_int", + "hphr_cnp_int", + "hphl_cnp_int"; + + cdc-vdda-cp-supply = <&pm8953_s4>; + qcom,cdc-vdda-cp-voltage = <1900000 2050000>; + qcom,cdc-vdda-cp-current = <500000>; + + cdc-vdd-io-supply = <&pm8953_l5>; + qcom,cdc-vdd-io-voltage = <1800000 1800000>; + qcom,cdc-vdd-io-current = <5000>; + + cdc-vdd-pa-supply = <&pm8953_s4>; + qcom,cdc-vdd-pa-voltage = <1900000 2050000>; + qcom,cdc-vdd-pa-current = <260000>; + + cdc-vdd-mic-bias-supply = <&pm8953_l13>; + qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>; + qcom,cdc-vdd-mic-bias-current = <5000>; + + qcom,cdc-mclk-clk-rate = <9600000>; + + qcom,cdc-static-supplies = "cdc-vdd-io", + "cdc-vdd-pa", + "cdc-vdda-cp"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + + msm_digital_codec: msm-dig-codec { + compatible = "qcom,msm-digital-codec"; + reg = <0xc0f0000 0x0>; + }; + }; +}; diff --git a/qcom/sdm439-camera-sensor-cdp.dtsi b/qcom/sdm439-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..6e93d685 --- /dev/null +++ b/qcom/sdm439-camera-sensor-cdp.dtsi @@ -0,0 +1,316 @@ +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include <dt-bindings/clock/qcom,rpmcc.h> + +&cci { + #address-cells = <1>; + #size-cells = <0>; + + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + qcom,cci-master = <0>; + reg = <0x0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", + "cam_vio", "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + qcom,eeprom-name = "sunny_8865"; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0x6c>; + qcom,cci-master = <0>; + qcom,num-blocks = <8>; + + qcom,page0 = <1 0x0100 2 0x01 1 1>; + qcom,poll0 = <0 0x0 2 0x0 1 0>; + qcom,mem0 = <0 0x0 2 0x0 1 0>; + + qcom,page1 = <1 0x5002 2 0x00 1 0>; + qcom,poll1 = <0 0x0 2 0x0 1 0>; + qcom,mem1 = <0 0x0 2 0x0 1 0>; + + qcom,page2 = <1 0x3d84 2 0xc0 1 0>; + qcom,poll2 = <0 0x0 2 0x0 1 0>; + qcom,mem2 = <0 0x0 2 0x0 1 0>; + + qcom,page3 = <1 0x3d88 2 0x70 1 0>; + qcom,poll3 = <0 0x0 2 0x0 1 0>; + qcom,mem3 = <0 0x0 2 0x0 1 0>; + + qcom,page4 = <1 0x3d89 2 0x10 1 0>; + qcom,poll4 = <0 0x0 2 0x0 1 0>; + qcom,mem4 = <0 0x0 2 0x0 1 0>; + + qcom,page5 = <1 0x3d8a 2 0x70 1 0>; + qcom,poll5 = <0 0x0 2 0x0 1 0>; + qcom,mem5 = <0 0x0 2 0x0 1 0>; + + qcom,page6 = <1 0x3d8b 2 0xf4 1 0>; + qcom,poll6 = <0 0x0 2 0x0 1 0>; + qcom,mem6 = <0 0x0 2 0x0 1 0>; + + qcom,page7 = <1 0x3d81 2 0x01 1 10>; + qcom,poll7 = <0 0x0 2 0x0 1 1>; + qcom,mem7 = <1536 0x7010 2 0 1 0>; + + cam_vdig-supply = <&pm8953_l23>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", + "sensor_vreg", + "sensor_gpio", "sensor_gpio" , "sensor_clk"; + qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio", + "sensor_gpio_reset", "sensor_gpio_standby", + "sensor_cam_mclk"; + qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>; + qcom,cam-power-seq-delay = <1 1 1 30 30 5>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + qcom,cci-master = <1>; + reg = <0x2>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = </*&led_flash0 TODO*/>; + qcom,eeprom-src = <&eeprom0>; + qcom,actuator-src = <&actuator0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", + "cam_vio", "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_default + &cam_sensor_front_default>; + pinctrl-1 = <&cam_sensor_mclk1_sleep + &cam_sensor_front_sleep>; + gpios = <&tlmm 27 0>, + <&tlmm 38 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_STANDBY1"; + qcom,sensor-position = <0x100>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + clocks = <&gcc MCLK1_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom2>; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; diff --git a/qcom/sdm439-camera-sensor-mtp.dtsi b/qcom/sdm439-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..6e93d685 --- /dev/null +++ b/qcom/sdm439-camera-sensor-mtp.dtsi @@ -0,0 +1,316 @@ +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include <dt-bindings/clock/qcom,rpmcc.h> + +&cci { + #address-cells = <1>; + #size-cells = <0>; + + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + qcom,cci-master = <0>; + reg = <0x0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", + "cam_vio", "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + qcom,eeprom-name = "sunny_8865"; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0x6c>; + qcom,cci-master = <0>; + qcom,num-blocks = <8>; + + qcom,page0 = <1 0x0100 2 0x01 1 1>; + qcom,poll0 = <0 0x0 2 0x0 1 0>; + qcom,mem0 = <0 0x0 2 0x0 1 0>; + + qcom,page1 = <1 0x5002 2 0x00 1 0>; + qcom,poll1 = <0 0x0 2 0x0 1 0>; + qcom,mem1 = <0 0x0 2 0x0 1 0>; + + qcom,page2 = <1 0x3d84 2 0xc0 1 0>; + qcom,poll2 = <0 0x0 2 0x0 1 0>; + qcom,mem2 = <0 0x0 2 0x0 1 0>; + + qcom,page3 = <1 0x3d88 2 0x70 1 0>; + qcom,poll3 = <0 0x0 2 0x0 1 0>; + qcom,mem3 = <0 0x0 2 0x0 1 0>; + + qcom,page4 = <1 0x3d89 2 0x10 1 0>; + qcom,poll4 = <0 0x0 2 0x0 1 0>; + qcom,mem4 = <0 0x0 2 0x0 1 0>; + + qcom,page5 = <1 0x3d8a 2 0x70 1 0>; + qcom,poll5 = <0 0x0 2 0x0 1 0>; + qcom,mem5 = <0 0x0 2 0x0 1 0>; + + qcom,page6 = <1 0x3d8b 2 0xf4 1 0>; + qcom,poll6 = <0 0x0 2 0x0 1 0>; + qcom,mem6 = <0 0x0 2 0x0 1 0>; + + qcom,page7 = <1 0x3d81 2 0x01 1 10>; + qcom,poll7 = <0 0x0 2 0x0 1 1>; + qcom,mem7 = <1536 0x7010 2 0 1 0>; + + cam_vdig-supply = <&pm8953_l23>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", + "sensor_vreg", + "sensor_gpio", "sensor_gpio" , "sensor_clk"; + qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio", + "sensor_gpio_reset", "sensor_gpio_standby", + "sensor_cam_mclk"; + qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>; + qcom,cam-power-seq-delay = <1 1 1 30 30 5>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + qcom,cci-master = <1>; + reg = <0x2>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = </*&led_flash0 TODO*/>; + qcom,eeprom-src = <&eeprom0>; + qcom,actuator-src = <&actuator0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", + "cam_vio", "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_default + &cam_sensor_front_default>; + pinctrl-1 = <&cam_sensor_mclk1_sleep + &cam_sensor_front_sleep>; + gpios = <&tlmm 27 0>, + <&tlmm 38 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_STANDBY1"; + qcom,sensor-position = <0x100>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + clocks = <&gcc MCLK1_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom2>; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; diff --git a/qcom/sdm439-camera-sensor-qrd.dtsi b/qcom/sdm439-camera-sensor-qrd.dtsi new file mode 100644 index 00000000..7883909d --- /dev/null +++ b/qcom/sdm439-camera-sensor-qrd.dtsi @@ -0,0 +1,280 @@ +#include <dt-bindings/clock/qcom,gcc-sdm429w.h> +#include <dt-bindings/clock/qcom,rpmcc.h> + +&cci { + #address-cells = <1>; + #size-cells = <0>; + + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2850000>; + qcom,cam-vreg-max-voltage = <2850000>; + qcom,cam-vreg-op-mode = <80000>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + qcom,cci-master = <0>; + reg = <0x0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", "cam_vio", + "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + qcom,eeprom-name = "sunny_8865"; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0x6c>; + qcom,cci-master = <0>; + qcom,num-blocks = <8>; + + qcom,page0 = <1 0x0100 2 0x01 1 1>; + qcom,poll0 = <0 0x0 2 0x0 1 0>; + qcom,mem0 = <0 0x0 2 0x0 1 0>; + + qcom,page1 = <1 0x5002 2 0x00 1 0>; + qcom,poll1 = <0 0x0 2 0x0 1 0>; + qcom,mem1 = <0 0x0 2 0x0 1 0>; + + qcom,page2 = <1 0x3d84 2 0xc0 1 0>; + qcom,poll2 = <0 0x0 2 0x0 1 0>; + qcom,mem2 = <0 0x0 2 0x0 1 0>; + + qcom,page3 = <1 0x3d88 2 0x70 1 0>; + qcom,poll3 = <0 0x0 2 0x0 1 0>; + qcom,mem3 = <0 0x0 2 0x0 1 0>; + + qcom,page4 = <1 0x3d89 2 0x10 1 0>; + qcom,poll4 = <0 0x0 2 0x0 1 0>; + qcom,mem4 = <0 0x0 2 0x0 1 0>; + + qcom,page5 = <1 0x3d8a 2 0x70 1 0>; + qcom,poll5 = <0 0x0 2 0x0 1 0>; + qcom,mem5 = <0 0x0 2 0x0 1 0>; + + qcom,page6 = <1 0x3d8b 2 0xf4 1 0>; + qcom,poll6 = <0 0x0 2 0x0 1 0>; + qcom,mem6 = <0 0x0 2 0x0 1 0>; + + qcom,page7 = <1 0x3d81 2 0x01 1 10>; + qcom,poll7 = <0 0x0 2 0x0 1 1>; + qcom,mem7 = <1536 0x7010 2 0 1 0>; + + cam_vdig-supply = <&pm8953_l23>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", + "cam_vana", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg", + "sensor_vreg", + "sensor_gpio", "sensor_gpio" , "sensor_clk"; + qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio", + "sensor_gpio_reset", "sensor_gpio_standby", + "sensor_cam_mclk"; + qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>; + qcom,cam-power-seq-delay = <1 1 1 30 30 5>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <19200000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,led-flash-src = </*&led_flash0 TODO*/>; + qcom,eeprom-src = <&eeprom0>; + qcom,actuator-src = <&actuator0>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + cam_vdig-supply = <&pm8953_l3>; + qcom,cam-vreg-name = "cam_vana", "cam_vio", + "cam_vdig", "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>; + qcom,cam-vreg-op-mode = <80000 0 200000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_default + &cam_sensor_rear_reset + &cam_sensor_rear_vana>; + pinctrl-1 = <&cam_sensor_mclk0_sleep + &cam_sensor_rear_reset_sleep + &cam_sensor_rear_vana_sleep>; + gpios = <&tlmm 26 0>, + <&tlmm 36 0>, + <&tlmm 35 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&gcc MCLK0_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <200000 0 80000 100000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_default + &cam_sensor_front_default>; + pinctrl-1 = <&cam_sensor_mclk1_sleep + &cam_sensor_front_sleep>; + gpios = <&tlmm 27 0>, + <&tlmm 38 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_STANDBY1"; + qcom,sensor-position = <0x100>; + qcom,sensor-mode = <1>; + qcom,cci-master = <1>; + clocks = <&gcc MCLK1_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <270>; + qcom,eeprom-src = <&eeprom1>; + qcom,actuator-src = <&actuator1>; + cam_vdig-supply = <&pm8953_l3>; + cam_vana-supply = <&pm8953_l22>; + cam_vio-supply = <&pm8953_l6>; + cam_vaf-supply = <&pm8953_l17>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana", + "cam_vaf"; + qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>; + qcom,cam-vreg-op-mode = <105000 0 80000 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_default + &cam_sensor_front1_default>; + pinctrl-1 = <&cam_sensor_mclk2_sleep + &cam_sensor_front1_sleep>; + gpios = <&tlmm 27 0>, + <&tlmm 38 0>, + <&tlmm 39 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_STANDBY2"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&gcc MCLK2_CLK_SRC>, + <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; diff --git a/qcom/sdm439-cdp-overlay.dts b/qcom/sdm439-cdp-overlay.dts new file mode 100644 index 00000000..fcd65e65 --- /dev/null +++ b/qcom/sdm439-cdp-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm439-cdp.dtsi" + +/ { + model = "CDP"; + qcom,board-id = <1 2>; +}; diff --git a/qcom/sdm439-cdp.dts b/qcom/sdm439-cdp.dts new file mode 100644 index 00000000..899cac7d --- /dev/null +++ b/qcom/sdm439-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm439.dtsi" +#include "sdm439-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 CDP"; + compatible = "qcom,sdm439-cdp", "qcom,sdm439", "qcom,cdp"; + qcom,board-id = <1 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm439-cdp.dtsi b/qcom/sdm439-cdp.dtsi new file mode 100644 index 00000000..66621782 --- /dev/null +++ b/qcom/sdm439-cdp.dtsi @@ -0,0 +1,586 @@ +#include "sdm439-camera-sensor-cdp.dtsi" + +&blsp1_uart2 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8953_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio2"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&i2c_5 { /* BLSP2 QUP1 (NFC) */ + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 17 0x00>; + qcom,nq-ven = <&tlmm 16 0x00>; + qcom,nq-firm = <&tlmm 130 0x00>; + qcom,nq-clkreq = <&pm8953_gpios 2 0x00>; + qcom,nq-esepwr = <&tlmm 93 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK2"; + interrupts = <17 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_disable_active + &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>; + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + clock-names = "ref_clk"; + }; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm8953_l8>; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l5>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm8953_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 800000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l12>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 67 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_active>; + + camera_focus { + label = "camera_focus"; + gpios = <&tlmm 128 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&tlmm 127 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + vol_up { + label = "volume_up"; + gpios = <&tlmm 91 0x1>; + linux,input-type = <1>; + linux,code = <115>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&pm8953_gpios { + bklt_en { + bklt_en_default: bklt_en_default { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-high; + }; + }; +}; + +&cdc_pdm_lines_2_act { + mux { + pins = "gpio70", "gpio71", "gpio72"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio70", "gpio71", "gpio72"; + drive-strength = <16>; + }; +}; + +&cdc_pdm_lines_act { + mux { + pins = "gpio69", "gpio73", "gpio74"; + function = "cdc_pdm0"; + }; + + config { + pins = "gpio69", "gpio73", "gpio74"; + drive-strength = <16>; + }; +}; + +&pm8953_pwm { + status = "ok"; +}; + +#include "msm8937-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active &bklt_en_default>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-bklight-en-gpio = <&pm8953_gpios 4 0>; + qcom,platform-te-gpio = <&tlmm 24 0>; + qcom,platform-reset-gpio = <&tlmm 60 0>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; + +&mdss_dsi1 { + status = "disabled"; +}; + +&dsi_hx8399c_truly_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + + +&dsi_hx8399c_hd_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 + 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-max-error-count = <3>; + /delete-node/ qcom,mdss-dsi-display-timings; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 03 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 + 14 00 02 28 00 05 01 00 00 78 00 + 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + /delete-node/ qcom,mdss-dsi-display-timings; +}; + +&dsi_truly_1080_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_truly_1080_cmd { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; diff --git a/qcom/sdm439-ext-audio-mtp.dtsi b/qcom/sdm439-ext-audio-mtp.dtsi new file mode 100644 index 00000000..2d53e873 --- /dev/null +++ b/qcom/sdm439-ext-audio-mtp.dtsi @@ -0,0 +1,64 @@ +&int_codec { + status = "disabled"; +}; + +&wsa881x_i2c_f { + status = "disabled"; +}; + +&wsa881x_i2c_45 { + status = "disabled"; +}; + +&cdc_pri_mi2s_gpios { + status = "disabled"; +}; + +&wsa881x_analog_vi_gpio { + status = "disabled"; +}; + +&wsa881x_analog_clk_gpio { + status = "disabled"; +}; + +&wsa881x_analog_reset_gpio { + status = "disabled"; +}; + +&slim_msm { + status = "okay"; +}; + +&dai_slim { + status = "okay"; +}; + +&wcd9xxx_intc { + status = "okay"; +}; + +&clock_audio { + status = "okay"; +}; + +&wcd9335 { + status = "okay"; +}; + +&cdc_us_euro_sw { + status = "okay"; +}; + +&cdc_quin_mi2s_gpios { + status = "okay"; +}; + +&wcd_rst_gpio { + status = "okay"; +}; + +&ext_codec { + status = "okay"; +}; + diff --git a/qcom/sdm439-external-codec-mtp-overlay.dts b/qcom/sdm439-external-codec-mtp-overlay.dts new file mode 100644 index 00000000..58abc6ed --- /dev/null +++ b/qcom/sdm439-external-codec-mtp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sdm439-mtp.dtsi" +#include "sdm439-external-codec.dtsi" + +/ { + model = "MTP"; + qcom,board-id = <8 3>; + qcom,msm-id = <353 0x0>; +}; diff --git a/qcom/sdm439-external-codec-mtp.dts b/qcom/sdm439-external-codec-mtp.dts new file mode 100644 index 00000000..056d78f9 --- /dev/null +++ b/qcom/sdm439-external-codec-mtp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sdm439.dtsi" +#include "sdm439-mtp.dtsi" +#include "sdm439-external-codec.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 Audio Codec MTP"; + compatible = "qcom,sdm439-mtp", "qcom,sdm439", "qcom,mtp"; + qcom,board-id = <8 3>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm439-external-codec.dtsi b/qcom/sdm439-external-codec.dtsi new file mode 100644 index 00000000..24e20690 --- /dev/null +++ b/qcom/sdm439-external-codec.dtsi @@ -0,0 +1 @@ +#include "sdm439-ext-audio-mtp.dtsi" diff --git a/qcom/sdm439-mtp-overlay.dts b/qcom/sdm439-mtp-overlay.dts new file mode 100644 index 00000000..73f9f6e3 --- /dev/null +++ b/qcom/sdm439-mtp-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm439-mtp.dtsi" + +/ { + model = "MTP"; + qcom,board-id = <8 1>; +}; diff --git a/qcom/sdm439-mtp.dts b/qcom/sdm439-mtp.dts new file mode 100644 index 00000000..da296b0b --- /dev/null +++ b/qcom/sdm439-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm439.dtsi" +#include "sdm439-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 MTP"; + compatible = "qcom,sdm439-mtp", "qcom,sdm439", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm439-mtp.dtsi b/qcom/sdm439-mtp.dtsi new file mode 100644 index 00000000..6b55c243 --- /dev/null +++ b/qcom/sdm439-mtp.dtsi @@ -0,0 +1,628 @@ +#include "sdm439-camera-sensor-mtp.dtsi" + +&blsp1_uart2 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8953_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio2"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&i2c_5 { /* BLSP2 QUP1 (NFC) */ + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 17 0x00>; + qcom,nq-ven = <&tlmm 16 0x00>; + qcom,nq-firm = <&tlmm 130 0x00>; + qcom,nq-clkreq = <&pm8953_gpios 2 0x00>; + qcom,nq-esepwr = <&tlmm 93 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK2"; + interrupts = <17 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_disable_active + &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>; + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + clock-names = "ref_clk"; + }; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm8953_l8>; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l5>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm8953_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 800000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l12>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 67 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_active>; + + camera_focus { + label = "camera_focus"; + gpios = <&tlmm 128 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&tlmm 127 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + vol_up { + label = "volume_up"; + gpios = <&tlmm 91 0x1>; + linux,input-type = <1>; + linux,code = <115>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +#include "msm8937-mdss-panels.dtsi" + +&pm8953_gpios { + bklt_en { + bklt_en_default: bklt_en_default { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-high; + }; + }; +}; + +&pm8953_pwm { + status = "ok"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active &bklt_en_default>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-bklight-en-gpio = <&pm8953_gpios 4 0>; + qcom,platform-te-gpio = <&tlmm 24 0>; + qcom,platform-reset-gpio = <&tlmm 60 0>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; +}; + +&mdss_dsi1 { + status = "disabled"; +}; + +&dsi_hx8399c_truly_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + +&dsi_hx8399c_hd_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 + 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-max-error-count = <3>; + /delete-node/ qcom,mdss-dsi-display-timings; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 03 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 + 14 00 02 28 00 05 01 00 00 78 00 + 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + /delete-node/ qcom,mdss-dsi-display-timings; +}; + +&dsi_truly_1080_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_truly_1080_cmd { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&i2c_2 { +#address-cells = <1>; +#size-cells = <0>; + +#include "smb1355.dtsi" +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default + &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + smb1355_charger_0: qcom,smb1355-charger@1000 { + status ="ok"; + /delete-property/ io-channels; + /delete-property/ io-channels-names; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + }; +}; diff --git a/qcom/sdm439-pm8953.dtsi b/qcom/sdm439-pm8953.dtsi new file mode 100644 index 00000000..7dad3778 --- /dev/null +++ b/qcom/sdm439-pm8953.dtsi @@ -0,0 +1,326 @@ +&rpm_bus { + /* Deleting all pm8937 regulators */ + /delete-node/ rpm-regulator-smpa1; + /delete-node/ rpm-regulator-smpa2; + /delete-node/ rpm-regulator-smpa3; + /delete-node/ rpm-regulator-smpa4; + /delete-node/ rpm-regulator-ldoa2; + /delete-node/ rpm-regulator-ldoa3; + /delete-node/ rpm-regulator-ldoa5; + /delete-node/ rpm-regulator-ldoa6; + /delete-node/ rpm-regulator-ldoa7; + /delete-node/ rpm-regulator-ldoa8; + /delete-node/ rpm-regulator-ldoa9; + /delete-node/ rpm-regulator-ldoa10; + /delete-node/ rpm-regulator-ldoa11; + /delete-node/ rpm-regulator-ldoa12; + /delete-node/ rpm-regulator-ldoa13; + /delete-node/ rpm-regulator-ldoa14; + /delete-node/ rpm-regulator-ldoa15; + /delete-node/ rpm-regulator-ldoa16; + /delete-node/ rpm-regulator-ldoa17; + /delete-node/ rpm-regulator-ldoa19; + /delete-node/ rpm-regulator-ldoa22; + /delete-node/ rpm-regulator-ldoa23; +}; + +&spmi_bus { + /delete-node/ qcom,pm8937@0; + /delete-node/ qcom,pm8937@1; +}; + +&thermal_zones { + /delete-node/ pa-therm1-adc; + /delete-node/ xo-therm-adc; + /delete-node/ xo-therm-buf-adc; + /delete-node/ case-therm-adc; + /delete-node/ pa-therm0-adc; + /delete-node/ pm8937_tz; +}; + +&int_codec { + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + /delete-property/ msm-vdd-wsa-switch-supply; +}; + +&clock_audio { + /delete-property/ qcom,audio-ref-clk-gpio; +}; + +&wcd9335 { + /delete-property/ cdc-vdd-buck-supply; + /delete-property/ cdc-buck-sido-supply; + /delete-property/ cdc-vdd-tx-h-supply; + /delete-property/ cdc-vdd-rx-h-supply; + /delete-property/ cdc-vdd-px-supply; + /delete-property/ cdc-vdd-mic-bias-supply; +}; + +&soc { + /delete-node/ regulator@01946004; + /delete-node/ regulator@b018000; + /delete-node/ eldo2; + /delete-node/ adv_vreg; + + qcom,gcc@1800000 { + /delete-property/ vdd_cx-supply; + /delete-property/ vdd_sr2_dig-supply; + /delete-property/ vdd_sr2_pll-supply; + /delete-property/ vdd_hf_dig-supply; + /delete-property/ vdd_hf_pll-supply; + vdd_cx-supply = <&pm8953_s2_level>; + vdd_sr2_dig-supply = <&pm8953_s2_level_ao>; + vdd_sr2_pll-supply = <&pm8953_l7_ao>; + vdd_hf_dig-supply = <&pm8953_s2_level_ao>; + vdd_hf_pll-supply = <&pm8953_l7_ao>; + }; + + qcom,cpu-clock-8939@b111050 { + /delete-property/ vdd-c0-supply; + /delete-property/ vdd-c1-supply; + /delete-property/ vdd-cci-supply; + }; + + qcom,lpass@c200000 { + /delete-property/ vdd_cx-supply; + }; + + qcom,pronto@a21b000 { + /delete-property/ vdd_pronto_pll-supply; + }; + + qcom,wcnss-wlan@0a000000 { + /delete-property/ qcom,pronto-vddmx-supply; + /delete-property/ qcom,pronto-vddcx-supply; + /delete-property/ qcom,pronto-vddpx-supply; + /delete-property/ qcom,iris-vddxo-supply; + /delete-property/ qcom,iris-vddrfa-supply; + /delete-property/ qcom,iris-vddpa-supply; + /delete-property/ qcom,iris-vdddig-supply; + /delete-property/ qcom,wcnss-adc_tm; + }; +}; + +&pil_mss { + /delete-property/ vdd_mss-supply; + /delete-property/ vdd_cx-supply; + /delete-property/ vdd_cx-voltage; + /delete-property/ vdd_mx-supply; + /delete-property/ vdd_mx-uV; + /delete-property/ vdd_pll-supply; +}; + +&mdss_dsi { + vdda-supply = <&pm8953_l23>; + vddio-supply = <&pm8953_l5>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda"; + qcom,supply-min-voltage = <800000>; + qcom,supply-max-voltage = <800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; +}; + +&usb_otg { + hsusb_vdd_dig-supply = <&pm8953_l23>; + HSUSB_1p8-supply = <&pm8953_l7>; + HSUSB_3p3-supply = <&pm8953_l13>; + qcom,vdd-voltage-level = <0 800000 800000>; +}; + +&mdss_dsi0_pll { + vddio-supply = <&pm8953_l6>; +}; + +&mdss_dsi1_pll { + vddio-supply = <&pm8953_l6>; +}; + +&mdss_dsi0 { + vdd-supply = <&pm8953_l17>; + vddio-supply = <&pm8953_l6>; +}; + +&mdss_dsi1 { + status = "disabled"; + vdd-supply = <&pm8953_l17>; + vddio-supply = <&pm8953_l6>; +}; + +&int_codec { + /delete-property/ asoc-codec; + /delete-property/ msm-vdd-wsa-switch-supply; +}; + +&clock_audio { + /delete-property/ qcom,audio-ref-clk-gpio; +}; + +&wcd9335 { + /delete-property/ cdc-vdd-buck-supply; + /delete-property/ cdc-buck-sido-supply; + /delete-property/ cdc-vdd-tx-h-supply; + /delete-property/ cdc-vdd-rx-h-supply; + /delete-property/ cdc-vdd-px-supply; + /delete-property/ cdc-vdd-mic-bias-supply; +}; + +#include "pm8953.dtsi" +#include "pm8953-rpm-regulator.dtsi" +#include "sdm439-regulator.dtsi" + +&thermal_zones { + aoss0-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + mdm-core-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + lpass-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + camera-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + cpuss1-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + apc1-cpu0-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + apc1-cpu1-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + apc1-cpu2-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + apc1-cpu3-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + cpuss0-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + gpu-lowf { + cooling-maps { + cx_vdd_cdev { + cooling-device = <&pm8953_cx_cdev 0 0>; + }; + }; + }; + + pa-therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8953_adc_tm 0x36>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; + +&pm8953_vadc { + pinctrl-0 = <&pa_therm1_default>; + /delete-node/ chan@13; +}; + +&pm8953_mpps { + /delete-node/ case_therm; +}; + +&pil_mss { + vdd_mss-supply = <&pm8953_s1>; + vdd_cx-supply = <&pm8953_s2_level>; + vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_mx-supply = <&pm8953_s7_level_ao>; + vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + vdd_pll-supply = <&pm8953_l7>; +}; + +&soc { + qcom,lpass@c200000 { + vdd_cx-supply = <&pm8953_s2_level>; + }; + + qcom,pronto@a21b000 { + vdd_pronto_pll-supply = <&pm8953_l7>; + }; + + qcom,wcnss-wlan@0a000000 { + qcom,pronto-vddmx-supply = <&pm8953_s7_level_ao>; + qcom,pronto-vddcx-supply = <&pm8953_s2_level>; + qcom,pronto-vddpx-supply = <&pm8953_l5>; + qcom,iris-vddxo-supply = <&pm8953_l7>; + qcom,iris-vddrfa-supply = <&pm8953_l19>; + qcom,iris-vddpa-supply = <&pm8953_l9>; + qcom,iris-vdddig-supply = <&pm8953_l5>; + qcom,wcnss-adc_tm = <&pm8953_adc_tm>; + }; +}; + diff --git a/qcom/sdm439-pmi632.dtsi b/qcom/sdm439-pmi632.dtsi new file mode 100644 index 00000000..ab4b1a6c --- /dev/null +++ b/qcom/sdm439-pmi632.dtsi @@ -0,0 +1,341 @@ +#include "pmi632.dtsi" + +&pmi632_charger { + dpdm-supply = <&usb_otg>; +}; + +&usb_otg { + vbus_otg-supply = <&smb5_vbus>; + extcon = <&pmi632_charger>; +}; + +&pmi632_pon { + qcom,ps-hold-hard-reset-disable; + qcom,ps-hold-shutdown-disable; +}; + +/ { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&quiet_therm_default &smb_therm_default>; +}; + +&pmi632_gpios { + quiet_therm { + quiet_therm_default: quiet_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + smb_therm { + smb_therm_default: smb_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; +}; + +&pm8953_typec { + status = "disabled"; +}; + +&thermal_zones { + pmi-vbat-lvl0 { + cooling-maps { + vbat_map0 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_map1 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_map2 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + vbat_map3 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soc_map0 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + soc_map1 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + soc_map2 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + soc_map3 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + }; + }; + + quiet-therm-step { + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm 0x53>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + quiet_batt_439_trip1: quiet-batt-trip1 { + temperature = <38000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_439_trip2: quiet-batt-trip2 { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_439_trip3: quiet-batt-trip3 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_439_trip4: quiet-batt-trip4 { + temperature = <44000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_modem_439_trip1: quiet-modem-trip0 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_modem_439_trip2: quiet-modem-trip1 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_batt_439_trip5: quiet-batt-trip5 { + temperature = <46000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_439_batt_trip6_mdm_trip3: quiet-bt-trp6-mdm-trp3 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_cpus_439_trip: quiet-cpus-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_gpu_439_trip: quiet-gpu-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_batt_439_trip7: quiet-batt-trip7 { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_modem_439_trip4: quiet-modem-trip3 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + skin_cpu0 { + trip = <&quiet_cpus_439_trip>; + /* throttle from fmax to 1497600KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu1 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu2 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu3 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu4 { + trip = <&quiet_cpus_439_trip>; + /* throttle from fmax to 1171200KHz */ + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu5 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu6 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_cpu7 { + trip = <&quiet_cpus_439_trip>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + + skin_gpu { + trip = <&quiet_gpu_439_trip>; + /* throttle from fmax to 510000000Hz */ + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>; + }; + + modem_proc_lvl1 { + trip = <&quiet_modem_439_trip1>; + cooling-device = <&modem_proc 1 1>; + }; + + modem_proc_lvl2 { + trip = <&quiet_modem_439_trip4>; + cooling-device = <&modem_proc 3 3>; + }; + + modem_lvl1 { + trip = <&quiet_modem_439_trip2>; + cooling-device = <&modem_pa 1 1>; + }; + + modem_lvl2 { + trip = <&quiet_439_batt_trip6_mdm_trip3>; + cooling-device = <&modem_pa 2 2>; + }; + + modem_lvl3 { + trip = <&quiet_modem_439_trip4>; + cooling-device = <&modem_pa 3 3>; + }; + + battery_lvl1 { + trip = <&quiet_batt_439_trip1>; + cooling-device = <&pmi632_charger 1 1>; + }; + + battery_lvl2 { + trip = <&quiet_batt_439_trip2>; + cooling-device = <&pmi632_charger 2 2>; + }; + + battery_lvl3 { + trip = <&quiet_batt_439_trip3>; + cooling-device = <&pmi632_charger 3 3>; + }; + + battery_lvl4 { + trip = <&quiet_batt_439_trip4>; + cooling-device = <&pmi632_charger 4 4>; + }; + + battery_lvl5 { + trip = <&quiet_batt_439_trip5>; + cooling-device = <&pmi632_charger 5 5>; + }; + + battery_lvl6 { + trip = <&quiet_439_batt_trip6_mdm_trip3>; + cooling-device = <&pmi632_charger 6 6>; + }; + + battery_lvl7 { + trip = <&quiet_batt_439_trip7>; + cooling-device = <&pmi632_charger 7 7>; + }; + + }; + }; + + quiet-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm 0x53>; + thermal-governor = "user_space"; + wake-capable-sensor; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/sdm439-qrd-overlay.dts b/qcom/sdm439-qrd-overlay.dts new file mode 100644 index 00000000..e8729f8f --- /dev/null +++ b/qcom/sdm439-qrd-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm439-qrd.dtsi" + +/ { + model = "QRD"; + qcom,board-id = <0xb 2>; +}; diff --git a/qcom/sdm439-qrd.dts b/qcom/sdm439-qrd.dts new file mode 100644 index 00000000..792d66c9 --- /dev/null +++ b/qcom/sdm439-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm439.dtsi" +#include "sdm439-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 QRD"; + compatible = "qcom,sdm439-qrd", "qcom,sdm439", "qcom,qrd"; + qcom,board-id = <0xb 2>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm439-qrd.dtsi b/qcom/sdm439-qrd.dtsi new file mode 100644 index 00000000..f2bdd844 --- /dev/null +++ b/qcom/sdm439-qrd.dtsi @@ -0,0 +1,418 @@ +#include "msm8937-mdss-panels.dtsi" +#include "sdm439-camera-sensor-qrd.dtsi" + +&blsp1_uart2 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm8953_l8>; + qcom,vdd-voltage-level = <2900000 2900000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l5>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&int_codec { + status = "okay"; + qcom,model = "sdm439-sku1-snd-card"; + qcom,msm-micbias1-ext-cap; + qcom,msm-micbias2-ext-cap; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,msm-hs-micbias-type = "external"; + /delete-property/ qcom,quin-mi2s-gpios; +}; + +&cdc_quin_mi2s_gpios { + status = "disabled"; +}; + +&wsa881x_i2c_f { + status = "okay"; +}; + +&wsa881x_i2c_45 { + status = "okay"; +}; + +&pm8953_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio2"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&i2c_5 { /* BLSP2 QUP1 (NFC) */ + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 17 0x00>; + qcom,nq-ven = <&tlmm 16 0x00>; + qcom,nq-firm = <&tlmm 130 0x00>; + qcom,nq-clkreq = <&pm8953_gpios 2 0x00>; + qcom,nq-esepwr = <&tlmm 93 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK2"; + interrupts = <17 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_disable_active + &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>; + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + clock-names = "ref_clk"; + }; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm8953_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 800000>; + + /* device communication power supply */ + vdd-io-supply = <&pm8953_l12>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 67 0x0>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + +&soc { + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_active>; + + vol_up: vol_up { + label = "volume_up"; + gpios = <&tlmm 91 0x1>; + linux,input-type = <1>; + linux,code = <115>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + fpc1020 { + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <48 0>; /* TBD */ + fpc,gpio_rst = <&tlmm 124 0x0>; + fpc,gpio_irq = <&tlmm 48 0>; + vcc_spi-supply = <&pm8953_l5>; + vdd_io-supply = <&pm8953_l5>; + vdd_ana-supply = <&pm8953_l5>; + fpc,enable-on-boot; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + pinctrl-0 = <&fpc_reset_low>; + pinctrl-1 = <&fpc_reset_high>; + pinctrl-2 = <&fpc_int_low>; + }; +}; + +&tlmm { + pmx_ts_rst_active { + ts_rst_active: ts_rst_active { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + pmx_ts_rst_suspend { + ts_rst_suspend: ts_rst_suspend { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; + +&soc { + hbtp { + compatible = "qcom,hbtp-input"; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_rst_active>; + pinctrl-1 = <&ts_rst_suspend>; + vcc_ana-supply = <&pm8953_l10>; + vcc_dig-supply = <&pm8953_l5>; + qcom,afe-load = <20000>; + qcom,afe-vtg-min = <3000000>; + qcom,afe-vtg-max = <3000000>; + qcom,dig-load = <40000>; + qcom,dig-vtg-min = <1800000>; + qcom,dig-vtg-max = <1800000>; + qcom,fb-resume-delay-us = <1000>; + qcom,afe-force-power-on; + qcom,afe-power-on-delay-us = <6>; + qcom,afe-power-off-delay-us = <6>; + }; +}; + +&tlmm { + pmx_mdss { + mdss_dsi_active: mdss_dsi_active { + mux { + pins = "gpio60"; + }; + + config { + pins = "gpio60"; + }; + }; + + mdss_dsi_suspend: mdss_dsi_suspend { + mux { + pins = "gpio60"; + }; + + config { + pins = "gpio60"; + }; + }; + }; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "bklight_en"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <10>; + }; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi0 { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + bklight_en-supply = <&pm8953_l5>; + vddio-supply = <&pm8953_l6>; + + qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>; + /delete-property/ qcom,platform-bklight-en-gpio; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-te-gpio = <&tlmm 24 0>; + qcom,platform-reset-gpio = <&tlmm 60 0>; +}; + +&mdss_dsi1 { + status = "disabled"; +}; + +&pm8953_pwm { + status = "ok"; +}; + +&dsi_hx8399c_truly_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + +&dsi_hx8399c_hd_vid { + /delete-property/ qcom,mdss-dsi-panel-timings; + qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08]; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; +}; + +&i2c_2 { +#address-cells = <1>; +#size-cells = <0>; + +#include "smb1355.dtsi" +}; + +&pmi632_vadc { + chan@4a { + qcom,scale-function = <22>; + }; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default + &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + smb1355_charger_0: qcom,smb1355-charger@1000 { + status ="ok"; + /delete-property/ io-channels; + /delete-property/ io-channels-names; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + }; +}; + +&pmi632_charger { + qcom,thermal-mitigation = <4200000 3500000 3000000 2500000 + 2000000 1500000 1000000 500000>; +}; diff --git a/qcom/sdm439-rcm-overlay.dts b/qcom/sdm439-rcm-overlay.dts new file mode 100644 index 00000000..a8a4252c --- /dev/null +++ b/qcom/sdm439-rcm-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "sdm439-rcm.dtsi" + +/ { + model = "RCM"; + qcom,board-id = <21 1>; +}; diff --git a/qcom/sdm439-rcm.dts b/qcom/sdm439-rcm.dts new file mode 100644 index 00000000..a8689972 --- /dev/null +++ b/qcom/sdm439-rcm.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm439.dtsi" +#include "sdm439-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 RCM"; + compatible = "qcom,sdm439-cdp", "qcom,sdm439", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; +}; diff --git a/qcom/sdm439-rcm.dtsi b/qcom/sdm439-rcm.dtsi new file mode 100644 index 00000000..26be67e2 --- /dev/null +++ b/qcom/sdm439-rcm.dtsi @@ -0,0 +1 @@ +#include "sdm439-cdp.dtsi" diff --git a/qcom/sdm439-regulator.dtsi b/qcom/sdm439-regulator.dtsi new file mode 100644 index 00000000..a757744e --- /dev/null +++ b/qcom/sdm439-regulator.dtsi @@ -0,0 +1,498 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&rpm_bus { + /* PM8953 regulators */ + rpm-regulator-smpa1 { + status = "okay"; + pm8953_s1: regulator-s1 { + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + status = "okay"; + }; + }; + + /* PM8953 S2 - VDD_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + pm8953_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8953_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8953_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + }; + + pm8953_cx_cdev: regulator-cx-cdev { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pm8953_s2_floor_level>; + regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_RETENTION>; + #cooling-cells = <2>; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8953_s3: regulator-s3 { + regulator-min-microvolt = <856000>; + regulator-max-microvolt = <1280000>; + qcom,init-voltage = <856000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8953_s4: regulator-s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1900000>; + status = "okay"; + }; + }; + + /* VDD_MX supply */ + rpm-regulator-smpa7 { + status = "okay"; + pm8953_s7_level: regulator-s7-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s7_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,init-voltage-level = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + qcom,use-voltage-level; + qcom,always-send-voltage; + }; + + pm8953_s7_level_ao: regulator-s7-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s7_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,use-voltage-level; + qcom,always-send-voltage; + }; + + pm8953_s7_level_so: regulator-s7-level-so { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_s7_level_so"; + qcom,set = <2>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_BINNING>; + qcom,init-voltage-level = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8953_l1: regulator-l1 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1152000>; + qcom,init-voltage = <968000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8953_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8953_l3: regulator-l3 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1140000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + status = "okay"; + pm8953_l4: regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l4"; + qcom,set = <3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8953_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8953_l6: regulator-l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8953_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8953_l7_ao: regulator-l7-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l7_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8953_l8: regulator-l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8953_l9: regulator-l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8953_l10: regulator-l10 { + regulator-min-microvolt = <2948000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2948000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8953_l11: regulator-l11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8953_l12: regulator-l12 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8953_l13: regulator-l13 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <3050000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "okay"; + pm8953_l14: regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l14"; + qcom,set = <3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3052000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <5000>; + status = "okay"; + pm8953_l15: regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8953_l15"; + qcom,set = <3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3052000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8953_l16: regulator-l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8953_l17: regulator-l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8953_l19: regulator-l19 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1356000>; + qcom,init-voltage = <1224000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8953_l22: regulator-l22 { + regulator-min-microvolt = <2560000>; + regulator-max-microvolt = <2840000>; + qcom,init-voltage = <2560000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8953_l23: regulator-l23 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <800000>; + status = "okay"; + }; + }; +}; + +&spmi_bus { + qcom,pm8953@1 { + /* PM8953 S5 + S6 = VDD_APC_supply */ + pm8953_s5: spm-regulator@2000 { + compatible = "qcom,spm-regulator"; + reg = <0x2000 0x100>; + regulator-name = "pm8953_s5"; + regulator-min-microvolt = <490000>; + regulator-max-microvolt = <980000>; + + pm8953_s5_limit: avs-limit-regulator { + regulator-name = "pm8953_s5_avs_limit"; + regulator-min-microvolt = <490000>; + regulator-max-microvolt = <980000>; + }; + }; + }; +}; + +&soc { + apc_mem_acc_vreg: apc-mem-acc-regulator { + compatible = "qcom,mem-acc-regulator"; + regulator-name = "apc_mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <2>; + qcom,acc-reg-addr-list = <0x01942138 0x01942130 0x01946004>; + qcom,acc-init-reg-config = <1 0xff>; + qcom,num-acc-corners = <2>; + qcom,boot-acc-corner = <1>; + qcom,corner1-reg-config = + /* 1 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, + /* 1 -> 2 */ + < 2 0xffff>, < 3 0xff>; + qcom,corner2-reg-config = + /* 2 -> 1 */ + < 2 0x5555>, < 3 0x55>, + /* 2 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <810000 845000 980000>; + qcom,cpr-voltage-floor = <700000 700000 790000>; + vdd-apc-supply = <&pm8953_s5>; + mem-acc-supply = <&apc_mem_acc_vreg>; + qcom,mem-acc-corner-map = <1 1 1 1 2 2>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <10>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <4>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,cpr-fuse-row = <67 0>; + qcom,cpr-fuse-target-quot = <42 24 6>; + qcom,cpr-fuse-ro-sel = <60 57 54>; + qcom,cpr-init-voltage-ref = <760000 795000 910000>; + qcom,cpr-fuse-init-voltage = + <67 36 6 0>, + <67 18 6 0>, + <67 0 6 0>; + qcom,cpr-fuse-quot-offset = + <71 26 6 0>, + <71 20 6 0>, + <70 54 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-corner-map = <1 2 3 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 1305600000>, + <2 1497600000>, + <3 1708800000>, + <4 1804800000>, + <5 1958400000>, + <6 2016000000>; + qcom,speed-bin-fuse-sel = <37 34 3 0>; + qcom,cpr-speed-bin-max-corners = + <0 (-1) 1 2 5>, + <1 (-1) 1 2 5>, + <4 (-1) 1 2 6>, + <5 (-1) 1 2 6>; + qcom,cpr-fuse-revision = <69 39 3 0>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + + qcom,cpr-fuse-version-map = + /* <Speed-bin pvs-version cpr-rev ... ... ...> */ + <(-1) (-1) ( 0) (-1) (-1) (-1)>, + <(-1) (-1) ( 1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1)>; + + qcom,cpr-quotient-adjustment = + <66 77 66>, /* SVSP/NOM/TUR:30/35/30 mV */ + <(-74) 0 (-30)>, /* SVSP/NOM/TUR:-34/0/-14 mV */ + <0 0 0>; + + qcom,cpr-floor-to-ceiling-max-range = + <50000 50000 65000 65000 65000 65000>, + <50000 50000 65000 65000 65000 65000>, + <50000 50000 65000 65000 65000 65000>; + + qcom,cpr-voltage-ceiling-override = + <(-1) (-1) 810000 845000 885000 980000 980000 980000>; + + qcom,cpr-virtual-corner-quotient-adjustment = + <0 0 0 0 0 0>, + <0 0 (-22) 0 0 0>, /* NOMP: -10 mV */ + <0 0 0 0 0 0>; + + qcom,cpr-enable; + }; + + dbu1: dbu1 { + compatible = "regulator-fixed"; + regulator-name = "dbu1"; + startup-delay-us = <0>; + enable-active-high; + }; +}; diff --git a/qcom/sdm439.dts b/qcom/sdm439.dts new file mode 100644 index 00000000..5ac98a19 --- /dev/null +++ b/qcom/sdm439.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdm439.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439 MTP"; + compatible = "qcom,sdm439"; + qcom,pmic-id = <0x010016 0x25 0x0 0x0>; + qcom.pmic-name = "PMI632"; +}; diff --git a/qcom/sdm439.dtsi b/qcom/sdm439.dtsi new file mode 100644 index 00000000..bc5ac4c2 --- /dev/null +++ b/qcom/sdm439.dtsi @@ -0,0 +1,669 @@ +#include "msm8937.dtsi" +#include "sdm439-pm8953.dtsi" +#include "sdm439-pmi632.dtsi" +#include "sdm439-audio.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM439"; + compatible = "qcom,sdm439"; + qcom,msm-id = <353 0x0>; +}; + +&soc { + qcom,csid@1b30000 { + qcom,csi-vdd-voltage = <800000>; + qcom,mipi-csi-vdd-supply = <&pm8953_l23>; + }; + + qcom,csid@1b30400 { + qcom,csi-vdd-voltage = <800000>; + qcom,mipi-csi-vdd-supply = <&pm8953_l23>; + }; + + qcom,csid@1b30800 { + qcom,csi-vdd-voltage = <800000>; + qcom,mipi-csi-vdd-supply = <&pm8953_l23>; + }; + + qcom,csiphy@1b34000 { + compatible = "qcom,csiphy-v10.00", "qcom,csiphy"; + }; + + qcom,csiphy@1b35000 { + compatible = "qcom,csiphy-v10.00", "qcom,csiphy"; + }; + + /delete-node/ qcom,msm-cpufreq; + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = + "l2_clk", + "cpu0_clk", + "cpu4_clk"; + /* TODO + * clocks = <&clock_cpu clk_cci_clk>, + * <&clock_cpu clk_a53_bc_clk>, + * <&clock_cpu clk_a53_lc_clk>; + */ + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 960000 >, + < 1305600 >, + < 1497600 >, + < 1708800 >, + < 1804800 >, + < 1958400 >, + < 2016000 >; + + qcom,cpufreq-table-4 = + < 768000 >, + < 998400 >, + < 1171200 >, + < 1305600 >, + < 1459200 >; + }; + + /delete-node/ generic-bw-opp-table; + generic_bw_opp_table: generic-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 101, 8); /* 769 MB/s */ + BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ + BW_OPP_ENTRY( 278, 8); /* 2124 MB/s */ + BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */ + BW_OPP_ENTRY( 422, 8); /* 3221 MB/s */ + BW_OPP_ENTRY( 557, 8); /* 4248 MB/s */ + BW_OPP_ENTRY( 662, 8); /* 5053 MB/s */ + BW_OPP_ENTRY( 749, 8); /* 5712 MB/s */ + BW_OPP_ENTRY( 797, 8); /* 6079 MB/s */ + BW_OPP_ENTRY( 845, 8); /* 6445 MB/s */ + BW_OPP_ENTRY( 931, 8); /* 7104 MB/s */ + }; + + /delete-node/ qcom,cpu-cpu-ddr-bw; + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&generic_bw_opp_table>; + }; + + /delete-node/ qcom,cpu0-cpu-ddr-latfloor; + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "cpufreq"; + qcom,src-dst-ports = + <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; + qcom,active-only; + operating-points-v2 = <&generic_bw_opp_table>; + }; + + /delete-node/ qcom,cci; + cci_cache: qcom,cci { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + /* TODO + * clocks = <&clock_cpu clk_cci_clk>; + */ + governor = "cpufreq"; + freq-tbl-khz = + < 400000 >, + < 400000 >, + < 400000 >, + < 533000 >, + < 576000 >; + }; + + /delete-node/ qcom,cpu0-cpugrp; + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1305600 MHZ_TO_MBPS(384, 8) >, + < 1804800 MHZ_TO_MBPS(557, 8) >; + }; + }; + + /delete-node/ qcom,cpu4-cpugrp; + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1171200 MHZ_TO_MBPS(384, 8) >, + < 1459200 MHZ_TO_MBPS(749, 8) >; + }; + }; +}; + + +/ { + /delete-node/ energy-costs; + energy_costs: energy-costs { + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 800000 137 + 1305600 207 + 1497600 256 + 1708800 327 + 1804800 343 + 1958400 445 + 2016000 470 + >; + idle-cost-data = < + 100 80 60 40 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 768000 43 + 998400 56 + 1171200 71 + 1305600 89 + 1459200 120 + >; + }; + }; +}; + +&kgsl_smmu { + qcom,enable-static-cb; +}; + +&reserved_memory { + gpu_mem: gpu_region@0 { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; +}; + +&modem_mem { + reg = <0x0 0x86800000 0x0 0x5500000>; +}; + +&adsp_fw_mem { + reg = <0x0 0x8bd00000 0x0 0x1100000>; +}; + +&wcnss_fw_mem { + reg = <0x0 0x8ce00000 0x0 0x700000>; +}; + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a506_zap"; + memory-region = <&gpu_mem>; + qcom,mas-crypto = <&mas_crypto>; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc CRYPTO_CLK_SRC>; + clock-names = "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk", + "scm_bus_clk", "scm_core_clk_src"; + qcom,scm_core_clk_src-freq = <80000000>; + }; +}; + +&kgsl_msm_iommu { + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + memory-region = <&secure_mem>; + }; +}; + +&clock_cpu { + compatible = "qcom,cpu-clock-sdm439"; + vdd-c0-supply = <&apc_vreg_corner>; + vdd-c1-supply = <&apc_vreg_corner>; + vdd-cci-supply = <&apc_vreg_corner>; + qcom,speed0-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 998400000 1>, + < 1171200000 2>, + < 1305600000 3>, + < 1459200000 5>; + + qcom,speed0-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>; + + qcom,speed0-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed1-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 998400000 1>, + < 1171200000 2>, + < 1305600000 3>, + < 1459200000 5>; + + qcom,speed1-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1804800000 5>; + + qcom,speed1-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed4-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 998400000 1>, + < 1171200000 2>, + < 1305600000 3>, + < 1459200000 5>; + + qcom,speed4-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>, + < 2016000000 6>; + + qcom,speed4-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed5-bin-v0-c0 = + < 0 0>, + < 768000000 1>, + < 998400000 1>, + < 1171200000 2>, + < 1305600000 3>, + < 1459200000 5>; + + qcom,speed5-bin-v0-c1= + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>; + + qcom,speed5-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; +}; + +&gcc { + compatible = "qcom,gcc-sdm439"; + reg = <0x1800000 0x80000>, + <0xb016000 0x00040>, + <0xb116000 0x00040>, + <0x00a6018 0x00004>; + reg-names = "cc_base", "apcs_c1_base", + "apcs_c0_base", "efuse"; + vdd_cx-supply = <&pm8953_s2_level>; + vdd_sr2_dig-supply = <&pm8953_s2_level_ao>; + vdd_sr2_pll-supply = <&pm8953_l7_ao>; + vdd_hf_dig-supply = <&pm8953_s2_level_ao>; + vdd_hf_pll-supply = <&pm8953_l7_ao>; +}; + +&gcc_mdss { + compatible = "qcom,gcc-mdss-sdm439"; + /* TODO + * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; + */ + clock-names = "pclk0_src", "byte0_src", "pclk1_src", + "byte1_src"; + #clock-cells = <1>; +}; + +&mdss_dsi0_pll { + compatible = "qcom,mdss_dsi_pll_12nm"; + reg = <0x001a94400 0x400>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <31500>; + qcom,ssc-ppm = <5000>; +}; + +&mdss_dsi1_pll { + compatible = "qcom,mdss_dsi_pll_12nm"; + reg = <0x001a96400 0x400>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <31500>; + qcom,ssc-ppm = <5000>; +}; + +&mdss_dsi { + ranges = <0x1a94000 0x1a94000 0x300 + 0x1a94400 0x1a94400 0x400 + 0x193e000 0x193e000 0x30 + 0x1a96000 0x1a96000 0x300 + 0x1a96400 0x1a96400 0x400 + 0x193e000 0x193e000 0x30>; +}; + +&mdss_dsi0 { + reg = <0x1a94000 0x300>, + <0x1a94400 0x400>, + <0x193e000 0x30>; + reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; + /delete-property/ qcom,platform-strength-ctrl; + /delete-property/ qcom,platform-bist-ctrl; + /delete-property/ qcom,platform-regulator-settings; + /delete-property/ qcom,platform-lane-config; +}; + +&mdss_dsi1 { + reg = <0x1a96000 0x300>, + <0x1a96400 0x400>, + <0x193e000 0x30>; + reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; + /delete-property/ qcom,platform-strength-ctrl; + /delete-property/ qcom,platform-bist-ctrl; + /delete-property/ qcom,platform-regulator-settings; + /delete-property/ qcom,platform-lane-config; +}; + +/* GPU Overrides*/ +&gpubw { + /delete-property/qcom,bw-tbl; + qcom,bw-tbl = + < 0 >, /* off */ + < 769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */ + < 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */ + < 2273 >, /* 3. DDR:297.60 MHz BIMC: 148.80 MHz */ + < 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */ + < 4248 >, /* 5. DDR:556.80 MHz BIMC: 278.40 MHz */ + < 5346 >, /* 6. DDR:662.40 MHz BIMC: 331.20 MHz */ + < 5712 >, /* 7. DDR:748.80 MHz BIMC: 374.40 MHz */ + < 6150 >, /* 8. DDR:796.80 MHz BIMC: 398.40 MHz */ + < 7105 >; /* 9. DDR:931.20 MHz BIMC: 465.60 MHz */ +}; + +&msm_gpu { + /delete-property/qcom,msm-bus,num-cases; + qcom,msm-bus,num-cases = <10>; + /delete-property/qcom,msm-bus,vectors-KBps; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, /* off */ + <26 512 0 806400>, /* 1. 100.80 MHz */ + <26 512 0 1689600>, /* 2. 211.20 MHz */ + <26 512 0 2380800>, /* 3. 297.60 MHz */ + <26 512 0 3072000>, /* 4. 384.00 MHz */ + <26 512 0 4454400>, /* 5. 556.80 MHz */ + <26 512 0 5299200>, /* 6. 662.40 MHz */ + <26 512 0 5990400>, /* 7. 748.80 MHz */ + <26 512 0 6374400>, /* 8. 796.80 MHz */ + <26 512 0 7449600>; /* 9. 931.20 MHz */ + + qcom,gpu-speed-bin-vectors = + <0x6004 0x00c00000 22>, + <0x6008 0x00000600 7>; + + /delete-node/qcom,gpu-pwrlevels; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <9>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <560000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <510000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <4>; + + qcom,initial-pwrlevel = <2>; + + /* NOM+ */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <560000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <510000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <5>; + + qcom,initial-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <510000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <10>; + + qcom,initial-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; + +&sdhc_1 { + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>; + +}; + +&sdhc_2 { + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>; + +}; + +&mdss_mdp { + qcom,vbif-settings = <0xd0 0x20>; +}; + +&thermal_zones { + hexa-cpu-max-step { + trips { + cpu-trip { + temperature = <95000>; + }; + }; + }; +}; + +&usb_otg { + qcom,hsusb-otg-phy-init-seq = <0x43 0x80 0x06 0x82 0xffffffff>; +}; diff --git a/qcom/sdm660-pinctrl.dtsi b/qcom/sdm660-pinctrl.dtsi index f3b76407..8532a1c2 100644 --- a/qcom/sdm660-pinctrl.dtsi +++ b/qcom/sdm660-pinctrl.dtsi @@ -3,7 +3,7 @@ compatible = "qcom,sdm660-pinctrl"; reg = <0x03000000 0xc00000>; reg-names = "pinctrl", "spi_cfg"; - interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/qcom/vbms-batterydata-mlp356477-2800mah.dtsi b/qcom/vbms-batterydata-mlp356477-2800mah.dtsi new file mode 100644 index 00000000..b8a1124c --- /dev/null +++ b/qcom/vbms-batterydata-mlp356477-2800mah.dtsi @@ -0,0 +1,106 @@ +qcom,mlp356477_2800mah { + qcom,fcc-mah = <4200>; + qcom,batt-id-kohm = <82>; + qcom,rbatt-capacitive-mohm = <50>; + qcom,default-rbatt-mohm = <148>; + qcom,max-voltage-uv = <4400000>; + qcom,v-cutoff-uv = <3400000>; + qcom,chg-term-ua = <100000>; + qcom,battery-type = "mlp356477_2800mah"; + + qcom,fcc-temp-lut { + qcom,lut-col-legend = <(-20) 0 25 40 60>; + qcom,lut-data = <2863 2856 2854 2852 2841>; + }; + + qcom,ibat-acc-lut { + qcom,lut-col-legend = <(-20) 0 25>; + qcom,lut-row-legend = <0 250 500 1000>; + qcom,lut-data = <2792 2798 2797>, + <618 2712 2780>, + <128 2440 2766>, + <14 1806 2724>; + }; + + qcom,pc-temp-ocv-lut { + qcom,lut-col-legend = <(-20) 0 25 40 60>; + qcom,lut-row-legend = <100 95 90 85 80>, + <75 70 65 60 55>, + <50 45 40 35 30>, + <25 20 16 13 11>, + <10 9 8 7 6>, + <5 4 3 2 1>, + <0>; + qcom,lut-data = <4390 4384 4378 4374 4366>, + <4252 4302 4314 4313 4307>, + <4160 4238 4256 4255 4250>, + <4103 4179 4200 4198 4194>, + <4014 4126 4144 4144 4138>, + <3962 4077 4092 4090 4086>, + <3913 4022 4042 4042 4037>, + <3875 3960 3993 3995 3992>, + <3850 3914 3946 3948 3946>, + <3832 3872 3892 3894 3892>, + <3816 3839 3858 3860 3859>, + <3802 3814 3832 3834 3832>, + <3787 3798 3810 3812 3811>, + <3771 3785 3792 3794 3792>, + <3754 3772 3774 3774 3768>, + <3734 3756 3756 3749 3738>, + <3712 3734 3734 3726 3714>, + <3692 3712 3712 3704 3690>, + <3672 3698 3692 3684 3674>, + <3656 3689 3686 3680 3669>, + <3646 3685 3685 3679 3668>, + <3634 3681 3683 3678 3666>, + <3620 3676 3680 3676 3664>, + <3604 3668 3676 3670 3654>, + <3580 3651 3660 3652 3630>, + <3550 3620 3625 3614 3590>, + <3508 3574 3575 3565 3538>, + <3445 3510 3510 3500 3470>, + <3350 3420 3421 3413 3377>, + <3182 3274 3282 3266 3232>, + <3000 3000 3000 3000 3000>; + }; + + qcom,rbatt-sf-lut { + qcom,lut-col-legend = <(-20) 0 25 40 60>; + qcom,lut-row-legend = <100 95 90 85 80>, + <75 70 65 60 55>, + <50 45 40 35 30>, + <25 20 16 13 11>, + <10 9 8 7 6>, + <5 4 3 2 1>; + qcom,lut-data = <1593 376 99 75 68>, + <1591 376 99 75 68>, + <1455 370 99 75 68>, + <1391 362 99 76 67>, + <1280 358 99 76 69>, + <1245 363 102 78 70>, + <1213 358 107 80 72>, + <1200 330 112 84 74>, + <1207 322 116 89 77>, + <1228 311 97 76 68>, + <1261 309 94 74 68>, + <1309 312 94 74 68>, + <1411 320 96 76 70>, + <1588 337 97 78 72>, + <1827 364 99 79 71>, + <2133 397 97 75 69>, + <2536 438 97 74 69>, + <2964 476 100 76 68>, + <3313 509 100 74 68>, + <3539 520 100 76 68>, + <3793 536 101 76 70>, + <4098 558 104 78 72>, + <4461 581 108 82 76>, + <4893 605 112 84 77>, + <5421 626 114 82 72>, + <6107 646 111 79 72>, + <7007 676 114 80 72>, + <8309 727 119 82 76>, + <10285 857 130 89 84>, + <14336 1715 261 178 168>; + }; +}; |