diff options
Diffstat (limited to 'bindings')
43 files changed, 2425 insertions, 25 deletions
diff --git a/bindings/arm/msm/heap-sharing.txt b/bindings/arm/msm/heap-sharing.txt index 03b1efdd..77ca3498 100755 --- a/bindings/arm/msm/heap-sharing.txt +++ b/bindings/arm/msm/heap-sharing.txt @@ -31,6 +31,8 @@ Optional properties for child nodes: - qcom,allocate-on-request: Indicates memory allocation happens only upon client request +- qcom,shared: Indicates memory allocation should be shared by HLOS and peripheral. + Note: qcom,allocate-boot-time and qcom,allocate-on-request are mutually exclusive rite now. - qcom,guard-band: Indicates addition of a guard band memory allocation in addition to the client's memory region. @@ -62,4 +64,4 @@ qcom,memshare { qcom,guard-band; label = "modem"; }; -};
\ No newline at end of file +}; diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index bdf8ed7d..5aa5cebd 100755 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -107,6 +107,9 @@ SoCs: - KAKA compatible = "qcom,kaka" +- CROW + compatible = "qcom,crow" + - CINDER compatible = "qcom,cinder" @@ -128,6 +131,9 @@ SoCs: - SDXBAAGHA compatible = "qcom,sdxbaagha" +- MONACO_AUTO + compatible = "qcom,monaco_auto" + Generic board variants: - CDP device: @@ -252,6 +258,7 @@ compatible = "qcom,kona-cdp" compatible = "qcom,kona-qrd" compatible = "qcom,kona-iot" compatible = "qcom,kona-iot-qrd" +compatible = "qcom,kona-hdk" compatible = "qcom,lahaina-rumi" compatible = "qcom,lahaina-atp" compatible = "qcom,lahaina-mtp" @@ -283,6 +290,7 @@ compatible = "qcom,sm6150-qrd" compatible = "qcom,sm6150-idp" compatible = "qcom,qcs405-rumi" compatible = "qcom,qcs405-iot" +compatible = "qcom,qcs407-iot" compatible = "qcom,qcs403-iot" compatible = "qcom,sa8150-adp-star" compatible = "qcom,adp-star" @@ -322,6 +330,7 @@ compatible = "qcom,kalamap-qrd" compatible = "qcom,kalamap-hdk" compatible = "qcom,kalamap-hhg" compatible = "qcom,kaka-rumi" +compatible = "qcom,crow-rumi" compatible = "qcom,cinder-rumi" compatible = "qcom,cinder-idp" compatible = "qcom,cinder-x100" @@ -366,3 +375,4 @@ compatible = "qcom,lemans-adas-high-adp-star" compatible = "qcom,lemans-adas-high-qam-star" compatible = "qcom,lemans-ivi-adas-adp-star" compatible = "qcom,lemans-ivi-adas-qam-star" +compatible = "qcom,monaco_auto-rumi" diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt index 9cddfbce..889d8737 100755 --- a/bindings/clock/qcom,camcc.txt +++ b/bindings/clock/qcom,camcc.txt @@ -19,6 +19,7 @@ Required properties : "qcom,sc8180x-camcc" "qcom,sm8250-camcc" "qcom,lemans-camcc" + "qcom,crow-camcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index cced5fab..61e8d7e3 100755 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -13,6 +13,7 @@ Required properties : "qcom,kalama-debugcc" "qcom,sm8150-debugcc" "qcom,cinder-debugcc" + "qcom,cinder-debugcc-v2" "qcom,khaje-debugcc" "qcom,sc8180x-debugcc" "qcom,monaco-debugcc" diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index 71a6cc58..70deebda 100755 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -29,6 +29,7 @@ Required properties : "qcom,lemans-dispcc0" "qcom,lemans-dispcc1" "qcom,sm8250-dispcc" + "qcom,crow-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,ecpricc.txt b/bindings/clock/qcom,ecpricc.txt index 5dc95e3a..386c7509 100755 --- a/bindings/clock/qcom,ecpricc.txt +++ b/bindings/clock/qcom,ecpricc.txt @@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. ECPRI Clock Controller Binding -------------------------------------------------------------------- Required properties : -- compatible : shall contain "qcom,cinder-ecpricc" +- compatible : shall contain "qcom,cinder-ecpricc" or "qcom,cinder-ecpricc-v2" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt index 1b13ef77..ac97f4b6 100755 --- a/bindings/clock/qcom,gcc.txt +++ b/bindings/clock/qcom,gcc.txt @@ -37,6 +37,7 @@ Required properties : "qcom,kalama-gcc" "qcom,kalama-gcc-v2" "qcom,cinder-gcc" + "qcom,cinder-gcc-v2" "qcom,khaje-gcc" "qcom,gcc-sc8180x" "qcom,monaco-gcc" @@ -46,6 +47,7 @@ Required properties : "qcom,lemans-gcc" "qcom,sa410m-gcc" "qcom,direwolf-gcc" + "qcom,crow-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 57af8042..ec5071ee 100755 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -18,6 +18,7 @@ Required properties : "qcom,monaco-gpucc", "qcom,scuba-gpucc" "qcom,lemans-gpucc" + "qcom,crow-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,tcsrcc.txt b/bindings/clock/qcom,tcsrcc.txt index 72b63cd9..2f84d0a7 100755 --- a/bindings/clock/qcom,tcsrcc.txt +++ b/bindings/clock/qcom,tcsrcc.txt @@ -4,7 +4,8 @@ Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding Required properties : - compatible : shall contain only one of the following: - "qcom,tcsrcc-kalama" + "qcom,kalama-tcsrcc" + "qcom,crow-tcsrcc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index 74772ab8..9a6c93a8 100755 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -17,6 +17,7 @@ Required properties : "qcom,sa8155-videocc" "qcom,sa8155-videocc-v2" "qcom,lemans-videocc" + "qcom,crow-videocc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/crypto/msm/ice.txt b/bindings/crypto/msm/ice.txt new file mode 100755 index 00000000..acafaebd --- /dev/null +++ b/bindings/crypto/msm/ice.txt @@ -0,0 +1,51 @@ +* Inline Crypto Engine (ICE) + +Required properties: + - compatible : should be "qcom,ice" + - reg : <register mapping> + +Optional properties: + - interrupt-names : name describing the interrupts for ICE IRQ + - interrupts : <interrupt mapping for ICE IRQ> + - qcom,enable-ice-clk : should enable clocks for ICE HW + - clocks : List of phandle and clock specifier pairs + - clock-names : List of clock input name strings sorted in the same + order as the clocks property. + - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks + property. + - qcom,instance-type : describe the storage type for which ICE node is defined + currently, only "ufs" and "sdcc" are supported storage type + - vdd-hba-supply : regulated supply to be used by ICE HW + - qcom,bus-vector-names : bus vectors mapping + +Example: + ufs_ice: ufsice@630000 { + compatible = "qcom,ice"; + reg = <0x630000 0x8000>; + interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; + interrupts = <0 258 0>, <0 257 0>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk"; + clocks = <&clock_gcc clk_ufs_ice_core_clk_src>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <300000000>, <0>; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs_card_ice: ufscardice@1db0000 { + compatible = "qcom,ice_card"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>, + <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>, + <&clock_gcc GCC_UFS_CARD_AHB_CLK>, + <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_card_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs_card"; + }; diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index f4196db8..71a20d87 100755 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -28,6 +28,7 @@ Properties: "qcom,mpm-monaco" "qcom,mpm-scuba" "qcom,mpm-sa410m" + "qcom,mpm-qcs405" - interrupts: Usage: required diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt index a2030839..a38dd5d8 100755 --- a/bindings/interrupt-controller/qcom,pdc.txt +++ b/bindings/interrupt-controller/qcom,pdc.txt @@ -28,6 +28,7 @@ Properties: - "qcom,lemans-pdc": For lemans - "qcom,sdxbaagha-pdc": For SDXBAAGHA - "qcom,kona-pdc": For Kona + - "qcom,crow-pdc": For Crow - reg: Usage: required diff --git a/bindings/iommu/virt,smmu-v3.txt b/bindings/iommu/virt,smmu-v3.txt new file mode 100755 index 00000000..3bb431a4 --- /dev/null +++ b/bindings/iommu/virt,smmu-v3.txt @@ -0,0 +1,28 @@ +* Paravirtualized ARM SMMUv3 + +The Parvirt smmu-v3 driver communicates with the underlying +hypervisor to provide S1 translation context descriptor and +other properties which is set by the client. The backend SMMUv3 +driver in hypervisor is supposed to program the SMMUv3 hardware +with the information from the paravirt SMMUv3 driver. + +** Paravirt SMMUv3 required properties: + +- compatible : Should include: + + "arm,virt-smmu-v3" + + +- #iommu-cells : See the generic IOMMU binding described in + devicetree/bindings/pci/pci-iommu.txt + for details. For Paravirt SMMUv3, must be 1, + with each cell describing a single stream ID. + All possible stream IDs which a device may + emit must be described. + +** Example + + virt_smmuv3: qcom,virt-smmuv3 { + #iommu-cells = <1>; + compatible = "arm,virt-smmu-v3"; + }; diff --git a/bindings/media/msm-npu-pwrlevels.txt b/bindings/media/msm-npu-pwrlevels.txt new file mode 100755 index 00000000..9a8a014c --- /dev/null +++ b/bindings/media/msm-npu-pwrlevels.txt @@ -0,0 +1,164 @@ +Qualcomm Technologies, Inc. NPU powerlevels + +Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines +a series of clock frequencies. These frequencies are for the corresponding +clocks in the clocks property of the msm_npu device. + +qcom,npu-pwrlevels bindings: + +Required Properties: +- #address-cells: Should be set to 1 +- #size-cells: Should be set to 0 +- compatible: Must be qcom,npu-pwrlevels +- initial-pwrlevel: NPU initial wakeup power level, this is the index of the + child node. + +qcom,npu-pwrlevel: This is a child node defining power levels. +qcom,npu-pwrlevels must contain at least one power level node. Each child node +has the following properties: + +Required Properties: +- reg: Index of the powerlevel (0 = lowest performance) +- clk-freq: List of clock frequencies (in Hz) of each clock for the current + powerlevel. List of clocks and order described in: + Documentation/devicetree/bindings/media/msm-npu.txt + +Example: + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; diff --git a/bindings/media/msm-npu.txt b/bindings/media/msm-npu.txt new file mode 100755 index 00000000..f009650f --- /dev/null +++ b/bindings/media/msm-npu.txt @@ -0,0 +1,228 @@ +* Qualcomm Technologies, Inc. MSM NPU + +NPU (Neural Network Processing Unit) applies neural network processing + +Required properties: +- compatible: Must be "qcom,msm-npu" +- reg: Specify offset and length of the device register sets. +- reg-names: Names corresponding to the defined register sets. + - "npu_base": npu base registers +- interrupts: Specify the npu interrupts. +- interrupt-names: should specify relevant names to each interrupts + property defined. +- cache-slice-names: A set of names that identify the usecase names of a + client that uses cache slice. These strings are used to look up the + cache slice entries by name +- cache-slices: The tuple has phandle to llcc device as the first argument + and the second argument is the usecase id of the client +- clocks: clocks required for the device. +- clock-names: names of clocks required for the device. +- vdd-supply: Phandle for vdd regulator device node +- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding + 'reg' domain, e.g. vdd_cx-supply. +- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off + during proxy voting/unvoting. +- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator, + e.g. qcom,vdd_cx-uV-uA. +- mboxes: Phandle array for mailbox controllers to be used for IPC +- mbox-names: names of each mailboxes +- #cooling-cells: Should be set to 2 +- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements + (see devbw.txt) +- qcom,npu-pwrlevels: Container for NPU power levels + (see msm-npu-pwrlevels.txt) +Example: + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x800000>; + reg-names = "npu_base"; + interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + cache-slice-names = "npu"; + cache-slices = <&llcc 23>; + clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CLK_SRC>, + <&clock_npucc NPU_CC_XO_CLK>, + <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, + <&clock_npucc NPU_CC_BTO_CORE_CLK>, + <&clock_npucc NPU_CC_BWMON_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, + <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&clock_npucc NPU_CC_PERF_CNT_CLK>, + <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, + <&clock_npucc NPU_CC_SLEEP_CLK>; + clock-names = "cal_dp_clk", + "cal_dp_clk_src", + "xo_clk", + "armwic_core_clk", + "bto_core_clk", + "bwmon_clk", + "cal_dp_cdc_clk", + "comp_noc_axi_clk", + "conf_noc_ahb_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "perf_cnt_clk", + "qtimer_core_clk", + "sleep_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&pm8150l_s6_level>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>; + mbox-names = "npu_low", "npu_high"; + #cooling-cells = <2>; + qcom,npubw-dev = <&npu_npu_ddr_bw>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + clk-freq = <9600000 + 9600000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 60000000 + 19200000 + 19200000 + 30000000 + 19200000 + 19200000 + 19200000 + 19200000 + 19200000 + 9600000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + clk-freq = <300000000 + 300000000 + 19200000 + 100000000 + 19200000 + 19200000 + 300000000 + 150000000 + 19200000 + 19200000 + 60000000 + 100000000 + 100000000 + 37500000 + 100000000 + 19200000 + 300000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + clk-freq = <350000000 + 350000000 + 19200000 + 150000000 + 19200000 + 19200000 + 350000000 + 200000000 + 37500000 + 19200000 + 120000000 + 150000000 + 150000000 + 75000000 + 150000000 + 19200000 + 350000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + clk-freq = <400000000 + 400000000 + 19200000 + 200000000 + 19200000 + 19200000 + 400000000 + 300000000 + 37500000 + 19200000 + 120000000 + 200000000 + 200000000 + 75000000 + 200000000 + 19200000 + 400000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + clk-freq = <600000000 + 600000000 + 19200000 + 300000000 + 19200000 + 19200000 + 600000000 + 403000000 + 75000000 + 19200000 + 240000000 + 300000000 + 300000000 + 150000000 + 300000000 + 19200000 + 600000000 + 19200000 + 0>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + clk-freq = <715000000 + 715000000 + 19200000 + 350000000 + 19200000 + 19200000 + 715000000 + 533000000 + 75000000 + 19200000 + 240000000 + 350000000 + 350000000 + 150000000 + 350000000 + 19200000 + 715000000 + 19200000 + 0>; + }; + }; + }; diff --git a/bindings/msm_mhi_dev.txt b/bindings/msm_mhi_dev.txt index 52d20dde..18e6f9bb 100755 --- a/bindings/msm_mhi_dev.txt +++ b/bindings/msm_mhi_dev.txt @@ -43,6 +43,8 @@ Required properties: Optional property: - qcom,mhi-ethernet-interface;: If property is present use ethernet packet parsing support. + - qcom,tx_rx_reqs: If property present it will override the number of elements + in rx and tx queues for mhi_dev_net device.(Default:128) Example: mhi: qcom,msm-mhi-dev { diff --git a/bindings/net/qcom-qrtr-genpool.yaml b/bindings/net/qcom-qrtr-genpool.yaml index 9d25994d..37f11f82 100755 --- a/bindings/net/qcom-qrtr-genpool.yaml +++ b/bindings/net/qcom-qrtr-genpool.yaml @@ -24,26 +24,36 @@ properties: Phandle reference to a client which has a dedicated memory region for sharing between Virtual Machine and Digital Signal Processor subsystem. - genpool-poll: - $ref: /schemas/types.yaml#/definitions/flag - description: - If set, enables polling mode for RX. - - genpool-poll-sleep: - $ref: /schemas/types.yaml#/definitions/uint32 - maxItems: 1 - description: - Sleep (ms) between each poll. If not set, the default interval is 100ms. + interrupts: + description: | + IRQs for setting up and transferring data from and to an edge. + items: + - description: IRQ from an edge to check if FIFO and memory is setup + - description: IRQ from an edge informing there is data to consume + + mboxes: + description: | + List of phandles to mailbox channels used for setting up and transferring + data from and to an edge. + items: + - description: mailbox for signaling an edge that FIFO and memory is setup + - description: mailbox for signaling an edge there is data to consume required: -compatible -gen-pool + -interrupt-parent + -interrupts + -mboxes examples: - | qrtr-genpool { compatible = "qcom,qrtr-genpool"; gen-pool = <&fastrpc_compute_cb1>; - genpool-poll; - genpool-poll-sleep = <1000>; + interrupt-parent = <&ipcc_mproc_ns1>; + interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>, + <IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>, + <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>; }; diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt index 425bddc9..351eb34c 100755 --- a/bindings/pci/msm_ep_pcie.txt +++ b/bindings/pci/msm_ep_pcie.txt @@ -75,6 +75,7 @@ Optional Properties: - qcom,msm-bus,vectors-KBps - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode. - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset. + - qcom,override-disable-sriov: Set to report as SRIOV capability disable with client (MHI) driver. Example: diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index cdf1976c..4879cc92 100755 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -244,6 +244,11 @@ interconnects: Value type: <bool> Definition: Support clock power management +- qcom,gdsc-clk-drv-ss-nonvotable: + Usage: optional + Value type: <bool> + Definition: gdsc clock can't be turned off during DRV process. + - qcom,n-fts: Usage: optional Value type: <u32> @@ -510,6 +515,7 @@ Example qcom,boot-option = <0x1>; qcom,drv-name = "lpass"; qcom,use-19p2mhz-aux-clk; + qcom,gdsc-clk-drv-ss-nonvotable; qcom,common-clk-en; qcom,clk-power-manage-en; qcom,n-fts = <0x50>; diff --git a/bindings/pinctrl/qcom,crow-pinctrl.yaml b/bindings/pinctrl/qcom,crow-pinctrl.yaml new file mode 100755 index 00000000..4a27f5b4 --- /dev/null +++ b/bindings/pinctrl/qcom,crow-pinctrl.yaml @@ -0,0 +1,135 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,crow-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CROW TLMM block + +maintainers: + - Naini Singh <nainsing@qti.qualcomm.com> + +description: | + This binding describes the Top Level Mode Multiplexer block. + +properties: + compatible: + oneOf: + const: qcom,crow-pinctrl + + reg: + items: + - description: Base address of TLMM register space + - description: Size of TLMM register space + + interrupts: + minItems: 0 + maxItems: 1 + items: + - const: TLMM summary IRQ + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + wakeup-parent: + maxItems: 1 + description: + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + +# PIN CONFIGURATION NODES +patternPropetries: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + function: + description: + Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0, + cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, + gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1, + mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9, + nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, + phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, + phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist, + pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, + qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, + qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable, + qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, + qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, + qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, + sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0, + vfr_1, vsense_trigger] + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + qcom,i2c_pull: true + description: + Configures additions 2.2k drive strength for the specified pin. + bias-pull-down: true + bias-pull-up: true + bias-disable: true + output-high: true + output-low: true + required: + - pins + - function + additionalProperties: false + +examples: + - | + tlmm: pinctrl@03000000 { + compatible = "qcom,crow-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; + diff --git a/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml b/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml new file mode 100755 index 00000000..19921572 --- /dev/null +++ b/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml @@ -0,0 +1,148 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MONACO_AUTO TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + Monaco Auto platform. + +properties: + compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,monaco_auto-pinctrl" + + reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + + gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + + wakeup-parent: + Usage: optional + Value type: <phandle> + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio148 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + + bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@03000000 { + compatible = "qcom,monaco_auto-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index 1c6a7002..fa125bf1 100755 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -56,6 +56,7 @@ PMIC's from Qualcomm. "qcom,pm5100-gpio" "qcom,pm8775-gpio" "qcom,pm2250-gpio" + "qcom,pm8009-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively diff --git a/bindings/power/supply/qcom/qcom,qbg.yaml b/bindings/power/supply/qcom/qcom,qbg.yaml index d5543d89..cfa61c5e 100755 --- a/bindings/power/supply/qcom/qcom,qbg.yaml +++ b/bindings/power/supply/qcom/qcom,qbg.yaml @@ -66,6 +66,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Resistance of the battery connector in mOhms. + qcom,qbg-vbatt-empty-threshold-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Vbatt empty threshold in mv at which QBG generates low Vbatt + interrupt. + nvmem-cell-names: minItems: 2 maxItems: 3 diff --git a/bindings/power/supply/qcom/smb1390-charger-psy.txt b/bindings/power/supply/qcom/smb1390-charger-psy.txt new file mode 100755 index 00000000..b5bcb13f --- /dev/null +++ b/bindings/power/supply/qcom/smb1390-charger-psy.txt @@ -0,0 +1,119 @@ +Qualcomm Technologies, Inc. SMB1390 Charger Specific Bindings + +SMB1390 charge pump is paired with QTI family of standalone chargers to +enable a high current, high efficiency Li+ battery charging system. + +======================= +Required Node Structure +======================= + +SMB1390 Charger must be described in two levels of device nodes. + +================================== +First Level Node - SMB1390 Charger +================================== + +Charger specific properties: +- compatible + Usage: required + Value type: <string> + Definition: "qcom,smb1390-charger-psy" for master SMB1390 and + "qcom,smb1390-slave" for slave SMB1390. + +- qcom,pmic-revid + Usage: required + Value type: phandle + Definition: Should specify the phandle of SMB's revid module. This is used + to identify the SMB subtype. + +- io-channels +- io-channel-names + Usage: required + Value type: <phandle> + Definition: For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt + +- qcom,min-ilim-ua + Usage: optional + Value type: <u32> + Definition: Minimum ILIM supported, if requested ILIM goes below this value + disable SMB1390. If this values is not specified default minimum + ILIM is 1A. + +- qcom,max-temp-alarm-degc + Usage: optional + Value type: <u32> + Definition: Maximum die temperature to trigger temp alarm. The value + must be one of the following: + 80, 90, 105, 115. + If this value is not specified or is not one of the above + then default value is 105. + +- qcom,max-cutoff-soc + Usage: optional + Value type: <u32> + Definition: SOC beyond which SMB1390 is kept disabled. + If this value is not specified then default value is 85%. + +- qcom,parallel-output-mode + Usage: optional + Value type: <u32> + Definition: Defines the SMB1390 output connection topology. + This should be one of the following: + 0 - If SMB1390 output is not connected to anything; + 1 - If SMB1390 output is connected to VPH_PWR; + 2 - If SMB1390 output is connected to VBATT. + If this value is not specified then default value is 1. + +- qcom,parallel-input-mode + Usage: optional + Value type: <u32> + Definition: Defines the SMB1390 input connection topology. + This should be one of the following: + 0 - If SMB1390 input is not connected to anything; + 1 - If SMB1390 input is connected to USBIN; + 3 - If SMB1390 input is connected to USBMID. + If this value is not specified then default value is 3. + +================================================ +Second Level Nodes - SMB1390 Charger Peripherals +================================================ + +Peripheral specific properties: +- interrupts + Usage: required + Value type: <prop-encoded-array> + Definition: Peripheral interrupt specifier. + +- interrupt-names + Usage: required + Value type: <stringlist> + Definition: Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + +======= +Example +======= + +smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + qcom,pmic-revid = <&smb1390_revid>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x10 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; +}; diff --git a/bindings/qdsp/msm-fastrpc.txt b/bindings/qdsp/msm-fastrpc.txt index d839212b..6ce414b3 100755 --- a/bindings/qdsp/msm-fastrpc.txt +++ b/bindings/qdsp/msm-fastrpc.txt @@ -98,3 +98,9 @@ Example: memory-region = <&adsp_mem>; restrict-access; }; + + qcom,mdsprpc-mem { + compatible = "qcom,msm-mdsprpc-mem-region"; + memory-region = <&mdsp_mem>; + restrict-access; + }; diff --git a/bindings/regulator/cpr-regulator.txt b/bindings/regulator/cpr-regulator.txt new file mode 100755 index 00000000..0f5e27a2 --- /dev/null +++ b/bindings/regulator/cpr-regulator.txt @@ -0,0 +1,961 @@ +QTI CPR (Core Power Reduction) Regulator + +CPR regulator device is for QTI RBCPR (RapidBridge CPR) on + application processor core. It takes voltage corner level + as input and converts it to actual voltage based on the + suggestions from factory production process. When CPR is + enabled for application processer core, it will suggest + scaling the voltage up or down for best performance and + power of the core. The scaling based on factory production + process is called PVS (Process Voltage Scaling) with efuse + bits to indicate what bin (and voltage range) a chip is in. + +Required properties: +- compatible: Must be "qcom,cpr-regulator" +- reg: Register addresses for RBCPR, RBCPR clock + select, PVS and CPR eFuse address +- reg-names: Register names. Must be "rbcpr" and "efuse_addr". + "rbcpr_clk" is optional. +- regulator-name: A string used to describe the regulator +- interrupts: Interrupt line from RBCPR to interrupt controller. +- qcom,cpr-fuse-corners: Number of fuse corners present. Many other properties + are sized based upon this value. +- regulator-min-microvolt: Minimum corner value which should be 1 to + represent the lowest supported corner. +- regulator-max-microvolt: Maximum corner value which should be equal to + qcom,cpr-fuse-corners if consumers request fuse + corners or the length of qcom,cpr-corner-map if + consumers request virtual corners. +- qcom,cpr-voltage-ceiling: Array of ceiling voltages in microvolts for fuse + corners ordered from lowest voltage corner to highest + voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. +- qcom,cpr-voltage-floor: Array of floor voltages in microvolts for fuse + corners ordered from lowest voltage corner to highest + voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. +- vdd-apc-supply: Regulator to supply VDD APC power +- qcom,vdd-apc-step-up-limit: Limit of vdd-apc-supply steps for scaling up. +- qcom,vdd-apc-step-down-limit: Limit of vdd-apc-supply steps for scaling down. +- qcom,cpr-ref-clk: The reference clock in kHz. +- qcom,cpr-timer-delay: The delay in microseconds for the timer interval. +- qcom,cpr-timer-cons-up: Consecutive number of timer interval (qcom,cpr-timer-delay) + occurred before issuing UP interrupt. +- qcom,cpr-timer-cons-down: Consecutive number of timer interval (qcom,cpr-timer-delay) + occurred before issuing DOWN interrupt. +- qcom,cpr-irq-line: Internal interrupt route signal of RBCPR, one of 0, 1 or 2. +- qcom,cpr-step-quotient: Defines the number of CPR quotient (i.e. Ring Oscillator(RO) + count) per vdd-apc-supply output voltage step. A single + integer value may be specified which is to be used for all + RO's. Alternatively, 8 integer values may be specified which + define the step quotients for RO0 to RO7 in order. +- qcom,cpr-up-threshold: The threshold for CPR to issue interrupt when + error_steps is greater than it when stepping up. +- qcom,cpr-down-threshold: The threshold for CPR to issue interrupt when + error_steps is greater than it when stepping down. +- qcom,cpr-idle-clocks: Idle clock cycles RO can be in. +- qcom,cpr-gcnt-time: The time for gate count in microseconds. +- qcom,cpr-apc-volt-step: The voltage in microvolt per CPR step, such as 5000uV. +- qcom,cpr-fuse-row: Array of row number of CPR fuse and method to read that row. It should have + index and value like this: + [0] => the fuse row number + [1] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,cpr-fuse-target-quot: Array of bit positions in the primary CPR fuse row defined + by qcom,cpr-fuse-row for the target quotients of each + fuse corner. Each bit position corresponds to the LSB + of the quotient parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage + corner. This property must be of length defined by + qcom,cpr-fuse-corners. +- qcom,cpr-fuse-ro-sel: Array of bit positions in the primary CPR fuse row defined + by qcom,cpr-fuse-row for the ring oscillator selection for each + fuse corner. Each bit position corresponds to the LSB + of the RO select parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage + corner. This property must be of length defined by + qcom,cpr-fuse-corners. + +Optional properties: +- vdd-mx-supply: Regulator to supply memory power as dependency + of VDD APC. +- qcom,vdd-mx-vmax: The maximum voltage in uV for vdd-mx-supply. This + is required when vdd-mx-supply is present. +- qcom,vdd-mx-vmin-method: The method to determine the minimum voltage for + vdd-mx-supply, which can be one of following + choices compared with VDD APC: + 0 => equal to the voltage(vmin) of VDD APC + 1 => equal to PVS corner ceiling voltage + 2 => equal to slow speed corner ceiling + 3 => equal to qcom,vdd-mx-vmax + 4 => equal to VDD_APC fuse corner mapped vdd-mx voltage + 5 => equal to VDD_APC virtual corner mapped vdd-mx voltage + This is required when vdd-mx-supply is present. +- qcom,vdd-mx-corner-map: Array of integers which defines the mapping from VDD_APC + voltage corners to vdd-mx-supply voltages. + Each element is a voltage to request from vdd-mx for the + corresponding fuse corner or virtual corner. The elements + in the array are ordered from lowest voltage corner + to highest voltage corner. The length of this property + depends on the value of qcom,vdd-mx-vmin-method property. + When qcom,vdd-mx-vmin-method property has a value of 4, the length + of this property must be equal to the value defined by qcom,cpr-fuse-corners. + When qcom,vdd-mx-vmin-method property has a value of 5, the length of + this property must be equal to the number of elements in the qcom,cpr-corner-map + property. +- qcom,pvs-voltage-table: Array of N-tuples in which each tuple specifies the + initial voltage in microvolts of the PVS bin for each + fuse voltage corner. The location or 0-based index + of a tuple in the list corresponds to the PVS bin number. + Each tuple must be of length defined by qcom,cpr-fuse-corners. + A given cpr-regulator device must have either + qcom,pvs-voltage-table specified or + qcom,cpr-fuse-init-voltage (and its associated properties). +- qcom,pvs-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the redundant PVS fuse bits would be + used instead of the original bits and method to read fuse row, reading + register through SCM or directly. The 5 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => the value to indicate redundant selection + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading + When the value of the fuse bits specified by first 3 elements equals to + the value in 4th element, redundant PVS fuse bits should be selected. + Otherwise, the original PVS bits should be selected. If the 5th + element is 0, read the fuse row from register directly. Otherwise, + read it through SCM. + This property is required if qcom,pvs-voltage-table is present. +- qcom,pvs-fuse: Array of 4 elements to indicate the bits for PVS fuse and read method. + The array should have index and value like this: + [0] => the PVS fuse row number + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading + This property is required if qcom,pvs-voltage-table is present. +- qcom,pvs-fuse-redun: Array of 4 elements to indicate the bits for redundant PVS fuse. + The array should have index and value like this: + [0] => the redundant PVS fuse row number + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading + This property is required if qcom,pvs-voltage-table is present. +- qcom,cpr-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the redundant CPR fuse bits would be + used instead of the original bits and method to read fuse row, using SCM + to read or read register directly. The 5 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => the value to indicate redundant selection + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading + When the value of the fuse bits specified by first 3 elements equals to + the value in 4th element, redundant CPR fuse bits should be selected. + Otherwise, the original CPR bits should be selected. If the 5th element + is 0, read the fuse row from register directly. Otherwise, read it through + SCM. +- qcom,cpr-fuse-redun-row: Array of row number of redundant CPR fuse and method to read that + row. It should have index and value like this: + [0] => the redundant fuse row number + [1] => the value to indicate reading the fuse row directly or using SCM + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-target-quot: Array of bit positions in the redundant CPR fuse row defined + by qcom,cpr-fuse-redun-row for the target quotients of each + fuse corner. Each bit position corresponds to the LSB + of the quotient parameter. The elements in the array + are ordered from lowest voltage corner to highest voltage corner. + This property must be of length defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-ro-sel: Array of bit positions in the redundant CPR fuse row defined + by qcom,cpr-fuse-redun-row for the ring oscillator select of each + fuse corner. Each bit position corresponds to the LSB of the RO + select parameter. The elements in the array are ordered from + lowest voltage corner to highest voltage corner. + This property must be of length defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-redun-sel is present. +- qcom,cpr-fuse-redun-bp-cpr-disable: Redundant bit position of the bit to indicate if CPR should be disable +- qcom,cpr-fuse-redun-bp-scheme: Redundant bit position of the bit to indicate if it's a global/local scheme + This property is required if cpr-fuse-redun-bp-cpr-disable + is present, and vise versa. +- qcom,cpr-fuse-bp-cpr-disable: Bit position of the bit to indicate if CPR should be disabled +- qcom,cpr-fuse-bp-scheme: Bit position of the bit to indicate if it's a global/local scheme +- qcom,cpr-fuse-revision: Array of 4 integer elements which define the location of the bits for + the CPR fusing revision fuse parameter. The 4 elements are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => the number of bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The fusing revision value is used to determine which specific adjustments + are required on some chips. +- qcom,cpr-fuse-target-quot-size: Array of target quotient parameter bit sizes in the primary + or redundant CPR fuse row for each fuse corner. The elements in the + array are ordered from lowest voltage corner to highest voltage corner. + If this property is not present, then all target quotient fuse values + are assumed to be the default length of 12 bits. +- qcom,cpr-fuse-target-quot-scale: Array of doubles which defines the scaling coefficients to decode + the target quotients of each fuse corner. The first element in each + double represents the offset to add to the scaled quotient. The second + element represents the multiplier to scale the quotient by. For example, + given a tuple <A B>, quot_decoded = A + (B * quot_raw). + The doubles in the array are ordered from lowest voltage corner to highest + voltage corner. This property must contain a number of doubles equal to + the value of qcom,cpr-fuse-corners. If this property is not present, + then all target quotient parameters are assumed to have an offset of 0 + and a multiplier of 1 (i.e. no decoding needed). +- qcom,cpr-enable: Present: CPR enabled by default. + Not Present: CPR disable by default. +- qcom,cpr-fuse-cond-min-volt-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to decide if the conditional minimum apc voltage needs + to be applied and the fuse reading method. + The 5 elements with index[0..4] are: + [0] => the fuse row number; + [1] => LSB bit position of the bits; + [2] => number of the bits; + [3] => the expected data to read; + [4] => fuse reading method, 0 for direct reading or 1 for SCM reading; + When the value of the fuse bits specified by first 3 elements is not equal to + the value in 4th element, then set the apc voltage for all parts running + at each voltage corner to be not lower than the voltage defined + using "qcom,cpr-cond-min-voltage". +- qcom,cpr-cond-min-voltage: Minimum voltage in microvolts allowed for cpr-regulator output if the fuse bits + defined in qcom,cpr-fuse-cond-min-volt-sel have not been programmed with the + expected data. This is required if cpr-fuse-cond-min-volt-sel is present. +- qcom,cpr-fuse-uplift-sel: Array of 5 elements to indicate where to read the bits, what value to + compare with in order to enable or disable the pvs voltage uplift workaround, + and the fuse reading method. + The 5 elements with index[0..4] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => number of the bits; + [3]: => the value to indicate if the apc pvs voltage uplift workaround will + be enabled; + [4]: => fuse reading method, 0 for direct reading or 1 for SCM reading. + When the value of the fuse bits specified by first 3 elements equals to the + value in 4th element, the pvs voltage uplift workaround will be enabled. +- qcom,speed-bin-fuse-sel: Array of 4 elements to indicate where to read the speed bin of the processor, + and the fuse reading method. + The 4 elements with index[0..3] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => number of the bits; + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-voltage: Uplift in microvolts used for increasing pvs init voltage. If this property is present, + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-max-volt: Maximum voltage in microvolts used for pvs voltage uplift workaround to limit + the maximum pvs voltage. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-quotient: Array of target quotient increments to add to the fused quotients of each + fuse corner as part of the PVS voltage uplift workaround. + The elements in the array are ordered from lowest voltage + corner to highest voltage corner. This property must be of + length defined by qcom,cpr-fuse-corners. This is required + if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-uplift-speed-bin: The speed bin value corresponding to one type of processor which needs to apply the + pvs voltage uplift workaround. + This is required if cpr-fuse-uplift-disable-sel is present. +- qcom,cpr-fuse-version-map: Array of integer tuples which each match to a given combination of CPR + fuse parameter values. Each tuple consists of N + 3 elements. Where + N is the number of fuse corners defined by the qcom,cpr-fuse-corners + property. The elements in one tuple are: + [0]: => the speed bin of the CPU + [1]: => the PVS version of the CPU + [2]: => the CPR fuse revision + [3 - N+2]: => the ring oscillator select value of each fuse corner + ordered from lowest to highest + Any element in a tuple may use the value 0xffffffff as a wildcard + which will match against any fuse parameter value. The first tuple + that matches against the fuse values read from hardware will be used. + This property is used by several properties to provide an index into + their lists. +- qcom,cpr-allowed: Integer values that specifies whether the closed loop CPR is allowed or + not for a particular fuse revision. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-allowed must contain the same number + of integers as that of the number of tuples in qcom,cpr-fuse-version-map. + If the integer value has a value 0 for a particular fuse revision, then it + is treated as if the closed loop operation is disabled in the fuse. If the + integer value has a value 1 for a particular fuse revision, then the closed + loop operation is enabled for that fuse revision. If nothing is specified + for a particular fuse revision, then the closed loop operation is enabled + for that fuse revision by default. +- qcom,cpr-quotient-adjustment: Array of integer tuples of target quotient adjustments to add to the fused + quotients of each fuse corner. The elements in a tuple are ordered from + lowest voltage corner to highest voltage corner. Each tuple must be of + length defined by qcom,cpr-fuse-corners. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-quotient-adjustment must contain the + same number of tuples as qcom,cpr-fuse-version-map. These tuples are then + mapped one-to-one in the order specified. E.g. if the second + qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient + adjustments defined in the second qcom,cpr-quotient-adjustment tuple will + be applied. If the qcom,cpr-fuse-version-map property is not specified, + then qcom,cpr-quotient-adjustment must contain a single tuple which is then + applied unconditionally. If this property is specified, then the quotient + adjustment values are added to the target quotient values read from fuses + before writing them into the CPR GCNT target control registers. + This property can be used to add or subtract static voltage margin from the + regulator managed by the CPR controller. +- qcom,cpr-init-voltage-adjustment: Array of integer tuples of initial voltage adjustments in microvolts to + add to the fused initial voltage values of each fuse corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length defined by qcom,cpr-fuse-corners. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-init-voltage-adjustment must contain the same number of tuples as + qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then the initial voltage adjustments defined in the + second qcom,cpr-init-voltage-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-init-voltage-adjustment must contain a single tuple which is then + applied unconditionally. This property can be used to add or subtract + static initial voltage margin from the regulator managed by the CPR + controller. +- qcom,cpr-quot-offset-adjustment: Array of integer tuples of target quotient offset adjustments to add + to the fused quotient offsets of each fuse corner. The elements in a tuple + are ordered from lowest voltage corner to highest voltage corner. Each tuple + must be of length defined by qcom,cpr-fuse-corners. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-quot-offset-adjustment must contain the + same number of tuples as qcom,cpr-fuse-version-map. These tuples are then + mapped one-to-one in the order specified. E.g. if the second + qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient + offset adjustments defined in the second qcom,cpr-quot-offset-adjustment tuple + will be applied. If the qcom,cpr-fuse-version-map property is not specified, + then qcom,cpr-quot-offset-adjustment must contain a single tuple which is then + applied unconditionally. If this property is specified, then the quotient + offset adjustment values are added to the target quotient offset values read + from fuses. + This property can be used to add or subtract static quotient offset margin from + the regulator managed by the CPR controller. +- qcom,cpr-clamp-timer-interval: The number of 64 reference clock cycle blocks to delay for whenever + the clamp signal, sensor mask registers or sensor bypass registers + change. The CPR controller loop is disabled during this delay. + Supported values are 0 to 255. If this property is not specified, + then a value of 0 is assumed. Note that if this property has a + value greater than 0, then software cannot accurately determine the + error_steps value that corresponds to a given CPR measurement + unless processor power collapsing is disabled. If this property + has a value of 0, then the CPR controller loop is not disabled and + re-enabled while idle if the clamp signal changes. Instead, it + will remain idle until software issues an ACK or NACK command. + This ensures that software can read the error_steps value which + resulted in the CPR up or down interrupt. Setting this property to + a value greater than 0 is useful for resetting the CPR sensors of a + processor that uses BHS type voltage switches in order to avoid + anomalous CPR up interrupts when exiting from power collapse. +- vdd-apc-optional-prim-supply: Present: Regulator of highest priority to supply VDD APC power + Not Present: No such regulator. +- vdd-apc-optional-sec-supply: Present: Regulator of second highest priority to supply VDD APC power. + Not Present: No such regulator. +- qcom,cpr-speed-bin-max-corners: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version to + the maximum virtual voltage corner corresponding to each fuse corner. The value N + corresponds to the number of fuse corners specified by qcom,cpr-fuse-corners. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as + a wildcard to match any PVS version values. + [2 - N+1]: => the max virtual voltage corner value corresponding to each fuse corner + for this speed bin, ordered from lowest voltage corner to highest + voltage corner. + No CPR target quotient scaling is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified, then quotient scaling is enabled for the highest voltage corner. If this property is + not specified, then no quotient scaling can take place. +- qcom,cpr-corner-map: Array of elements of fuse corner value for each virtual corner. + The location or 1-based index of an element in the list corresponds to + the virtual corner value. For example, the first element in the list is the fuse corner + value that virtual corner 1 maps to. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,cpr-corner-frequency-map: Array of tuples in which a tuple describes a corner to application processor frequency + mapping. + The 2 elements in one tuple are: + [0]: => a virtual voltage corner. + [1]: => the application processor frequency in Hz corresponding to the virtual corner. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,pvs-version-fuse-sel: Array of 4 elements to indicate where to read the pvs version of the processor, + and the fuse reading method. + The 4 elements with index[0..3] are: + [0]: => the fuse row number of the selector; + [1]: => LSB bit position of the bits; + [2]: => the number of bits; + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading. +- qcom,cpr-voltage-ceiling-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version + to the ceiling voltage to apply for each virtual voltage corner. The value N + corresponds to the number of virtual corners as specified by the number of elements + in the qcom,cpr-corner-map property. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as a + wildcard to match any PVS version values. + [2 - N+1]: => the ceiling voltage value in microvolts corresponding to each virtual + corner for this speed bin, ordered from lowest voltage corner to + highest voltage corner. + No ceiling override is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified and the speed bin + PVS version matches, then the per-virtual-corner ceiling + voltages will be used in place of the per-fuse-corner ceiling voltages defined in the + qcom,cpr-voltage-ceiling property. If this property is not specified, then the + per-fuse-corner ceiling voltages will always be used. +- qcom,cpr-voltage-floor-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version + to the floor voltage to apply for each virtual voltage corner. The value N + corresponds to the number of virtual corners as specified by the number of elements + in the qcom,cpr-corner-map property. + The elements in one tuple are: + [0]: => the speed bin of the CPU. It may use the value 0xffffffff as a + wildcard to match any speed bin values. + [1]: => the PVS version of the CPU. It may use the value 0xffffffff as a + wildcard to match any PVS version values. + [2 - N+1]: => the floor voltage value in microvolts corresponding to each virtual + corner for this speed bin, ordered from lowest voltage corner to + highest voltage corner. + No floor override is applied on chips which have a speed bin + PVS version + pair that does not appear in one of the tuples in this property. If the property is + specified and the speed bin + PVS version matches, then the per-virtual-corner floor + voltages will be used in place of the per-fuse-corner floor voltages defined in the + qcom,cpr-voltage-floor property. If this property is not specified, then the + per-fuse-corner floor voltages will always be used. +- qcom,cpr-floor-to-ceiling-max-range: Array of integer tuples of floor-to-ceiling max range values in microvolts + to be subtracted from the ceiling voltage values of each virtual corner. + Supported values are those greater than or equal 0, or (-1). The value 0 for a corner + implies that the floor value for that corner has to equal to its ceiling value. + The value (-1) for a corner implies that no modification to the default floor voltage + is required. The elements in a tuple are ordered from lowest voltage corner to highest + voltage corner. Each tuple must be of the length equal to the number of virtual corners + as specified by the number of elements in the qcom,cpr-corner-map property. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-dynamic-floor-override-adjustment must contain the same number of + tuples as qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then voltage adjustments defined in the second + qcom,cpr-dynamic-floor-override-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-dynamic-floor-override-adjustment must contain a single tuple which + is then applied unconditionally. +- qcom,cpr-virtual-corner-init-voltage-adjustment: Array of integer tuples of voltage adjustments in microvolts to be + added to the initial voltage values of each virtual corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length equal to the number of virtual corners as + specified by the number of elements in the qcom,cpr-corner-map property. If the + qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-virtual-corner-init-voltage-adjustment must contain the same number of + tuples as qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then voltage adjustments defined in the second + qcom,cpr-virtual-corner-init-voltage-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-virtual-corner-init-voltage-adjustment must contain a single tuple which + is then applied unconditionally. +- qcom,cpr-virtual-corner-quotient-adjustment: Array of integer tuples of quotient offsets to be added to + the scaled target quotient of each virtual corner. The elements + in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length equal to the number of virtual corners as + specified by the number of elements in the qcom,cpr-corner-map property. + If the qcom,cpr-fuse-version-map property is specified, then + qcom,cpr-virtual-corner-quotient-adjustment must contain the same number of tuples as + qcom,cpr-fuse-version-map. These tuples are then mapped one-to-one in the + order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then quotient adjustments defined in the second + qcom,cpr-virtual-corner-quotient-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-virtual-corner-quotient-adjustment must contain a single tuple which is then + applied unconditionally. +- qcom,cpr-cpus: Array of CPU phandles which correspond to the cores that this cpr-regulator + device must monitor when adjusting the voltage and/or target quotient based + upon the number of online cores or make sure that one of them must be online + when performing de-aging measurements. This property must be specified in order to + utilize the qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment or + qcom,cpr-online-cpu-virtual-corner-quotient-adjustment or qcom,cpr-aging-sensor-id properties. +- qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment: Array of tuples where each tuple specifies + the voltage adjustment for each corner. These adjustments apply to the + initial voltage of each corner. The size of each tuple must be equal + to qcom,cpr-fuse-corners if consumers request fuse corners or the length of + qcom,cpr-corner-map if consumers request virtual corners. In each tuple, the + value corresponds to the voltage adjustment when running at that corner at + init, from lowest to highest. The tuples must be organized into 1 group if + qcom,cpr-fuse-version-map is not specified or the same number of groups as + the number of tuples in qcom,cpr-fuse-version-map. The i-th group of tuples + corresponds to the voltage adjustments for i-th fuse version map tuple. In + each group, there are 1 plus length of qcom,cpr-cpus tuples, each tuple + corresponds to the number of cores online, from 0 to the number of elements + in qcom,cpr-cpus. +- qcom,cpr-online-cpu-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a + given virtual corner may be reduced to the per number of cores online, + per-virtual corner ceiling voltage value. This property takes precedence + over qcom,cpr-scaled-init-voltage-as-ceiling if both are specified. +- qcom,cpr-online-cpu-virtual-corner-quotient-adjustment: Array of tuples where each tuple specifies + the quotient adjustment for each corner. These adjustments will be applied + to each corner at run time. The size of each tuple must be equal to + qcom,cpr-fuse-corners if consumers request fuse corners or the length of + qcom,cpr-corner-map if consumers request virtual corners. In each tuple, + the value corresponds to the quotient adjustment when running at that corner, + from lowest to highest. The tuples must be organized into 1 group if + qcom,cpr-fuse-version-map is not specified or the same number of groups + as the number of tuples in qcom,cpr-fuse-version-map. The i-th group of + tuples corresponds to the quotient adjustments for i-th fuse version map + tuple. In each group, there are 1 plus length of qcom,cpr-cpus tuples, + each tuple corresponds to the number of cores online, from 0 to the + number of elements in qcom,cpr-cpus. +- qcom,cpr-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given virtual + corner may be reduced to the per-fuse-corner initial voltage fuse value. +- qcom,cpr-scaled-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given + virtual corner may be reduced to the interpolated, per-virtual-corner initial + voltage value. Note that if both qcom,cpr-init-voltage-as-ceiling and + qcom,cpr-scaled-init-voltage-as-ceiling are specified, then + qcom,cpr-scaled-init-voltage-as-ceiling will take precedence since the interpolated + voltages are necessarily less than or equal to the fused initial voltage values. +- qcom,cpr-voltage-scaling-factor-max: Array of values which define the maximum allowed scaling factor to apply + when calculating per-corner initial voltage values for each fuse corner. The + array must be of length equal to the value of the qcom,cpr-fuse-corners property. + Each element in the array maps to the fuse corners in increasing order. + The elements have units of uV/MHz. Each element corresponds to 'max_factor' in + the following equation: + init_voltage_min(f) = fuse_init_voltage(f) - (fuse_f_max - f) * max_factor + If this property is not specified, then the initial voltage for each virtual + corner will be set to the initial voltage of the associated fuse corner. +- qcom,cpr-quot-adjust-scaling-factor-max: Array of values which define the maximum allowed scaling factor to + apply when calculating per-virtual-corner target quotients for each fuse + corner. Two data formats are allowed for this property. The primary one + requires that the array be of length equal to the value of the + qcom,cpr-fuse-corners property. When using this format, each element in the + array maps to the fuse corners in increasing order. The second depreciated + format allows for only a single element to be specified which defines the + maximum scaling factor for the highest fuse corner. In this case, a value of + 0 is assumed for the lower fuse corners. The elements of this property have + units of QUOT/GHz. Each element corresponds to 'max_factor' in the following + equation: + quot_min(f) = fuse_quot(f) - (fuse_f_max - f) * max_factor / 1000 + where f and fuse_f_max have units of MHz. + This property is required if qcom,cpr-speed-bin-max-corners is present. +- qcom,cpr-fuse-init-voltage: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get an initial voltage for a fuse corner. The fuse values + are encoded as voltage steps higher or lower than the voltages defined in + qcom,cpr-voltage-ceiling. Each step corresponds to the voltage defined by + the qcom,cpr-init-voltage-step property. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The quadruples are ordered from the lowest voltage fuse corner to the + highest voltage fuse corner. + A given cpr-regulator device must have either qcom,cpr-fuse-init-voltage + specified or qcom,pvs-voltage-table (and its associated properties). +- qcom,cpr-fuse-redun-init-voltage: Array of quadruples in which each quadruple specifies a fuse location + to read in order to get the redundant initial voltage for a fuse corner. + This property is the same as qcom,cpr-fuse-init-voltage except that it is + only utilized if a chip is configured to use the redundant set of fuse + values. This property is required if qcom,cpr-fuse-redun-sel and + qcom,cpr-fuse-init-voltage are specified. +- qcom,cpr-init-voltage-ref: Array of reference voltages in microvolts used when decoding the initial + voltage fuse values. The elements in the array are ordered from lowest + voltage corner to highest voltage corner. This property must be of length + defined by qcom,cpr-fuse-corners. + This property is required if qcom,cpr-fuse-init-voltage is present. +- qcom,cpr-init-voltage-step: The voltage step size in microvolts of the CPR initial voltage fuses described by the + qcom,cpr-fuse-init-voltage property. + This property is required if qcom,cpr-fuse-init-voltage is present. +- mem-acc-supply: Regulator to vote for the memory accelerator configuration. + Not Present: memory accelerator configuration not supported. +- qcom,mem-acc-corner-map: Array of integer which defines the mapping from mem-acc corner value for each + virtual corner. Each element is a mem-acc state for the corresponding virtual corner. + The elements in the array are ordered from lowest voltage corner to highest voltage corner. +- qcom,fuse-remap-source: Array of quadruples in which each quadruple specifies a fuse location to + remap. The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => the number of bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The fuse bits for all quadruples are packed together in the order specified + into 64-bit virtual fuse rows beginning at the row number defined in the + qcom,fuse-remap-base-row property. The remapped rows may be used by any + other properties. + Example: + qcom,fuse-remap-base-row = <1000>; + qcom,fuse-remap-source = + <13 57 2 0>, + <14 30 3 0>, + <20 1 7 0>, + <40 47 120 0>; + + This results in the following bit remapping: + + Row Bits Remap Row Remap Bits + 13 57..58 --> 1000 0..1 + 14 30..32 --> 1000 2..4 + 20 1..7 --> 1000 5..11 + 40 47..63 --> 1000 12..28 + 41 0..34 --> 1000 29..63 + 41 35..63 --> 1001 0..28 + 42 0..34 --> 1001 29..63 + 42 35..38 --> 1002 0..3 + + A tuple like this could then be used to reference some of the + concatenated bits from rows 13, 14, and 20: + + qcom,cpr-fuse-init-voltage = <1000 0 6 0>; +- qcom,fuse-remap-base-row: Integer which defines the virtual row number to use as a base when remapping + fuse bits. The remap base row number can be any value as long as it is + greater than all of the real row numbers addressed in other properties of + the cpr-regulator device node. This property is required if + qcom,fuse-remap-source is specified. +- qcom,cpr-quot-min-diff: Integer which defines the minimum target-quotient difference between + the highest and (highest - 1) fuse corner to keep CPR enabled. If this + property is not specified a default value of 50 is used. +- qcom,cpr-fuse-quot-offset: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get the quotient offset for a fuse corner. The fuse values + are encoded as the difference between quotients of that fuse corner and its + adjacent lower fuse corner divided by an unpacking multiplier value defined + under qcom,cpr-fuse-quot-offset-scale property. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The quadruples are ordered from the lowest fuse corner to the highest + fuse corner. + Quotient offset read from the fuse locations above can be overridden with + the property qcom,cpr-quot-adjust-scaling-factor-max. +- qcom,cpr-fuse-quot-offset-scale: Array of integer values which defines the multipliers to decode the quotient offsets + of each fuse corner. The elements in the array are ordered from the lowest voltage fuse corner + to the highest voltage fuse corner. If this property is not present, then all target quotient + parameters are assumed to have a multiplier of 1 (i.e. no decoding needed). +- qcom,cpr-redun-fuse-quot-offset: Array of quadruples in which each quadruple specifies a fuse location to + read in order to get the redundant quotient offset for a fuse corner. This + property is the same as qcom,cpr-fuse-quot-offset except that it is only + utilized if a chip is configured to use the redundant set of fuse values. +- qcom,cpr-fuse-min-quot-diff: Array of values which define the minimum difference allowed between the adjusted + quotients of the fuse corners. The length of the array should be equal to the value + of the qcom,cpr-fuse-corners property. Where each element in the array maps to the + fuse corners in increasing order. +- qcom,cpr-min-quot-diff-adjustment: Array of integer tuples of target quotient offsets to be added to + the adjusted target quotients of each fuse corner. When the quotient difference + between two adjacent fuse corners is insufficient, the quotient for the higher fuse corner is + replaced with that of the lower fuse corner plus the adjustment value. + The elements in a tuple are ordered from lowest voltage corner to highest voltage corner. + Each tuple must be of the length defined by qcom,cpr-fuse-corners. + If the qcom,cpr-fuse-version-map property is specified, then qcom,cpr-min-quot-diff-adjustment + must contain the same number of tuples as qcom,cpr-fuse-version-map. These tuples are then mapped + one-to-one in the order specified. E.g. if the second qcom,cpr-fuse-version-map tuple matches + for a given device, then the quotient adjustments defined in the + second qcom,cpr-min-quot-diff-adjustment tuple will be applied. If the + qcom,cpr-fuse-version-map property is not specified, then + qcom,cpr-min-quot-diff-adjustment must contain a single tuple which is then + applied unconditionally. The qcom,cpr-min-quot-diff-adjustment property must be specified + if the qcom,cpr-fuse-min-quot-diff property is specified. +- qcom,cpr-skip-voltage-change-during-suspend: Boolean property which indicates that the CPR voltage + should not be adjusted based upon the number of online cores while + entering or exiting system suspend. +- rpm-apc-supply: Regulator to notify RPM of the APC operating + corner +- qcom,rpm-apc-corner-map: Array of integers which define the mapping of + the RPM corner to the corresponding APC virtual + corner. This property must be defined if + 'rpm-apc-supply' is present. +- qcom,vsens-corner-map: Array of integers which define the mapping of the VSENS corner to the + corresponding APC fuse corner. The qcom,vsens-corner-map and + vdd-vsense-corner-supply properties must both be specified for a given + cpr-regulator device or neither must be specified. +- vdd-vsens-corner-supply: Regulator to specify the current operating fuse corner to the Voltage Sensor. +- vdd-vsens-voltage-supply: Regulator to specify the corner floor/ceiling voltages to the Voltage Sensor. +- qcom,cpr-aging-sensor-id: Array of CPR sensor IDs to be used in the CPR de-aging algorithm. The number + of values should be equal to number of sensors selected for age calibration. + If this property is not specified, then the de-aging procedure is not enabled. +- qcom,cpr-de-aging-allowed: Integer values that specify whether the CPR de-aging procedure is allowed or + not for a particular fuse revision. If the qcom,cpr-fuse-version-map + property is specified, then qcom,cpr-de-aging-allowed must contain the same number + of elements as there are tuples in qcom,cpr-fuse-version-map. If qcom,cpr-fuse-version-map + is not specified, then qcom,cpr-de-aging-allowed must contain a single value that + is used unconditionally. An element value of 1 means that the CPR de-aging procedure + can be performed for parts with the corresponding fuse revision. An element value of 0 + means that CPR de-aging cannot be performed. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ref-corner: The vdd-apc-supply reference virtual voltage corner to be set during the CPR de-aging + measurements. This corner value is needed to set appropriate voltage on + the dependent voltage rails such as vdd-mx and mem-acc. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ref-voltage: The vdd-apc-supply reference voltage in microvolts to be set during the + CPR de-aging measurements. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-max-aging-margin: The maximum allowed aging voltage margin in microvolts. This is used to limit + the calculated aging voltage margin. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-non-collapsible-sensors: Array of CPR sensor IDs which are in non-collapsible domain. The sensor IDs not + specified in the array should be bypassed for the de-aging procedure. The number of + elements should be less than or equal to 32. The values of the array elements should + be greater than or equal to 0 and less than or equal to 31. + This property is required for power-domains with bypass mux present in HW. + This property can be required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-ro-scaling-factor: The aging ring oscillator (RO) scaling factor with units of QUOT/V. + This value is used for calculating a voltage margin from RO measurements. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-ro-scaling-factor: Array of scaling factors with units of QUOT/V for each ring oscillator ordered + from the lowest to the highest RO. These values are used to calculate + the aging voltage margin adjustment for all of the ROs. Since CPR2 supports + exactly 8 ROs, the array must contain 8 elements corresponding to RO0 through RO7 in order. + If a given RO is unused for a fuse corner, then its scaling factor may be specified as 0. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-aging-derate: Array of scaling factors which define the amount of derating to apply to the reference + aging voltage margin adjustment for each of the fuse corners. Each element has units + of uV/mV. This property must be of length defined by qcom,cpr-fuse-corners. + The elements are ordered from the lowest to the highest fuse corner. + This property is required if the qcom,cpr-aging-sensor-id property has been specified. +- qcom,cpr-fuse-aging-init-quot-diff: Array of quadruples in which each quadruple specifies a fuse location to read in + order to get an initial quotient difference. The difference between quot min and quot max + is fused as the initial quotient difference. + The 4 elements in one quadruple are: + [0]: => the fuse row number of the bits + [1]: => LSB bit position of the bits + [2]: => number of the bits + [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading + The number of quadruples should be equal to the number of values specified in + the qcom,cpr-aging-sensor-id property. This property is required if + the qcom,cpr-aging-sensor-id property has been specified. +Example: + apc_vreg_corner: regulator@f9018000 { + status = "okay"; + compatible = "qcom,cpr-regulator"; + reg = <0xf9018000 0x1000>, <0xfc4b8000 0x1000>; + reg-names = "rbcpr", "efuse_addr"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + qcom,cpr-fuse-corners = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <12>; + + qcom,pvs-fuse = <22 6 5 1>; + qcom,pvs-fuse-redun-sel = <22 24 3 2 1>; + qcom,pvs-fuse-redun = <22 27 5 1>; + + qcom,pvs-voltage-table = + <1050000 1150000 1350000>, + <1050000 1150000 1340000>, + <1050000 1150000 1330000>, + <1050000 1150000 1320000>, + <1050000 1150000 1310000>, + <1050000 1150000 1300000>, + <1050000 1150000 1290000>, + <1050000 1150000 1280000>, + <1050000 1150000 1270000>, + <1050000 1140000 1260000>, + <1050000 1130000 1250000>, + <1050000 1120000 1240000>, + <1050000 1110000 1230000>, + <1050000 1100000 1220000>, + <1050000 1090000 1210000>, + <1050000 1080000 1200000>, + <1050000 1070000 1190000>, + <1050000 1060000 1180000>, + <1050000 1050000 1170000>, + <1050000 1050000 1160000>, + <1050000 1050000 1150000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>, + <1050000 1050000 1140000>; + qcom,cpr-voltage-ceiling = <1050000 1150000 1280000>; + qcom,cpr-voltage-floor = <1050000 1050000 1100000>; + vdd-apc-supply = <&pm8226_s2>; + vdd-apc-optional-prim-supply = <&ncp6335d>; + vdd-apc-optional-sec-supply = <&fan53555>; + vdd-mx-supply = <&pm8226_l3_ao>; + qcom,vdd-mx-vmax = <1350000>; + qcom,vdd-mx-vmin-method = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <1>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <15>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <5>; + qcom,cpr-gcnt-time = <1>; + qcom,cpr-clamp-timer-interval = <1>; + qcom,cpr-apc-volt-step = <5000>; + + qcom,vsens-corner-map = <1 2 2>; + vdd-vsens-corner-supply = <&vsens_apc0_corner>; + vdd-vsens-voltage-supply = <&vsens_apc0_voltage>; + + rpm-apc-supply = <&rpm_apc_vreg>; + qcom,rpm-apc-corner-map = <4 4 5 5 7 7 7 7 7 7 7 7>; + + qcom,cpr-fuse-row = <138 1>; + qcom,cpr-fuse-bp-cpr-disable = <36>; + qcom,cpr-fuse-bp-scheme = <37>; + qcom,cpr-fuse-target-quot = <24 12 0>; + qcom,cpr-fuse-target-quot-size = <12 12 12>; + qcom,cpr-fuse-ro-sel = <54 38 41>; + qcom,cpr-fuse-revision = <140 26 2 0>; + qcom,cpr-fuse-redun-sel = <138 57 1 1 1>; + qcom,cpr-fuse-redun-row = <139 1>; + qcom,cpr-fuse-redun-target-quot = <24 12 0>; + qcom,cpr-fuse-redun-ro-sel = <46 36 39>; + qcom,cpr-fuse-cond-min-volt-sel = <54 42 6 7 1>; + qcom,cpr-cond-min-voltage = <1140000>; + qcom,cpr-fuse-uplift-sel = <22 53 1 0 0>; + qcom,cpr-uplift-voltage = <50000>; + qcom,cpr-uplift-quotient = <0 0 120>; + qcom,cpr-uplift-max-volt = <1350000>; + qcom,cpr-uplift-speed-bin = <1>; + qcom,speed-bin-fuse-sel = <22 0 3 0>; + qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3>; + qcom,cpr-corner-frequency-map = + <1 300000000>, + <2 384000000>, + <3 600000000>, + <4 787200000>, + <5 998400000>, + <6 1094400000>, + <7 1190400000>, + <8 1305600000>, + <9 1344000000>, + <10 1401600000>, + <11 1497600000>, + <12 1593600000>; + qcom,pvs-version-fuse-sel = <22 4 2 0>; + qcom,cpr-speed-bin-max-corners = + <0 1 2 4 7>, + <1 1 2 4 12>, + <2 1 2 4 10>, + <5 1 2 4 14>; + qcom,cpr-fuse-target-quot-scale = + <0 1>, + <0 1>, + <0 1>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 650 650>; + qcom,cpr-fuse-quot-offset = + <138 53 5 0>, + <138 53 5 0>, + <138 48 5 0>, + <138 58 5 0>; + qcom,cpr-fuse-redun-quot-offset = + <200 53 5 0>, + <200 53 5 0>, + <200 48 5 0>, + <200 58 5 0>; + qcom,cpr-fuse-init-voltage = + <27 36 6 0>, + <27 18 6 0>, + <27 0 6 0>; + qcom,cpr-fuse-redun-init-voltage = + <140 36 6 0>, + <140 18 6 0>, + <140 0 6 0>; + qcom,cpr-init-voltage-ref = <1050000 1150000 1280000>; + qcom,cpr-init-voltage-step = <10000>; + qcom,cpr-voltage-ceiling-override = + <1 1 1050000 1050000 1150000 1150000 1280000 + 1280000 1280000 1280000 1280000 1280000 + 1280000 1280000>; + qcom,cpr-voltage-floor-override = + <1 1 1050000 1050000 1050000 1050000 1060000 + 1070000 1080000 1090000 1100000 1100000 + 1100000 1100000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + + qcom,cpr-fuse-version-map = + <0xffffffff 0xffffffff 2 4 4 4>, + <0xffffffff 0xffffffff 2 6 6 6>, + <0xffffffff 0xffffffff 3 4 4 4>; + qcom,cpr-quotient-adjustment = + <0 0 (-210)>, + <0 0 (-60)>, + <0 0 (-94)>; + qcom,cpr-quot-offset-adjustment = + <0 0 (-5)>; + qcom,cpr-init-voltage-adjustment = + <0 0 (-100000)>, + <0 0 (-100000)>, + <0 0 (-45000)>; + qcom,cpr-fuse-min-quot-diff = <0 0 40>; + qcom,cpr-min-quot-diff-adjustment = + <0 0 0>, + <0 0 72>, + <0 0 104>; + qcom,cpr-floor-to-ceiling-max-range = + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>, + <(-1) (-1) (-1) (-1) (-1) (-1) (-1) 50000 50000 50000 50000 50000>; + qcom,cpr-virtual-corner-init-voltage-adjustment = + <0 0 0 (-10000) 0 0 0 0 0 0 0 0>, + <0 0 0 0 0 0 0 0 0 0 0 (-20000)>, + <0 0 0 0 0 0 0 0 0 0 0 (-30000)>; + qcom,cpr-virtual-corner-quotient-adjustment = + <0 0 0 100 0 0 0 0 0 0 0 0>, + <0 0 0 0 0 0 0 0 0 0 0 (-300)>, + <0 0 0 (-60) 0 0 0 0 0 0 0 0>; + qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment = + /* 1st fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 2nd fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 3rd fuse version tuple matched */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */ + <0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */ + <0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */ + qcom,cpr-online-cpu-virtual-corner-quotient-adjustment = + /* 1st fuse version tuple matched */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */ + <0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 2nd fuse version tuple matched */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */ + <0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */ + <0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */ + /* 3rd fuse version tuple matched */ + <0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 0 CPUs online */ + <0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 1 CPUs online */ + <0 0 0 (-11) (-11) (-11) (-11) (-11) (-21) 0 (-21) (-21)>, /* 2 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */ + <0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */ + qcom,cpr-allowed = + <0>, + <1>, + <1>; + + qcom,fuse-remap-base-row = <1000>; + qcom,fuse-remap-source = + <140 7 3 0>, + <138 45 5 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + + qcom,cpr-aging-sensor-id = <17, 18>; + qcom,cpr-aging-ref-corner = <4>; + qcom,cpr-aging-ref-voltage = <1050000>; + qcom,cpr-max-aging-margin = <15000>; + qcom,cpr-de-aging-allowed = + <0>, + <0>, + <1>; + qcom,cpr-non-collapsible-sensors= <7 12 17 22>; + qcom,cpr-aging-ro-scaling-factor = <3500>; + qcom,cpr-ro-scaling-factor = <0 2500 2500 2500 0 0 0 0>; + qcom,cpr-aging-derate = <1000 1000 1250>; + qcom,cpr-fuse-aging-init-quot-diff = + <101 0 8 0>, + <101 8 8 0>; + }; diff --git a/bindings/regulator/mem-acc-regulator.txt b/bindings/regulator/mem-acc-regulator.txt new file mode 100755 index 00000000..a681f485 --- /dev/null +++ b/bindings/regulator/mem-acc-regulator.txt @@ -0,0 +1,288 @@ +Qualcomm Technologies, Inc. Memory Accelerator + +Memory accelerator configures the power-mode (corner) for the +accelerator. + +Required properties: +- compatible: Must be "qcom,mem-acc-regulator" +- regulator-name: A string used to describe the regulator +- regulator-min-microvolt: Minimum corner value as min constraint, which + should be 1 for SVS corner +- regulator-max-microvolt: Maximum corner value as max constraint, which + should be 4 for SUPER_TURBO or 3 for TURBO + +Optional properties: +- reg: Register addresses for acc-sel-l1, acc-sel-l2 control, acc-en, + MEM ACC eFuse address, acc-l1-custom , acc-l2-custom, + mem-acc-type1, mem-acc-type2, mem-acc-type3, mem-acc-type4, + mem-acc-type5 and mem-acc-type6. +- reg-names: Register names. Must be "acc-sel-l1", + "acc-sel-l2", "acc-en", "efuse_addr", + "acc-l1-custom", "acc-l2-custom", "mem-acc-type1", + "mem-acc-type2", "mem-acc-type3", "mem-acc-type4", + "mem-acc-type5", "mem-acc-type6". + A given mem-acc-regulator driver must have "acc-sel-l1" or + "acc-sel-l2" or "mem-acc-type*" reg-names property and + related register address property. +- qcom,corner-acc-map Array which maps the APC (application processor) + corner value to the accelerator corner. The number of elements + in this property defines the number of accelerator corners. + Either qcom,corner-acc-map property or qcom,cornerX-reg-config + properties should be specified. +- qcom,acc-en-bit-pos Array which specifies bit positions in the + 'acc-en' register. Setting these bits forces the + the acclerator to use the corner value specified + in the 'acc-sel-l1' and 'acc-sel-l2' register. +- qcom,acc-sel-l1-bit-size Integer which specifies the number of bits in + the 'acc-sel-l1' register which define each L1 + select parameter. If this property is not + specified, then a default value of 2 is assumed. +- qcom,acc-sel-l1-bit-pos Array which specifies bit positions in the + 'acc-sel-l1' register. Each element in this array + is the LSB of an N-bit value where 'N' is + defined by the qcom,acc-sel-l1-bit-size + property. This N-bit value specifies the corner + value used by the accelerator for the L1 cache. +- qcom,acc-sel-l2-bit-size Integer which specifies the number of bits in + the 'acc-sel-l2' register which define each L2 + select parameter. If this property is not + specified, then a default value of 2 is assumed. +- qcom,acc-sel-l2-bit-pos Array which specifies bit positions in the + 'acc-sel-l2' register. Each element in this array + is the LSB of an N-bit value where 'N' is + defined by the qcom,acc-sel-l2-bit-size + property. This N-bit value specifies the corner + value used by the accelerator for the L2 cache. +- qcom,l1-acc-custom-data: Array which maps APC corner values to L1 ACC custom data values. + The corresponding custom data is written into the custom register + while switching between APC corners. The custom register address + is specified by "acc-11-custom" reg-property. The length of the array + should be equal to number of APC corners. +- qcom,l2-acc-custom-data: Array which maps APC corner values to L2 ACC custom data values. + The corresponding custom data is written into the custom register + while switching between APC corners. The custom register address + is specified by "acc-l2-custom" reg-property. The length of the array + should be equal to number of APC corners. +- qcom,override-acc-fuse-sel: Array of 4 elements which specify the way to read the override fuse. + The override fuse value is used by the qcom,override-fuse-version-map + to identify the correct set of override properties. + The 4 elements with index [0..4] are: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,override-fuse-version-map: Array of integers which each match to a override fuse value. + Any element in a tuple may use the value 0xffffffff as a wildcard. + The index of the first value (in the array) which matches the override fuse + is used to select the right tuples from the other override properties. +- qcom,override-corner-acc-map: Array of tuples which overrides the existing acc-corner map + (specified by qcom,corner-acc-map) with corner values selected + from this property. "qcom,override-corner-acc-map" must contain the + same number of tuples as "qcom,override-fuse-version-map". These tuples + are then mapped one-to-one in the order specified. If the + "qcom,override-fuse-version-map" property is not specified, then + "qcom,override-corner-acc-map" must contain a single tuple which is then + applied unconditionally. +- qcom,override-l1-acc-custom-data: Array of tuples of which overrides the existing l1-acc-custom data + (specified by qcom,l1-acc-custom-data), with values specified in this property. + The corresponding custom data is written into the custom register while + switching between APC corners. The custom register address is specified by + "acc-11-custom" reg-property. This property can only be specified if the + "qcom,l1-acc-custom-data" is already defined. If the + "qcom,override-fuse-version-map" property is specified, then + qcom,override-l1-acc-custom-data must contain the same number of tuples + as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-l1-acc-custom-data" must contain a single + tuple which is then applied unconditionally. +- qcom,override-l2-acc-custom-data: Array of tuples of which overrides the existing l1-acc-custom data + (specified by qcom,l2-acc-custom-data), with values specified in this property. + The corresponding custom data is written into the custom register while + switching between APC corners. The custom register address is specified by + "acc-12-custom" reg-property. This property can only be specified if the + "qcom,l2-acc-custom-data" is already defined. If the + "qcom,override-fuse-version-map" property is specified, then + "qcom,override-l2-acc-custom-data" must contain the same number of tuples + as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-l2-acc-custom-data" must contain a single + tuple which is then applied unconditionally. +- qcom,mem-acc-type1: Array which specifies the value to be written to the mem acc type1 register for each fuse + corner, from the lowest fuse corner to the highest fuse corner. The length of the array + must be equal to the number of APC fuse corners. This property must be present if reg names + specifies mem-acc-type1. +- qcom,mem-acc-type2: Same as qcom,mem-acc-type1 except for mem acc type2 register. +- qcom,mem-acc-type3: Same as qcom,mem-acc-type1 except for mem acc type3 register. +- qcom,mem-acc-type4: Same as qcom,mem-acc-type1 except for mem acc type4 register. +- qcom,mem-acc-type5: Same as qcom,mem-acc-type1 except for mem acc type5 register. +- qcom,mem-acc-type6: Same as qcom,mem-acc-type1 except for mem acc type6 register. +- qcom,acc-reg-addr-list: Array of register addresses which need to be programmed during any corner switch. + This property can be used when multi register configuration is needed during a corner switch. +- qcom,acc-init-reg-config: Array of tuples specify the multi register configuration sequence need to be programmed + one time during device boot. + The format of each tuple as below: + <register-address-index, value> + Where register-address-index is used as an index in to qcom,acc-reg-addr-list property + to get the required register address and the value is programmed in to the corresponding + mapped register address. This property is required if qcom,acc-corner-addr-val-map + property specified. +- qcom,cornerX-reg-config: Array of tuples specify the multi register configuration sequence need to be programmed + when switching from acc corner X to any other corner. The possible values for X are {1, N}, + where N is the value defined in qcom,num-acc-corners. + The format of each tuple as below: + <register-address-index, value> + Where register-address-index is used as an index in to qcom,acc-reg-addr-list property + to get the required register address and the value is programmed in to the corresponding + mapped register address. Same index can be used multiple times when the register is + required to configure multiple times with different values in the sequence. + The number of register configuration sequences should be equal to N, where N is the + value specified in qcom,num-acc-corners property. Also, the number of tuples in each + register configuration sequence should be same and must be equal to the maximum required + register configurations in any sequence. The invalid register configuration can be + specified as <(-1) (-1)>. This property can only be specified when qcom,acc-corner-addr-val-map + property already defined. Either this property or qcom,corner-acc-map should be specified. +- qcom,num-acc-corners: The number of acc corners supported. This property is required if qcom,cornerX-reg-config + property specified. +- qcom,boot-acc-corner: The acc corner used during device boot. This property is required if qcom,cornerX-reg-config + property specified. +- qcom,override-cornerX-reg-config: A grouping of register configuration sequence lists. Each list is same as + the qcom,cornerX-reg-config property. The possible values for X are {1, N} where N is + the value defined in qcom,num-acc-corners. This property is used to specify the different + register configuration sequence lists and select one list among them based on the selected + index in qcom,override-fuse-version-map property. The selected list overrides the existing + register configuration sequence list specified in "qcom,cornerX-reg-config". If the + "qcom,override-fuse-version-map" property is specified, then + "qcom,override-cornerX-reg-config" must contain the same number of register + configuration sequence lists as the number of tuples in "qcom,override-fuse-version-map". + These register configuration sequence lists are then mapped one-to-one + in the order specified. If the qcom,override-fuse-version-map property is + not specified, then "qcom,override-cornerX-reg-config" must contain a single + register configuration sequence list which is then applied unconditionally. + This property can only be specified if qcom,cornerX-reg-config property is already defined. +- qcom,override-acc-range-fuse-list: Array of tuples define the selection parameters used for selecting the override + mem-acc configuration. The fused values for these selection parameters are used by the + qcom,override-fuse-range-map to identify the correct set of override properties. + Each tuple contains 4 elements as defined below: + [0] => the fuse row number of the selector + [1] => LSB bit position of the bits + [2] => number of bits + [3] => fuse reading method, 0 for direct reading or 1 for SCM reading +- qcom,override-fuse-range-map: Array of tuples where each tuple specifies the allowed range for all the selection parameters + defined in qcom,override-acc-range-fuse-list. The fused values of these selection parameters + are compared against their allowed range in each tuple starting from 0th tuple and use the + first matched tuple index to select the right tuples from the other override properties. + Either qcom,override-fuse-range-map or qcom,override-fuse-version-map is used to select + the override configuration. The qcom,override-fuse-range-map is used if both the + properties are specified. + +mem_acc_vreg_corner: regulator@fd4aa044 { + compatible = "qcom,mem-acc-regulator"; + reg = <0xfd4aa048 0x1>, <0xfd4aa044 0x1>, <0xfd4af000 0x1>, + <0x58000 0x1000>, <0x01942124 0x4>, <0xf900d084 1>, + <0xf900d088 1>, <0xf900d08c 1>, <0xf900d090 1>; + reg-names = "acc-en", "acc-sel-l1" , "acc-sel-l2", + "efuse_addr", "acc-l2-custom", "mem-acc-type1", + "mem-acc-type2", "mem-acc-type3", "mem-acc-type4"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,acc-en-bit-pos = <0>; + qcom,acc-sel-l1-bit-pos = <0>; + qcom,acc-sel-l2-bit-pos = <0>; + qcom,acc-sel-l1-bit-size = <2>; + qcom,acc-sel-l2-bit-size = <2>; + qcom,corner-acc-map = <0 1 3>; + qcom,l2-acc-custom-data = <0x0 0x3000 0x3000>; + + qcom,override-acc-fuse-sel = <0 52 2 0>; + qcom,override-fuse-version-map = <0>, + <2>, + <(-1)>; + qcom,override-acc-range-fuse-list = + <37 40 3 0>, + <36 30 8 0>; + qcom,override-fuse-range-map = + <0 0>, < 0 0>, <49 63>, + <1 1>, < 0 0>, <50 63>, + <0 1>, < 95 255>, < 0 63>; + qcom,override-corner-acc-map = <0 0 1>, + <0 1 2>, + <0 1 1>; + qcom,override-l2-acc-custom-data = <0x0 0x0 0x3000>, + <0x0 0x3000 0x3000>, + <0x0 0x0 0x0>; + qcom,mem-acc-type1 = <0x02 0x02 0x00>; + qcom,mem-acc-type2 = <0x02 0x02 0x00>; + qcom,mem-acc-type3 = <0x02 0x02 0x00>; + qcom,mem-acc-type4 = <0x02 0x02 0x00>; + + qcom,acc-reg-addr-list = <0x01942130 0x01942124 0x01942120>; + qcom,acc-init-reg-config = <1 0x55> <2 0x02>; + + qcom,num-acc-corners = <3>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>; /* 1 -> 3 */ + + qcom,corner2-reg-config = + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>; /* 2 -> 3 */ + + qcom,corner3-reg-config = + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */ + + qcom,override-corner1-reg-config = + /* 1st fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 1 -> 3 */ + + /* 2nd fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 1 -> 3 */ + + /* 3rd fuse version tuple matched */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */ + < 1 0x155>, < 3 0x22>, < 3 0x155>, /* 1 -> 2 */ + < 1 0x0>, < 2 0x155>, < 3 0x144>; /* 1 -> 3 */ + + qcom,override-corner2-reg-config = + /* 1st fuse version tuple matched */ + < 1 0x144>, < 1 0x11>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x0>, < 3 0x155>, /* 2 -> 3 */ + + /* 2nd fuse version tuple matched */ + < 1 0x144>, < 2 0x133>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, < 1 0x33>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x133>, < 2 0x0>, < 3 0x155>, /* 2 -> 3 */ + + /* 3rd fuse version tuple matched */ + < 1 0x144>, < 1 0x11>, <(-1) (-1)>, /* 2 -> 1 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */ + < 1 0x155>, < 2 0x22>, < 3 0x155>; /* 2 -> 3 */ + + + qcom,override-corner3-reg-config = + /* 1st fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */ + + /* 2nd fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */ + + /* 3rd fuse version tuple matched */ + < 1 0x0>, < 2 0x155>, <(-1) (-1)>, /* 3 -> 1 */ + < 1 0x155>, < 3 0x11>, <(-1) (-1)>, /* 3 -> 2 */ + <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */ +}; diff --git a/bindings/regulator/spm-regulator.txt b/bindings/regulator/spm-regulator.txt new file mode 100755 index 00000000..c3241577 --- /dev/null +++ b/bindings/regulator/spm-regulator.txt @@ -0,0 +1,61 @@ +Qualcomm Technologies Inc. SPM Regulators + +spm-regulator is a regulator device which supports PMIC processor supply +regulators via the SPM module. + +Required properties: +- compatible: Must be "qcom,spm-regulator" +- reg: Specifies the SPMI address and size for this regulator device +- regulator-name: A string used as a descriptive name for the regulator + +Required structure: +- A qcom,spm-regulator node must be a child of an SPMI node that has specified + the spmi-slave-container property + +Optional properties: +- qcom,mode: A string which specifies the mode to use for the regulator. + Supported values are "pwm" and "auto". PWM mode is more + robust, but draws more current than auto mode. If this + property is not specified, then the regulator will remain + in whatever mode hardware or bootloaders set it to. +- qcom,cpu-num: Specifies which CPU this regulator powers. This property is + not need when the SPM regulator is shared between all CPUs. +- qcom,bypass-spm: Boolean flag which indicates that voltage control should not + be managed by an SPM. Instead, the voltage should be + controlled via SPMI. +- qcom,max-voltage-step: Maximum single voltage step size in microvolts. +- qcom,recal-mask: Bit mask of the APSS clusters to recalibrate after each + voltage change. Bit 0 corresponds to the first cluster, + bit 1 corresponds to the second cluster, and so on. + +Optional structure: +- A child node may be specified within a qcom,spm-regulator node which defines + an additional regulator which controls the AVS minimum and maximum + voltage limits. +- The AVS child node must contain these properties defined in regulator.txt: + regulator-name, regulator-min-microvolt, regulator-max-microvolt. + +All properties specified within the core regulator framework can also be used. +These bindings can be found in regulator.txt. + +Example: + qcom,spmi@fc4c0000 { + + qcom,pm8226@1 { + spmi-slave-container; + + spm-regulator@1700 { + compatible = "qcom,spm-regulator"; + regulator-name = "8226_s2"; + reg = <0x1700 0x100>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + + avs-limit-regulator { + regulator-name = "8226_s2_avs_limit"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1275000>; + } + }; + }; + }; diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt index 8d488c9c..aa535e6c 100755 --- a/bindings/remoteproc/qcom,adsp.txt +++ b/bindings/remoteproc/qcom,adsp.txt @@ -52,6 +52,9 @@ on the Qualcomm Technologies inc ADSP Hexagon core. "qcom,lemans-cdsp1-pas" "qcom,lemans-gpdsp0-pas" "qcom,lemans-gpdsp1-pas" + "qcom,kona-adsp-pas" + "qcom,kona-cdsp-pas" + "qcom,kona-slpi-pas" - interrupts-extended: Usage: required @@ -166,6 +169,10 @@ on the Qualcomm Technologies inc ADSP Hexagon core. Value type: <stringlist> Definition: must be "stop" +- legacy-wlan: + Usage: optional + Value type: <none> + Definition: indicates the presence of legacy WLAN = SUBNODES The adsp node may have an subnode named either "smd-edge" or "glink-edge" that diff --git a/bindings/remoteproc/qcom,spss.txt b/bindings/remoteproc/qcom,spss.txt index b9f8ef60..568feb3d 100755 --- a/bindings/remoteproc/qcom,spss.txt +++ b/bindings/remoteproc/qcom,spss.txt @@ -9,6 +9,7 @@ on the QTI Secure Processor. Definition: must be one of: "qcom,waipio-spss-pas" "qcom,kalama-spss-pas" + "qcom,kona-spss-pas" - reg: Usage: required diff --git a/bindings/remoteproc/subsystem_notif_virt.txt b/bindings/remoteproc/subsystem_notif_virt.txt new file mode 100755 index 00000000..0fd0983b --- /dev/null +++ b/bindings/remoteproc/subsystem_notif_virt.txt @@ -0,0 +1,49 @@ +Subsystem Notification Virtual Driver + +The guest VM uses this driver to communicate +subsystem state notifications to a backend driver +via the virtual device's registers. + +[Root level node] +Required Properties: +-compatible : Should be "qcom,subsys-notif-virt" +-reg : The start and size of the virtual device's + register set. +-reg-names : Should be "vdev_base" for virtual device's + base address. + +[Child nodes] +-subsys-names : The name of the subsystem that the + driver is registering to notifications for. +-offset : The offset from the virtual device's register + base where the subsystem state will be written. +-type : The type of the subsystem. + "virtual" - When the subsystem is loaded by the host VM. + "native" - When the subsystem is loaded by the guest VM. + +Required Property for "virtual" subsystem types: +-interrupts : Tuple defining the interrupt which the driver must + register for to receive subsystem state notifications + from the backend. +-interrupt-names: Must be "state-irq" + +Example: + + subsys_notif_virt: qcom,subsys_notif_virt@2D000000 { + compatible = "qcom,subsys-notif-virt"; + reg = <0x2D000000 0x400>; + reg-names = "vdev_base"; + adsp { + subsys-name = "adsp"; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "state-irq"; + type = "virtual"; + offset = <0>; + }; + modem { + subsys-name = "modem"; + type = "native"; + offset = <256>; + }; + }; + diff --git a/bindings/serial/qcom,msm-geni-uart.txt b/bindings/serial/qcom,msm-geni-uart.txt index 5975753a..0e1d3a25 100755 --- a/bindings/serial/qcom,msm-geni-uart.txt +++ b/bindings/serial/qcom,msm-geni-uart.txt @@ -21,6 +21,9 @@ Optional properties: - qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr. - qcom,change-sampling-rate: This is a boolean parameter and use this to decide the samping rate at which sequencer engine runs. +- qcom,compat-ioctl-support: This is a boolean parameter and use this to register + compat ioctl ops for ldisc tty pointer. This compat ioctl is required when we + have 32-bit user-space application running on 64-bit kernel. Example: qupv3_uart11: qcom,qup_uart@0xa88000 { diff --git a/bindings/soc/qcom/hab.txt b/bindings/soc/qcom/hab.txt index 32f79e7f..f91ff6f0 100755 --- a/bindings/soc/qcom/hab.txt +++ b/bindings/soc/qcom/hab.txt @@ -21,6 +21,8 @@ Required properties: - remote-vmids: When the local role is "fe", this is to tell which VM is the relevant BE. When it is "be", this is to tell which VMs it will support as BE. + - kernel_only: If the current mmid group can only be accessed by kernel hab + clients, please add this property. Example: qcom,hab { @@ -37,5 +39,6 @@ Example: grp-start-id = <200>; role = "fe"; remote-vmids = <0>; + kernel_only; }; } diff --git a/bindings/soc/qcom/qcom,aoss-qmp.txt b/bindings/soc/qcom/qcom,aoss-qmp.txt index 7782e1c8..4f24b2eb 100755 --- a/bindings/soc/qcom/qcom,aoss-qmp.txt +++ b/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -27,6 +27,7 @@ power-domains. "qcom,cinder-aoss-qmp" "qcom,sdxpinn-aoss-qmp" "qcom,sdxbaagha-aoss-qmp" + "qcom,kona-aoss-qmp" - reg: Usage: required diff --git a/bindings/soc/qcom/qcom,power-state.txt b/bindings/soc/qcom/qcom,power-state.txt index e0900417..2cb20e58 100755 --- a/bindings/soc/qcom/qcom,power-state.txt +++ b/bindings/soc/qcom/qcom,power-state.txt @@ -11,10 +11,19 @@ Required Properties: Usage: required Value type: <string> Definition: must be "qcom,power-state" +- subsys-name: + Usage: required + Value type: <string> + Description: subsystem names supported +- rproc-handle: + Usage: required + Description: phandle to subsys defined in subsys-name. Example: qcom,power-state { compatible = "qcom,power-state"; + qcom,subsys-name = "adsp", "modem"; + qcom,rproc-handle = <&adsp_pas>, <&modem_pas>; }; diff --git a/bindings/soc/qcom/qcom,slatecom_interface.txt b/bindings/soc/qcom/qcom,slatecom_interface.txt index 2731a795..4525afb9 100755 --- a/bindings/soc/qcom/qcom,slatecom_interface.txt +++ b/bindings/soc/qcom/qcom,slatecom_interface.txt @@ -8,9 +8,11 @@ memory in the device. Required properties: - compatible: Must be "qcom,slate-daemon" +- qcom,platform-reset-gpio: This gpio state used to make boot decision for slate subsystem. Example: qcom,slate-daemon { compatible = "qcom,slate-daemon"; + qcom,platform-reset-gpio = <&pm5100_gpios 15 0>; }; diff --git a/bindings/soc/qcom/qti-pmic-lpm.yaml b/bindings/soc/qcom/qti-pmic-lpm.yaml new file mode 100755 index 00000000..c60aa714 --- /dev/null +++ b/bindings/soc/qcom/qti-pmic-lpm.yaml @@ -0,0 +1,45 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/soc/qcom/qti-pmic-lpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PMIC low power mode (PMIC LPM) binding + +description: | + Qualcomm Technologies, Inc. PMIC low power mode (PMIC LPM) reports entry and + exit of PMIC's low power modes DeepSleep/Hibernate/TWM to a companion chip + through the SDAM interface. + +properties: + compatible: + const: qti,pmic-lpm + + reg: + description: Base address of the SDAM peripheral. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm5100@0 { + #address-cells = <1>; + #size-cells = <0>; + + pmic-lpm@7200 { + compatible = "qti,pmic-lpm"; + reg = <0x7200>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + }; +... diff --git a/bindings/sound/ti,tas5805m.txt b/bindings/sound/ti,tas5805m.txt new file mode 100755 index 00000000..782aec44 --- /dev/null +++ b/bindings/sound/ti,tas5805m.txt @@ -0,0 +1,34 @@ +Texas Instruments TAS5805M audio amplifier + +The TAS5805M serial control bus communicates through I2C protocols. + +Required properties: + - compatible: "ti,tas5805m". + - reg: 7-bit I2C address. + - gpio,pdn: A GPIO spec to define which pin is connected to the + chip's active-low power down pin. + +Optional properties: + - gpio,hpd: GPIO used to detect external interrupt event. If specified, + the driver will mute tas5805m if this GPIO is high. + Unmute if this GPIO is low. + + +Example: + +tas5805m@2d { + compatible = "ti,tas5805m"; + reg = <0x2d>; + gpio,pdn = <&tlmm 127 0>; + + interrupt-parent = <&tlmm>; + interrupts = <32 0>; + gpio,hpd = <&tlmm 32 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_sleep &line_out_hpd_default>; +}; + + +For more product information please see the link below: +https://www.ti.com/product/TAS5805M diff --git a/bindings/spmi/qcom,spmi-pmic-arb.txt b/bindings/spmi/qcom,spmi-pmic-arb.txt index 17272330..8b9b40ab 100755 --- a/bindings/spmi/qcom,spmi-pmic-arb.txt +++ b/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -47,6 +47,8 @@ Optional properties: applicable to PMIC arbiter version 7 and beyond. Support values: 0 = primary bus, 1 = secondary bus Assumed to be 0 if unspecified. +- qcom,mid : SPMI master ID of this controller. Supported values + are 0, 1, 2 and 3. Consumer node optional properties: - qcom,pmic-arb : phandle for an spmi-pmic-arb device. This can be used by @@ -67,6 +69,7 @@ Example: qcom,ee = <0>; qcom,channel = <0>; + qcom,mid = <0>; #address-cells = <2>; #size-cells = <0>; diff --git a/bindings/thermal/qti-virtual-sensor.txt b/bindings/thermal/qti-virtual-sensor.txt index 57b4803a..29e083de 100755 --- a/bindings/thermal/qti-virtual-sensor.txt +++ b/bindings/thermal/qti-virtual-sensor.txt @@ -12,7 +12,7 @@ Properties: Definition: must be "qcom,vs-sensor" Virtual sensor driver properties: -- qcom,sensors: +- sensor-names: Usage: required Value type: <List of Thermal Zones> Definition: List of thermal zones whom maximum or minimum temperature need to find out. @@ -23,25 +23,25 @@ Properties: Definition: It can be 1 or 0. 1 is identifier for maximum temperature and 0 is identifier for minimum temperature. -- qcom,sensor_id: - Usage: optional - value type: <integer> - Definition: It will be 0,1,2.. depending upon how many thermal sensors are present in the target. - Example: virtual_sensor: virtual-sensor { compatible = "qcom,vs-sensor"; #thermal-sensor-cells = <1>; cpu_max: cpu-max{ - qcom,sensors = <&cpuss_0 &cpuss_1 &cpuss_2 &cpuss_3>; + sensor-names = "cpuss-0", + "cpuss-1", + "cpuss-2", + "cpuss-3"; qcom,logic = <1>; - qcom,sensor_id = <0>; }; modem_max: modem-max{ - qcom,sensors = <&modem_offline &modem_q6 & modem_offline_fec &modem_offline_phy_0 &modem_offline_phy_1>; + sensor-names = "modem_offline", + "modem_q6", + "modem_offline_fec", + "modem_offline_phy-0", + "modem_offline_phy-1"; qcom,logic = <1>; - qcom,sensor_id = <1>; }; }; diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index f186a428..c546aaea 100755 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -14,6 +14,8 @@ Required properties: present on MSM8996 chipset. "qcom,ufs-phy-qmp-v4-lahaina" for ufs phy present on SM8350 chipset. + "qcom,ufs-phy-qmp-v4-direwolf" for ufs phy + present on SA8295 Makena chipset. "qcom,ufs-phy-qrbtc-sdm845" for phy support for sdm845 emulation. "qcom,ufs-phy-qmp-v3" for V3 ufs phy @@ -24,6 +26,8 @@ Required properties: present on Kalama chipsets. "qcom,ufs-phy-qmp-v4-khaje" for ufs phy present on khaje chipsets. + "qcom,ufs-phy-qmp-v4-kona" for ufs phy + present on kona chipsets. - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. Required "reg-names" is "phy_mem". diff --git a/bindings/usb/msm-ssusb.txt b/bindings/usb/msm-ssusb.txt index 9c7b9366..6e13eb32 100755 --- a/bindings/usb/msm-ssusb.txt +++ b/bindings/usb/msm-ssusb.txt @@ -101,6 +101,9 @@ Optional properties : speed using "maximum-speed=super-speed" works only for device mode because we set speed to DWC3_DCFG_SUPERSPEED in DCFG register. It does not change anything for host mode and connected peripherals might still get enumerated in SSP. +- qcom,msm-probe-core-init: If present, call dwc3_ext_event_notify() at the end of dwc3_msm_probe, + which will populate the dwc3 child node and initialize the dwc3 controller during bootup. + Otherwise core_init will be done after getting USB role from ADSP. Sub nodes: - Sub node for "DWC3- USB3 controller". |