diff options
Diffstat (limited to 'qcom/direwolf-usb.dtsi')
| -rwxr-xr-x | qcom/direwolf-usb.dtsi | 668 |
1 files changed, 659 insertions, 9 deletions
diff --git a/qcom/direwolf-usb.dtsi b/qcom/direwolf-usb.dtsi index 05673bf5..aaba8cdf 100755 --- a/qcom/direwolf-usb.dtsi +++ b/qcom/direwolf-usb.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h> +#include <dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h> + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -43,6 +46,7 @@ qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,ignore-wakeup-src-in-hostmode; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -52,17 +56,18 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy0>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; tx-fifo-resize; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; }; @@ -89,6 +94,194 @@ 0x17 0x74>; /* override x2 */ }; + /* Primary USB port related USB4-USB3-DP PHY */ + usb_qmp_dp_phy0: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88eb000 0x4000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB4_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_PCS_PCS_STATUS1 + USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_PCS_POWER_DOWN_CONTROL + USB3_PCS_SW_RESET + USB3_PCS_START_CONTROL + 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ + USB43DP_COM_POWER_DOWN_CTRL + USB43DP_COM_SW_RESET + USB43DP_COM_RESET_OVRD_CTRL1 + USB43DP_COM_PHY_MODE_CTRL + USB43DP_COM_TYPEC_CTRL + USB3_PCS_CLAMP_ENABLE + USB43DP_COM_TYPEC_STATUS>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_QSERDES_PLL_SSC_EN_CENTER 0x01 0 + USB3_QSERDES_PLL_SSC_PER1 0x31 0 + USB3_QSERDES_PLL_SSC_PER2 0x01 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D 0 + USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02 0 + USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36 0 + USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A 0 + USB3_QSERDES_PLL_LOCK_CMP_EN 0x04 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82 0 + USB3_QSERDES_PLL_DEC_START_MODE0 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01 0 + USB3_QSERDES_PLL_DEC_START_MODE1 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05 0 + USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00 0 + USB3_QSERDES_PLL_HSCLK_SEL 0x13 0 + USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04 0 + USB3_QSERDES_PLL_CORE_CLK_EN 0x60 0 + USB3_QSERDES_PLL_CMN_CONFIG 0x76 0 + USB3_QSERDES_PLL_PLL_IVCO 0xFF 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20 0 + USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01 0 + USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A 0 + USB43DP_QSERDES_TXA_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXA_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXA_DFE_3 0x45 0 + USB43DP_QSERDES_RXA_GM_CAL 0x09 0 + USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB43DP_QSERDES_TXB_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXB_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXB_DFE_3 0x45 0 + USB43DP_QSERDES_RXB_GM_CAL 0x09 0 + USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_PCS_REFGEN_REQ_CONFIG1 0x21 0 + USB3_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_PCS_RX_CONFIG 0x0A 0 + USB3_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_PCS_EQ_CONFIG1 0x4B 0 + USB3_PCS_EQ_CONFIG5 0x10 0 + USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + 0xffffffff 0xffffffff 0x00>; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; @@ -137,6 +330,7 @@ qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,ignore-wakeup-src-in-hostmode; qcom,default-mode-host; interconnect-names = "usb-ddr", "ddr-usb"; @@ -147,17 +341,18 @@ compatible = "snps,dwc3"; reg = <0xa800000 0xd93c>; interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + usb-phy = <&usb2_phy1>, <&usb_qmp_dp_phy1>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; tx-fifo-resize; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; }; @@ -184,6 +379,194 @@ 0x17 0x74>; /* override x2 */ }; + /* Secondary USB port related USB4-USB3-DP PHY */ + usb_qmp_dp_phy1: ssphy@8903000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x8903000 0x4000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L1C0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4C0>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, + <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_PCS_PCS_STATUS1 + USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_PCS_POWER_DOWN_CONTROL + USB3_PCS_SW_RESET + USB3_PCS_START_CONTROL + 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ + USB43DP_COM_POWER_DOWN_CTRL + USB43DP_COM_SW_RESET + USB43DP_COM_RESET_OVRD_CTRL1 + USB43DP_COM_PHY_MODE_CTRL + USB43DP_COM_TYPEC_CTRL + USB3_PCS_CLAMP_ENABLE + USB43DP_COM_TYPEC_STATUS>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_QSERDES_PLL_SSC_EN_CENTER 0x01 0 + USB3_QSERDES_PLL_SSC_PER1 0x31 0 + USB3_QSERDES_PLL_SSC_PER2 0x01 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D 0 + USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02 0 + USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36 0 + USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A 0 + USB3_QSERDES_PLL_LOCK_CMP_EN 0x04 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82 0 + USB3_QSERDES_PLL_DEC_START_MODE0 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01 0 + USB3_QSERDES_PLL_DEC_START_MODE1 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05 0 + USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00 0 + USB3_QSERDES_PLL_HSCLK_SEL 0x13 0 + USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04 0 + USB3_QSERDES_PLL_CORE_CLK_EN 0x60 0 + USB3_QSERDES_PLL_CMN_CONFIG 0x76 0 + USB3_QSERDES_PLL_PLL_IVCO 0xFF 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20 0 + USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01 0 + USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A 0 + USB43DP_QSERDES_TXA_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXA_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXA_DFE_3 0x45 0 + USB43DP_QSERDES_RXA_GM_CAL 0x09 0 + USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB43DP_QSERDES_TXB_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXB_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXB_DFE_3 0x45 0 + USB43DP_QSERDES_RXB_GM_CAL 0x09 0 + USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_PCS_REFGEN_REQ_CONFIG1 0x21 0 + USB3_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_PCS_RX_CONFIG 0x0A 0 + USB3_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_PCS_EQ_CONFIG1 0x4B 0 + USB3_PCS_EQ_CONFIG5 0x10 0 + USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port related controller */ usb2: ssusb@a400000 { compatible = "qcom,dwc-usb3-msm"; @@ -235,6 +618,7 @@ reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; + qcom,ignore-wakeup-src-in-hostmode; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_MP &mc_virt SLAVE_EBI1>, @@ -244,8 +628,8 @@ compatible = "snps,dwc3"; reg = <0xa400000 0xd93c>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy2>, <&usb_nop_phy>, - <&usb2_phy3>, <&usb_nop_phy>, + usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, + <&usb2_phy3>, <&usb_qmp_phy1>, <&usb2_phy4>, <&usb_nop_phy>, <&usb2_phy5>, <&usb_nop_phy>; linux,sysdev_is_parent; @@ -254,10 +638,8 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; snps,dis_u3_susphy_quirk; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "host"; }; }; @@ -284,6 +666,140 @@ 0x17 0x74>; /* override x2 */ }; + /* Tertiary USB port 0 related QMP PHY */ + usb_qmp_phy0: ssphy@88ef000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ef000 0x2000>, + <0x088ef28c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK_SRC>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_UNI_PCS_PCS_STATUS1 + USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_UNI_PCS_POWER_DOWN_CONTROL + USB3_UNI_PCS_SW_RESET + USB3_UNI_PCS_START_CONTROL>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 + USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 + USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 + USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 + USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0 + USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 + USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 + USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 + USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0 + USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 + USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 + USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 + USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 + USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x00 0 + USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0 + USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 + USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 + USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_UNI_PCS_EQ_CONFIG1 0x4B 0 + USB3_UNI_PCS_EQ_CONFIG5 0x10 0 + USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port 1 related High Speed PHY */ usb2_phy3: hsphy@88e8000 { compatible = "qcom,usb-hsphy-snps-femto"; @@ -306,6 +822,140 @@ 0x17 0x74>; /* override x2 */ }; + /* Tertiary USB port 1 related QMP PHY */ + usb_qmp_phy1: ssphy@88f1000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88f1000 0x2000>, + <0x088f128c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK_SRC>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_UNI_PCS_PCS_STATUS1 + USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_UNI_PCS_POWER_DOWN_CONTROL + USB3_UNI_PCS_SW_RESET + USB3_UNI_PCS_START_CONTROL>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 + USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 + USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 + USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 + USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0 + USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 + USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 + USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 + USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0 + USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 + USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 + USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 + USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 + USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x00 0 + USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0 + USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 + USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 + USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_UNI_PCS_EQ_CONFIG1 0x4B 0 + USB3_UNI_PCS_EQ_CONFIG5 0x10 0 + USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port 2 related High Speed PHY */ usb2_phy4: hsphy@88e9000 { compatible = "qcom,usb-hsphy-snps-femto"; |