diff options
Diffstat (limited to 'qcom/msm-arm-smmu-8917.dtsi')
| -rw-r--r-- | qcom/msm-arm-smmu-8917.dtsi | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/qcom/msm-arm-smmu-8917.dtsi b/qcom/msm-arm-smmu-8917.dtsi new file mode 100644 index 00000000..adea3a4d --- /dev/null +++ b/qcom/msm-arm-smmu-8917.dtsi @@ -0,0 +1,81 @@ +&soc { + gfx_iommu: qcom,iommu@1f00000 { + status = "ok"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1f00000 0x10000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <1>; + qcom,tz-device-id = "GPU"; + qcom,skip-init; + qcom,enable-static-cb; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,regulator-names = "vdd"; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; + + apps_iommu: qcom,iommu@1e00000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1e00000 0x40000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,tz-device-id = "APPS"; + qcom,skip-init; + qcom,disable-atos; + ranges; + qcom,enable-static-cb; + qcom,use-3-lvl-tables; + qcom,regulator-names = "vdd"; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; +}; |