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-rwxr-xr-xqcom/sa410m.dtsi293
1 files changed, 262 insertions, 31 deletions
diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi
index f8212a93..d30a4d7a 100755
--- a/qcom/sa410m.dtsi
+++ b/qcom/sa410m.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,scuba.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
#address-cells = <2>;
@@ -24,7 +25,10 @@
granule = <512>;
};
- aliases {};
+ aliases {
+ serial0 = &qupv3_se4_2uart;
+ sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
+ };
firmware: firmware {};
@@ -389,6 +393,11 @@
#address-cells = <1>;
#size-cells = <1>;
+ download_mode@0 {
+ compatible = "qcom,msm-imem-download_mode";
+ reg = <0x0 0x8>;
+ };
+
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
@@ -423,6 +432,16 @@
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
+
+ emergency_download_mode@fe0 {
+ compatible = "qcom,msm-imem-emergency_download_mode";
+ reg = <0xfe0 0xc>;
+ };
+
+ ss_mdump@b88 {
+ compatible = "qcom,msm-imem-minidump";
+ reg = <0xb88 0x1c>;
+ };
};
dload_mode {
@@ -468,6 +487,22 @@
0x0f1a80b8 0x0f1b80b8>;
};
+ qfprom: qfprom@1b40000 {
+ compatible = "qcom,qfprom";
+ reg = <0x1b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+ status = "okay";
+
+ adsp_variant: adsp_variant@6011 {
+ reg = <0x6011 0x1>;
+ bits = <3 1>;
+ };
+
+ };
+
eud: qcom,msm-eud@1610000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
@@ -480,8 +515,8 @@
qcom,secure-eud-en;
qcom,eud-tcsr-check-enable;
qcom,eud-clock-vote-req;
- //clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
- //clock-names = "eud_ahb2phy_clk";
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "eud_ahb2phy_clk";
status = "disabled";
};
@@ -697,6 +732,27 @@
status = "ok";
};
+ spmi_bus: qcom,spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x1c40000 0x1100>,
+ <0x1e00000 0x2000000>,
+ <0x3e00000 0x100000>,
+ <0x3f00000 0xa0000>,
+ <0x1c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ thermal_zones: thermal-zones { };
+
clk_virt: interconnect@0 {
compatible = "qcom,scuba-clk_virt";
qcom,keepalive;
@@ -707,7 +763,7 @@
};
system_noc: interconnect0@1880000 {
- reg = <0x1880000 0x60200>;
+ reg = <0x01880000 0x5e080>;
compatible = "qcom,scuba-sys_noc";
qcom,keepalive;
#interconnect-cells = <1>;
@@ -761,21 +817,21 @@
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
- //interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
};
qcom,lpass@ab00000 {
compatible = "qcom,pil-tz-generic";
reg = <0xab00000 0x00100>;
- //clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
- //clock-names = "xo";
- //qcom,proxy-clock-names = "xo";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
- //vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
- //qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
- //vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
- //qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
qcom,firmware-name = "adsp";
@@ -790,11 +846,11 @@
qcom,minidump-as-elf32;
/* Inputs from lpass */
- //interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
- // <&adsp_smp2p_in 0 0>,
- // <&adsp_smp2p_in 2 0>,
- // <&adsp_smp2p_in 1 0>,
- // <&adsp_smp2p_in 3 0>;
+ interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
@@ -803,7 +859,7 @@
"qcom,stop-ack";
/* Outputs to lpass */
- //qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
status = "ok";
};
@@ -812,12 +868,12 @@
compatible = "qcom,pil-tz-generic";
reg = <0x6080000 0x100>;
- //clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
- //clock-names = "xo";
- //qcom,proxy-clock-names = "xo";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
- //vdd_cx-supply = <&VDD_CX_LEVEL>;
- //qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx";
qcom,firmware-name = "modem";
@@ -833,12 +889,12 @@
qcom,sequential-fw-load;
/* Inputs from mss */
- //interrupts-extended = <&intc 0 307 1>,
- // <&modem_smp2p_in 0 0>,
- // <&modem_smp2p_in 2 0>,
- // <&modem_smp2p_in 1 0>,
- // <&modem_smp2p_in 3 0>,
- // <&modem_smp2p_in 7 0>;
+ interrupts-extended = <&intc 0 307 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
@@ -848,7 +904,7 @@
"qcom,shutdown-ack";
/* Outputs to mss */
- //qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
status = "ok";
};
@@ -870,7 +926,7 @@
smem: qcom,smem {
compatible = "qcom,smem";
- //memory-region = <&smem_mem>;
+ memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 3>;
};
@@ -886,6 +942,61 @@
reg = <0x45f0000 0x7000>;
};
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,rpc-latency-us = <611>;
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable";
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C4 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable";
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C5 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable";
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C6 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable";
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C7 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable";
+ };
+
+ };
+
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
@@ -1104,14 +1215,134 @@
};
};
+ sdhc_1: sdhci@4744000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
+ reg-names = "hc_mem", "cqhci_mem";
+
+ iommus = <&apps_smmu 0xC0 0x0>;
+ qcom,iommu-dma = "bypass";
+
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "core", "iface", "ice_core";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
+ <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <0 0>, <0 0>,
+ /* 400 KB/s*/
+ <1046 1600>,<1600 1600>,
+ /* 25 MB/s */
+ <25600 250000>,<50000 133320>,
+ /* 50 MB/s */
+ <51200 250000>,<65000 133320>,
+ /* 100 MB/s */
+ <102400 250000>,<65000 133320>,
+ /* 200 MB/s */
+ <204800 800000>,<200000 300000>,
+ /* 400 MB/s */
+ <204800 800000>,<200000 300000>,
+ /* Max. bandwidth */
+ <1338562 4096000>,<1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
+
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ bus-width = <8>;
+ non-removable;
+ supports-cqe;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+ reset-names = "core_reset";
+
+ status = "disabled";
+
+ qos0 {
+ mask = <0x0f>;
+ vote = <43>;
+ };
+
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x280000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,vm-nav-path;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ memory-region = <&memshare_mem>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+
+ qcom-secure-buffer {
+ compatible = "qcom,secure-buffer";
+ };
+
};
+#include "sa410m-pmic.dtsi"
#include "sa410m-pinctrl.dtsi"
#include "pm2250-rpm-regulator.dtsi"
#include "scuba-regulator.dtsi"
#include "scuba-ion.dtsi"
#include "msm-arm-smmu-scuba.dtsi"
#include "sa410m-gdsc.dtsi"
+#include "sa410m-qupv3.dtsi"
+#include "sa410m-usb.dtsi"
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
&gcc_camss_top_gdsc {
status = "ok";
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 20:49:51 +0000