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-rwxr-xr-xqcom/sdmshrike.dtsi26
1 files changed, 25 insertions, 1 deletions
diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index 3180dd22..0d7ccca1 100755
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -1080,6 +1080,12 @@
#power-domain-cells = <1>;
};
+ aop-set-ddr-freq {
+ compatible = "qcom,aop-set-ddr-freq";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+ };
+
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
qcom,qmp = <&aoss_qmp>;
@@ -1630,6 +1636,23 @@
};
};
+ ufs_ice: ufsice@1d90000 {
+ compatible = "qcom,ice";
+ reg = <0x1d90000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ufs_core_clk",
+ "iface_clk", "ice_core_clk";
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ qcom,op-freq-hz = <0>, <0>, <300000000>;
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "ufs";
+ qcom,num-fde-slots = <31>;
+ };
+
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>; /* PHY regs */
reg-names = "phy_mem";
@@ -1759,7 +1782,7 @@
reset-names = "rst";
iommus = <&apps_smmu 0x300 0x0>;
- qcom,iommu-dma = "bypass";
+ qcom,iommu-dma = "fastmap";
dma-coherent;
status = "disabled";
@@ -2028,6 +2051,7 @@
#include "msm-arm-smmu-sdmshrike.dtsi"
#include "sdmshrike-debug.dtsi"
#include "sa8195-usb.dtsi"
+#include "sm8150-npu.dtsi"
&slpi_tlmm {
status = "ok";