summaryrefslogtreecommitdiff
path: root/qcom/trinket.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'qcom/trinket.dtsi')
-rwxr-xr-xqcom/trinket.dtsi844
1 files changed, 844 insertions, 0 deletions
diff --git a/qcom/trinket.dtsi b/qcom/trinket.dtsi
new file mode 100755
index 00000000..6b8e12f1
--- /dev/null
+++ b/qcom/trinket.dtsi
@@ -0,0 +1,844 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. Trinket";
+ compatible = "qcom,trinket";
+ qcom,msm-id = <467 0x10000>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x80000000>,
+ <0x1 0xc0000000 0x0 0xc0000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-size = <0x80000>;
+ cache-level = <2>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ d-cache-size = <0x8000>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ d-cache-size = <0x8000>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ d-cache-size = <0x10000>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-size = <0x100000>;
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ d-cache-size = <0x10000>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ d-cache-size = <0x10000>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ d-cache-size = <0x10000>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ idle-states { };
+
+ soc: soc { };
+
+ firmware: firmware {
+ scm {
+ compatible = "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* HYP 6MB */
+ hyp_region: hyp_region@45700000 {
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ /* XBL(BOOT) 1 MB + AOP (256KB) */
+ xbl_aop_mem: xbl_aop_mem@45e00000 {
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x140000>;
+ };
+
+ /* Secdata / APSS (4 KB) */
+ sec_apps_mem: sec_apps_region@45fff000 {
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ /* SMEM (2 MB) */
+ smem_region: smem@46000000 {
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ /* TZ_STAT (1 MB) + TAGS (8 MB) + TZ (2 MB) + TZ Apps (14 MB) +
+ * Stargate (TZ Apps) (20 MB)
+ */
+ removed_region: removed_region@46200000 {
+ no-map;
+ reg = <0x0 0x46200000 0x0 0x2d00000>;
+ };
+
+ /* MPSS_WLAN (126 MB) */
+ pil_modem_mem: modem_region@4b000000 {
+ no-map;
+ reg = <0x0 0x4b000000 0x0 0x7e00000>;
+ };
+
+ /* VIDEO (5 MB) */
+ pil_video_mem: pil_video_region@52e00000 {
+ no-map;
+ reg = <0x0 0x52e00000 0x0 0x500000>;
+ };
+
+ /* WLAN (2 MB) */
+ wlan_msa_mem: wlan_msa_region@53300000 {
+ no-map;
+ reg = <0x0 0x53300000 0x0 0x200000>;
+ };
+
+ /* cDSP (30 MB) */
+ pil_cdsp_mem: cdsp_regions@53500000 {
+ no-map;
+ reg = <0x0 0x53500000 0x0 0x1e00000>;
+ };
+
+ /* ADSP (30 MB) */
+ pil_adsp_mem: pil_adsp_region@55300000 {
+ no-map;
+ reg = <0x0 0x55300000 0x0 0x1e00000>;
+ };
+
+ /* IPA FW (64 KB) */
+ pil_ipa_fw_mem: ips_fw_region@57100000 {
+ no-map;
+ reg = <0x0 0x57100000 0x0 0x10000>;
+ };
+
+ /* IPA GSI (20 KB) */
+ pil_ipa_gsi_mem: ipa_gsi_region@57110000 {
+ no-map;
+ reg = <0x0 0x57110000 0x0 0x5000>;
+ };
+
+ /* GPU micro code (8 KB) */
+ pil_gpu_mem: gpu_region@57115000 {
+ no-map;
+ reg = <0x0 0x57115000 0x0 0x2000>;
+ };
+
+ /* UEFI/secure_dsp_mem (8 MB) + Secure DSP Heap (22 MB) */
+ cdsp_sec_mem: cdsp_sec_regions@5f800000 {
+ no-map;
+ reg = <0x0 0x5f800000 0x0 0x1e00000>;
+ };
+
+ /* QSEECOM (20 MB) */
+ qseecom_mem: qseecom_region@5e400000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0x0 0x5e400000 0x0 0x1400000>;
+ };
+
+ /* user_config (16 MB) */
+ user_contig_mem: user_contig_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ /* qseccom_ta_mem (16 MB) */
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ /* secure_display_memory (140 MB) */
+ secure_display_memory: secure_display_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x8c00000>;
+ };
+
+ /* adsp_memory (8 MB) */
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x800000>;
+ };
+
+ /* sdsp_mem (4 MB) */
+ sdsp_mem: sdsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ /* dump_mem (4 MB) */
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0x0 0x400000>;
+ };
+
+ /* cont_splash_memory (15 MB) */
+ cont_splash_memory: cont_splash_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "cont_splash_region";
+ };
+
+ /* dfps_data_memory (1 MB) */
+ dfps_data_memory: dfps_data_region@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ /* disp_rdump_memory (15 MB) */
+ disp_rdump_memory: disp_rdump_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "disp_rdump_region";
+ };
+
+ /* global autoconfigured region for contiguous allocations (32 MB) */
+ system_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ #gpio-cells = <2>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0xf200000 0x10000>, /* GICD */
+ <0xf300000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wdog: qcom,wdt@f017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 3 0>, <0 4 0>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ arch_timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ memtimer: timer@f120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0f120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0f121000 0x1000>,
+ <0x0f122000 0x1000>;
+ };
+
+ frame@f123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ vendor_hooks: qcom,cpu-vendor-hooks {
+ compatible = "qcom,cpu-vendor-hooks";
+ };
+
+ tcsr_mutex_block: syscon@00340000 {
+ compatible = "syscon";
+ reg = <0x340000 0x40000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@03c0000 {
+ compatible = "syscon";
+ reg = <0x003C0000 0x40000>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ qcom-secure-buffer {
+ compatible = "qcom,secure-buffer";
+ };
+
+ restart@440b000 {
+ compatible = "qcom,pshold";
+ reg = <0x440b000 0x4>, <0x03d3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom,mpm2-sleep-counter@4403000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4403000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-imem@c125000 {
+ compatible = "qcom,msm-imem";
+ reg = <0xc125000 0x1000>;
+ ranges = <0x0 0xc125000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+
+ pil@6dc {
+ compatible = "qcom,msm-imem-pil-disable-timeout";
+ reg = <0x6dc 0x4>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c200_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c300_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c400_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c500_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c600_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c700_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ tmc_etf {
+ qcom,dump-size = <0x8000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etf_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache200 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache300 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache400 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache500 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache600 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache700 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache200 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache300 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache400 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache500 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache600 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache700 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l1_tlb0 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l1_tlb100 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l1_tlb200 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l1_tlb300 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l1_tlb400 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l1_tlb500 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l1_tlb600 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l1_tlb700 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x127>;
+ };
+ };
+
+ mini_dump_mode {
+ compatible = "qcom,minidump";
+ status = "ok";
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+};
+
+#include "trinket-pinctrl.dtsi"
+#include "trinket-dma-heaps.dtsi"