From 9d088612ca6124e196691ee06bb39d1b37331a5f Mon Sep 17 00:00:00 2001
From: Nirmal Abraham <c_nabrah@qti.qualcomm.com>
Date: Thu, 4 Mar 2021 06:03:37 +0530
Subject: ARM: dts: msm: update mdss byte/pxl clocks for SPF targets

Update the mdss byte/pxl clock entries in gcc_mdss and
mdss_dsi nodes for SDM429/439/msm8937.

Change-Id: Ic742657893f1fe574c2d3e16e21e4bbbe5729518
---
 qcom/msm8917-mdss.dtsi |  1 -
 qcom/msm8917.dtsi      |  2 +-
 qcom/msm8937-mdss.dtsi | 13 ++++++-------
 qcom/msm8937.dtsi      | 10 +++++-----
 qcom/sdm429.dtsi       | 10 ++++------
 qcom/sdm439.dtsi       | 25 ++++++++++++++++++-------
 6 files changed, 34 insertions(+), 27 deletions(-)

(limited to 'qcom')

diff --git a/qcom/msm8917-mdss.dtsi b/qcom/msm8917-mdss.dtsi
index 235c6534..0f2e80ed 100644
--- a/qcom/msm8917-mdss.dtsi
+++ b/qcom/msm8917-mdss.dtsi
@@ -1,5 +1,4 @@
 #include "msm8937-mdss.dtsi"
-#include <dt-bindings/clock/mdss-28nm-pll-clk.h>
 &mdss_dsi {
 	vdda-supply = <&pm8937_l2>;
 	vddio-supply = <&pm8937_l6>;
diff --git a/qcom/msm8917.dtsi b/qcom/msm8917.dtsi
index 35bb7c3e..8bc44170 100644
--- a/qcom/msm8917.dtsi
+++ b/qcom/msm8917.dtsi
@@ -1,6 +1,6 @@
 #include "skeleton64.dtsi"
 #include <dt-bindings/clock/qcom,gcc-sdm429w.h>
-#include <dt-bindings/clock/mdss-28nm-pll-clk.h>
+#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
 #include <dt-bindings/clock/qcom,cpu-sdm.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
diff --git a/qcom/msm8937-mdss.dtsi b/qcom/msm8937-mdss.dtsi
index 68341b9b..a56cc009 100644
--- a/qcom/msm8937-mdss.dtsi
+++ b/qcom/msm8937-mdss.dtsi
@@ -232,13 +232,12 @@
 
 		clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,
 			<&gcc GCC_MDSS_AHB_CLK>,
-			<&gcc GCC_MDSS_AXI_CLK>;
-			/* TODO
-			 * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
-			 * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>,
-			 * <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
-			 * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>;
-			 */
+			<&gcc GCC_MDSS_AXI_CLK>,
+			<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+			<&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
+			<&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+			<&mdss_dsi1_pll PCLK_SRC_1_CLK>;
+
 		clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
 			"ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",
 			"ext_pixel1_clk";
diff --git a/qcom/msm8937.dtsi b/qcom/msm8937.dtsi
index 6658aad5..1a56a901 100644
--- a/qcom/msm8937.dtsi
+++ b/qcom/msm8937.dtsi
@@ -4,7 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-sdm429w.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
-#include <dt-bindings/clock/mdss-28nm-pll-clk.h>
+#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
 
 #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
 #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
@@ -599,10 +599,10 @@
 	gcc_mdss: qcom,gcc-mdss@1800000 {
 		compatible = "qcom,gcc-mdss-msm8937";
 		reg = <0x1800000 0x80000>;
-		 clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
-		 <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
-		 <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
-		 <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
+		 clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+		 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+		 <&mdss_dsi1_pll PCLK_SRC_1_CLK>,
+		 <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>;
 		clock-names = "pclk0_src", "byte0_src", "pclk1_src",
 			"byte1_src";
 		#clock-cells = <1>;
diff --git a/qcom/sdm429.dtsi b/qcom/sdm429.dtsi
index 6c42cd19..506cd0d1 100644
--- a/qcom/sdm429.dtsi
+++ b/qcom/sdm429.dtsi
@@ -219,12 +219,10 @@
 
 &gcc_mdss {
 	compatible = "qcom,gcc-mdss-sdm429";
-	/* TODO
-	 * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
-	 * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
-	 * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
-	 * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
-	 */
+	clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+		<&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+		<&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
+		<&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
 	clock-names = "pclk0_src", "byte0_src", "pclk1_src",
 		"byte1_src";
 	#clock-cells = <1>;
diff --git a/qcom/sdm439.dtsi b/qcom/sdm439.dtsi
index 758e4c3b..295eaae2 100644
--- a/qcom/sdm439.dtsi
+++ b/qcom/sdm439.dtsi
@@ -2,7 +2,7 @@
 #include "sdm439-pm8953.dtsi"
 #include "sdm439-pmi632.dtsi"
 #include "sdm439-audio.dtsi"
-
+#include <dt-bindings/clock/mdss-12nm-pll-clk.h>
 / {
 	model = "Qualcomm Technologies, Inc. SDM439";
 	compatible = "qcom,sdm439";
@@ -340,12 +340,10 @@
 
 &gcc_mdss {
 	compatible = "qcom,gcc-mdss-sdm439";
-	/* TODO
-	 * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
-	 * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
-	 * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
-	 * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
-	 */
+	clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+		<&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+		<&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
+		<&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
 	clock-names = "pclk0_src", "byte0_src", "pclk1_src",
 		"byte1_src";
 	#clock-cells = <1>;
@@ -380,6 +378,19 @@
 		0x1a96000 0x1a96000 0x300
 		0x1a96400 0x1a96400 0x400
 		0x193e000 0x193e000 0x30>;
+
+	clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,
+		<&gcc GCC_MDSS_AHB_CLK>,
+		<&gcc GCC_MDSS_AXI_CLK>,
+		<&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+		<&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>,
+		<&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+		<&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>;
+
+	clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
+		"ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",
+		"ext_pixel1_clk";
+
 };
 
 &mdss_dsi0 {
-- 
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