Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
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Required properties :
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
		"qcom,lahaina-gpucc",
		"qcom,shima-gpucc",
		"qcom,holi-gpucc".
		"qcom,waipio-gpucc",
		"qcom,waipio-gpucc-v2",
		"qcom,diwali-gpucc",
		"qcom,kalama-gpucc"
		"qcom,sm8150-gpucc",
		"qcom,sm8250-gpucc",
		"qcom,sa8155-gpucc",
		"qcom,khaje-gpucc",
		"qcom,sc8180x-gpucc".
		"qcom,monaco-gpucc",
		"qcom,scuba-gpucc"
		"qcom,lemans-gpucc"
		"qcom,crow-gpucc"
		"qcom,monaco_auto-gpucc"

- reg: shall contain base register offset and size.
- reg-names: names of registers listed in the same order as in the reg property.
		Must contain "cc_base".
- vdd_mx-supply: The vdd_mx logic rail supply.
- #clock-cells : from common clock binding, shall contain 1
- #reset-cells : from common reset binding, shall contain 1

Optional properties :
- #power-domain-cells : from generic power domain binding, shall contain 1
- clocks : shall contain the XO clock
	   shall contain the gpll0 out main clock (msm8998)
- clock-names : shall be "xo"
		shall be "gpll0" (msm8998)

Example:
1.
	gpucc: clock-controller@5090000 {
		compatible = "qcom,sdm845-gpucc";
		reg = <0x5090000 0x9000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
	};
2.
	clock_gpucc: clock-controller@3d90000 {
		compatible = "qcom,lahaina-gpucc";
		reg = <0x3d90000 0x9000>;
		reg-names = "cc_base";
		vdd_mx-supply = <&VDD_MXA_LEVEL>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};