#include <dt-bindings/clock/qcom,gcc-cinder.h>
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>

&soc {
	usb0: ssusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0xa600000 0x100000>;
		reg-names = "core_base";

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;

		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
		clock-names = "core_clk", "iface_clk",
				"utmi_clk", "sleep_clk";

		resets = <&gcc GCC_USB30_PRIM_BCR>;
		reset-names = "core_reset";

		interrupts-extended = <&pdc 8 IRQ_TYPE_EDGE_RISING>,
					<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
					<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
					<&pdc 9 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
				"ss_phy_irq", "dm_hs_phy_irq";
		qcom,use-pdc-interrupts;
		qcom,core-clk-rate = <200000000>;
		qcom,core-clk-rate-disconnected = <133333333>;
		qcom,core-clk-rate-hs = <66666667>;
		qcom,pm-qos-latency = <2>;

		interconnect-names = "usb-ddr", "ddr-usb";
		interconnects = <&system_noc MASTER_USB3 &mc_virt SLAVE_EBI1>,
				<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3_0>;

		extcon = <&eud>;
		qcom,msm-probe-core-init;

		dwc3@a600000 {
			compatible = "snps,dwc3";
			reg = <0xa600000 0xd93c>;

			iommus = <&apps_smmu 0xc0 0x0>;
			qcom,iommu-dma = "atomic";
			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
			dma-coherent;

			usb-phy = <&usb2_phy0>, <&usb_qmp_phy>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x0>;
			snps,is-utmi-l1-suspend;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			tx-fifo-resize;
			usb-role-switch;
			dr_mode = "otg";
			maximum-speed = "super-speed-plus";
		};
	};

	/* USB port related High Speed PHY */
	usb2_phy0: hsphy@88e3000 {
		compatible = "qcom,usb-hsphy-snps-femto";
		reg = <0x88e3000 0x120>,
			<0x088e2000 0x4>;
		reg-names = "hsusb_phy_base",
			    "eud_enable_reg";

		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_USB2_CLKREF_EN>;
		clock-names = "ref_clk_src", "ref_clk";

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		reset-names = "phy_reset";
	};

	/* USB port related QMP USB UNI PHY */
	usb_qmp_phy: ssphy@88e5000 {
		compatible = "qcom,usb-ssphy-qmp-v2";
		reg = <0x88e5000 0x2000>,
			<0x88E528C 0x4>;
		reg-names = "qmp_phy_base",
			"pcs_clamp_enable_reg";

		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
			 <&rpmhcc RPMH_CXO_CLK>,
			 <&gcc GCC_USB2_CLKREF_EN>,
			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
				"pipe_clk_ext_src", "ref_clk_src",
				"ref_clk", "com_aux_clk";

		resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
				<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
		reset-names = "phy_reset", "phy_phy_reset";

		qcom,qmp-phy-init-seq =
				/* <reg_offset, value> */
				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
				USB3_UNI_QSERDES_RX_GM_CAL	0x00
				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
				USB3_UNI_PCS_EQ_CONFIG1	0x4B
				USB3_UNI_PCS_EQ_CONFIG5	0x10
				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;

		qcom,qmp-phy-reg-offset =
				<USB3_UNI_PCS_PCS_STATUS1
				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
				USB3_UNI_PCS_POWER_DOWN_CONTROL
				USB3_UNI_PCS_SW_RESET
				USB3_UNI_PCS_START_CONTROL>;
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};
};