#include <dt-bindings/clock/qcom,gcc-direwolf.h>
#include "quin-vm-common.dtsi"
/ {
	model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine";
	qcom,msm-name = "SA_DIREWOLF_IVI";
	qcom,msm-id = <460 0x10000>;

	aliases {
		ufshc2 = &ufshc2_mem;
		hsuart0 = &qupv3_se2_4uart;
		pci-domain0 = &pcie0; /* PCIe0 domain */
		pci-domain1 = &pcie1; /* PCIe1 domain */
		pci-domain2 = &pcie2; /* PCIe2 domain */
		pci-domain3 = &pcie3; /* PCIe3 domain */
		pci-domain4 = &pcie4; /* PCIe4 domain */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cluster_0_opp_table: opp-table0 {
			compatible = "operating-points-v2";
			opp-shared;

			opp-2592000000 {
				opp-hz = /bits/ 64 <2592000000>;
				opp-microvolt = <952000>;
			};
		};

		cluster_1_opp_table: opp-table1 {
			compatible = "operating-points-v2";
			opp-shared;

			opp-2246400000 {
				opp-hz = /bits/ 64 <2246400000>;
				opp-microvolt = <952000>;
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_0_opp_table>;
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_0_opp_table>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_0_opp_table>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_0_opp_table>;
		};

		CPU4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x4>;
			capacity-dmips-mhz = <943>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_1_opp_table>;
		};

		CPU5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x5>;
			capacity-dmips-mhz = <943>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_1_opp_table>;
		};

		CPU6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x6>;
			capacity-dmips-mhz = <943>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_1_opp_table>;
		};

		CPU7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x7>;
			capacity-dmips-mhz = <943>;
			dynamic-power-coefficient = <100>;
			operating-points-v2 = <&cluster_1_opp_table>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};
};

&firmware {
	scm {
		compatible = "qcom,scm";
	};
};

&soc {
	/* Rome 3.3V supply */
	vreg_wlan: vreg_wlan {
		compatible = "qcom,stub-regulator";
		regulator-name = "vreg_wlan";
	};

	/* PWR_CTR2_VDD_1P8 supply */
	vreg_conn_1p8: vreg_conn_1p8 {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_1p8";
		pinctrl-names = "default";
		pinctrl-0 = <&conn_power_1p8_active>;
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&tlmm 128 0>;
	};

	/* PWR_CTR1_VDD_PA supply */
	vreg_conn_pa: vreg_conn_pa {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_pa";
		pinctrl-names = "default";
		pinctrl-0 = <&conn_power_pa_active>;
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&tlmm 129 0>;
	};

	apps_smmu: apps-smmu@15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x100000>,
			<0x15182000 0x20>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,handoff-smrs = <0xffff 0x0>;
		qcom,multi-match-handoff-smr;
		#global-interrupts = <2>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		interrupts =	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
	};

	dma_dev@0x0 {
		compatible = "qcom,iommu-dma";
		memory-region = <&system_cma>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
		/*Boolean property to disable shmbridge*/
		qcom,disable-shmbridge-support;
	};

	qcom_qseecom: qseecom@c1800000 {
		compatible = "qcom,qseecom";
		reg = <0xc1800000 0x3900000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,commonlib-loaded-by-hostvm;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_rng_ee3: qrng@10d3000 {
		compatible = "qcom,msm-rng";
		reg = <0x10d3000 0x1000>;
		qcom,no-qrng-config;
		clocks = <&dummycc RPMH_HWKM_CLK>;
		clock-names = "km_clk_src";
		status = "disabled";
	};

	qcom_rng_ee4: qrng@10d4000 {
		compatible = "qcom,msm-rng";
		reg = <0x10d4000 0x1000>;
		qcom,no-qrng-config;
		clocks = <&dummycc RPMH_HWKM_CLK>;
		clock-names = "km_clk_src";
		status = "disabled";
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,pdc";
		reg = <0xb220000 0x30000>;
		qcom,pdc-ranges = <12 492 6>, <126 611 8>, <136 621 1>, <138 623 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,direwolf-pinctrl";
		reg = <0x0F000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	VDD_CX_LEVEL:
	S1A0_LEVEL: pm8540_a0_s1_level: regulator-pm8540_a0-s1-level {
		compatible = "qcom,stub-regulator";
		regulator-name = "pm8540_a0_s1_level";
		regulator-min-microvolt =
			<RPMH_REGULATOR_LEVEL_RETENTION>;
		regulator-max-microvolt =
			<RPMH_REGULATOR_LEVEL_MAX>;
	};

	pcie_2a_pipe_clk: pcie_2a_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "pcie_2a_pipe_clk";
		#clock-cells = <0>;
	};

	pcie_2b_pipe_clk: pcie_2b_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "pcie_2b_pipe_clk";
		#clock-cells = <0>;
	};

	pcie_3a_pipe_clk: pcie_3a_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "pcie_3a_pipe_clk";
		#clock-cells = <0>;
	};

	pcie_3b_pipe_clk: pcie_3b_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "pcie_3b_pipe_clk";
		#clock-cells = <0>;
	};

	pcie_4_pipe_clk: pcie_4_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "pcie_4_pipe_clk";
		#clock-cells = <0>;
	};

	usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <0>;
	};

	usb3_uni_phy_mp_gcc_usb30_pipe_0_clk: usb3_uni_phy_mp_gcc_usb30_pipe_0_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_0_clk";
		#clock-cells = <0>;
	};

	usb3_uni_phy_mp_gcc_usb30_pipe_1_clk: usb3_uni_phy_mp_gcc_usb30_pipe_1_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_1_clk";
		#clock-cells = <0>;
	};

	usb3_uni_phy_sec_gcc_usb30_pipe_clk: usb3_uni_phy_sec_gcc_usb30_pipe_clk {
		compatible = "fixed-clock";
		clock-frequency = <1000>;
		clock-output-names = "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
		#clock-cells = <0>;
	};

	rpmh_cxo_clk: rpmh_cxo_clk {
		compatible = "qcom,dummycc";
		clock-output-names = "bi_tcxo";
		#clock-cells = <0>;
	};

	/* PWR_CTR1_VDD_PA supply for wlan2 */
	vreg_conn_pa2: vreg_conn_pa2 {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_pa2";
		pinctrl-names = "default";
		pinctrl-0 = <&conn_power_pa_active2>;
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&tlmm 216 0>;
	};
};

&regulator {
	gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
		regulator-name = "gcc_usb30_prim_gdsc";
	};

	gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc {
		regulator-name = "gcc_usb30_sec_gdsc";
	};

	gcc_usb30_mp_gdsc: gcc_usb30_mp_gdsc {
		regulator-name = "gcc_usb30_mp_gdsc";
	};

	gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc {
		regulator-name = "gcc_pcie_2a_gdsc";
	};

	gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc {
		regulator-name = "gcc_pcie_2b_gdsc";
	};

	gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc {
		regulator-name = "gcc_pcie_3a_gdsc";
	};

	gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc {
		regulator-name = "gcc_pcie_3b_gdsc";
	};

	gcc_pcie_4_gdsc: gcc_pcie_4_gdsc {
		regulator-name = "gcc_pcie_4_gdsc";
	};

	L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 {
		regulator-name = "ldoa3";
		regulator-min-microvolt = <1140000>;
		regulator-max-microvolt = <1260000>;
	};

	S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 {
		regulator-name = "smpe4";
		regulator-min-microvolt = <320000>;
		regulator-max-microvolt = <2040000>;
	};

	L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 {
		regulator-name = "ldoa5";
		regulator-min-microvolt = <720000>;
		regulator-max-microvolt = <950000>;
	};

	L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 {
		regulator-name = "ldog6";
	};

	L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 {
		regulator-name = "ldoa7";
		regulator-min-microvolt = <1620000>;
		regulator-max-microvolt = <1980000>;
	};

	L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 {
		regulator-name = "ldoa11";
		regulator-min-microvolt = <830000>;
		regulator-max-microvolt = <920000>;
	};

	L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 {
		regulator-name = "ldoa13";
		regulator-min-microvolt = <2970000>;
		regulator-max-microvolt = <3544000>;
	};

	L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 {
		regulator-name = "ldoc1";
		regulator-min-microvolt = <720000>;
		regulator-max-microvolt = <950000>;
	};

	L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 {
		regulator-name = "ldoc7";
		regulator-min-microvolt = <1620000>;
		regulator-max-microvolt = <1980000>;
	};

	L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 {
		regulator-name = "ldoc2";
		regulator-min-microvolt = <2970000>;
		regulator-max-microvolt = <3544000>;
	};

	L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 {
		regulator-name = "ldoa15";
	};

	L7G0: pm8540_g0_l7: regulator-pm8540_g0-l7 {
		regulator-name = "ldog7";
		regulator-min-microvolt = <1620000>;
		regulator-max-microvolt = <1980000>;
	};

	L4C0: pm8540_c0_l4: regulator-pm8540_c0-l4 {
		regulator-name = "ldoc4";
		regulator-min-microvolt = <1140000>;
		regulator-max-microvolt = <1260000>;
	};
};

&soc {
	virt_smmuv3: qcom,virt-smmuv3 {
		#iommu-cells = <1>;
		compatible = "arm,virt-smmu-v3";
	};

	tcsr_compute_signal_glb: syscon@0x1fd8000 {
		compatible = "syscon";
		reg = <0x1fd8000 0x1000>;
	};

	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
		compatible = "syscon";
		reg = <0x1fd9000 0x1000>;
	};

	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
		compatible = "syscon";
		reg = <0x1fdd000 0x1000>;
	};

	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
		compatible = "syscon";
		reg = <0x1fdb000 0x1000>;
	};

	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
		compatible = "syscon";
		reg = <0x1fdf000 0x1000>;
	};

	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
		compatible = "qcom,hgsl-tcsr-sender";
		syscon = <&tcsr_compute_signal_sender0>;
		syscon-glb = <&tcsr_compute_signal_glb>;
	};

	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
		compatible = "qcom,hgsl-tcsr-sender";
		syscon = <&tcsr_compute_signal_sender1>;
		syscon-glb = <&tcsr_compute_signal_glb>;
	};

	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
		compatible = "qcom,hgsl-tcsr-receiver";
		syscon = <&tcsr_compute_signal_receiver0>;
		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
	};

	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
		compatible = "qcom,hgsl-tcsr-receiver";
		syscon = <&tcsr_compute_signal_receiver1>;
		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
	};

	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
		compatible = "qcom,hgsl";
		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";

		qcom,glb-db-senders = <&hgsl_tcsr_sender0
					&hgsl_tcsr_sender1>;
		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
					&hgsl_tcsr_receiver1>;
	};
};

#include "pm8540-vm.dtsi"
#include "direwolf-pinctrl.dtsi"
#include "direwolf-vm-pcie.dtsi"
#include "direwolf-vm-qupv3.dtsi"
#include "direwolf-vm-usb.dtsi"
#include "direwolf-vm-ufs.dtsi"
&qupv3_0 {
	qcom,iommu-dma = "bypass";
};

&qupv3_1 {
	qcom,iommu-dma = "bypass";
};

&qupv3_2 {
	qcom,iommu-dma = "bypass";
};

&pm8540_2_gpios {
	usb20_vbus_boost {
		usb20_vbus_boost_default: usb20_vbus_boost_default {
			pins = "gpio9";
			function = "normal";
			output-high;
			power-source = <0>;
		};
	};
};

&pm8540_3_gpios {
	usb21_vbus_boost {
		usb21_vbus_boost_default: usb21_vbus_boost_default {
			pins = "gpio5";
			function = "normal";
			output-high;
			power-source = <0>;
		};
	};
};

&pm8540_4_gpios {
	usb223_vbus_boost {
		usb22_vbus_boost_default: usb22_vbus_boost_default {
			pins = "gpio5";
			function = "normal";
			output-high;
			power-source = <0>;
		};

		usb23_vbus_boost_default: usb23_vbus_boost_default {
			pins = "gpio9";
			function = "normal";
			output-high;
			power-source = <0>;
		};
	};
};

&usb2 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb20_vbus_boost_default &usb21_vbus_boost_default
				&usb22_vbus_boost_default &usb23_vbus_boost_default>;
};