#include #include &soc { /* Primary USB port related controller */ usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x0a600000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_RISING>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_prim_gdsc>; dpdm-supply = <&usb2_phy0>; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, /* * GCC_USB3_SEC_CLKREF_EN provides ref_clk for both * USB instances. */ <&gcc GCC_USB3_SEC_CLKREF_EN>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; dwc0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xd93c>; iommus = <&apps_smmu 0x0 0x0>; qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; interrupts = ; usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "otg"; usb-role-switch; }; qcom,usbbam@a704000 { compatible = "qcom,usb-bam-msm"; reg = <0xa704000 0x17000>; interrupts = ; qcom,usb-bam-fifo-baseaddr = <0x146bb000>; qcom,usb-bam-num-pipes = <4>; qcom,disable-clk-gating; qcom,usb-bam-override-threshold = <0x4001>; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x6064000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0x1800>; qcom,descriptor-fifo-offset = <0x1800>; qcom,descriptor-fifo-size = <0x800>; }; }; }; /* Primary USB port related High Speed PHY */ usb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e3000 0x110>, <0x088e2000 0x4>; reg-names = "hsusb_phy_base", "eud_enable_reg"; vdd-supply = <&pm8150_l5>; vdda18-supply = <&pm8150_l12>; vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; }; /* Primary USB port related QMP USB DP Combo PHY */ usb_qmp_dp_phy: ssphy@88e8000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x88e8000 0x3000>; reg-names = "qmp_phy_base"; vdd-supply = <&pm8150_l18>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&pm8150_l9>; qcom,qmp-phy-init-seq = /* */ ; qcom,qmp-phy-reg-offset = ; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "com_aux_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; }; usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; iommus = <&apps_smmu 0x180f 0x0>; qcom,iommu-dma = "disabled"; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; /* Secondary USB port related controller */ usb1: ssusb@a800000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa800000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_sec_gdsc>; clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_USB3_SEC_CLKREF_EN>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,charging-disabled; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, <&aggre1_noc MASTER_USB3_1 &config_noc SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; dwc1: dwc3@a800000 { compatible = "snps,dwc3"; reg = <0xa800000 0xd93c>; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; interrupts = ; usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; tx-fifo-resize; maximum-speed = "super-speed"; dr_mode = "drd"; }; }; /* Primary USB port related High Speed PHY */ usb2_phy1: hsphy@88e4000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e4000 0x110>; reg-names = "hsusb_phy_base"; vdd-supply = <&pm8150_l5>; vdda18-supply = <&pm8150_l12>; vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; }; /* Secondary USB port related QMP PHY */ usb_qmp_phy: ssphy@88eb000 { compatible = "qcom,usb-ssphy-qmp-v2"; reg = <0x88eb000 0x1000>, <0x088eb88c 0x4>; reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; vdd-supply = <&pm8150_l18>; qcom,vdd-voltage-level = <0 912000 912000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&pm8150_l9>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = /* */ ; qcom,qmp-phy-reg-offset = ; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_SEC_CLKREF_EN>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB3PHY_PHY_SEC_BCR>; reset-names = "phy_reset", "phy_phy_reset"; }; };