#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {
		apps_smmu: apps-smmu@15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x40000>;
		#iommu-cells = <2>;
		qcom,use-3-lvl-tables;
		#global-interrupts = <1>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		dma-coherent;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;

		anoc_1_qtb: anoc_1_qtb@1680000 {
			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
			reg = <0x1680000 0x1000>;
			qcom,stream-id-range = <0x0 0x400>;
			qcom,iova-width = <36>;
			qcom,num-qtb-ports = <1>;
		};

		ipa_qtb: ipa_qtb@1688000 {
			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
			reg = <0x1688000 0x1000>;
			qcom,stream-id-range = <0x400 0x400>;
			qcom,iova-width = <41>;
			qcom,num-qtb-ports = <1>;
		};

		pcie_qtb: pcie_qtb@16d0000 {
			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
			reg = <0x16d0000 0x1000>;
			qcom,stream-id-range = <0x800 0x400>;
			qcom,iova-width = <36>;
			qcom,num-qtb-ports = <1>;
			qcom,opt-out-tbu-halting;
		};
	};

	dma_dev {
		compatible = "qcom,iommu-dma";
		memory-region = <&system_cma>;
	};

	iommu_test_device {
		compatible = "qcom,iommu-debug-test";

		usecase0_apps {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x3e0 0x0>;
		};

		usecase1_apps_fastmap {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x3e0 0x0>;
			qcom,iommu-dma = "fastmap";
		};

		usecase2_apps_atomic {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x3e0 0x0>;
			qcom,iommu-dma = "atomic";
		};

		usecase3_apps_dma {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x3e0 0x0>;
			dma-coherent;
		};

	};
};