/ {
	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};
		};

		CPU0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1126>;
			sched-energy-costs = <&CPU_COST_0>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1126>;
			sched-energy-costs = <&CPU_COST_0>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_101: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_101: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU2: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <1126>;
			sched-energy-costs = <&CPU_COST_0>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_102: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_102: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU3: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <1126>;
			sched-energy-costs = <&CPU_COST_0>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L1_I_103: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_103: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU4: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_1>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			};

			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU5: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_1>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L1_I_1: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_1: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU6: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_1>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L1_I_2: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_2: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU7: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_1>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L1_I_3: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_3: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};
	};

	energy_costs: energy-costs {

		CPU_COST_0: core-cost0 {
			busy-cost-data = <
				 512  623
				 731  917
				 805 1106
				 914 1432
				1024 1740
			>;
		};

		CPU_COST_1: core-cost1 {
			busy-cost-data = <
				333  70
				532 114
				599 141
				665 178
				732 213
			>;
		};
	};
};