&soc {
	msm_bus: qcom,kgsl-busmon {
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
	};

	gpu_bw_tbl: gpu-bw-tbl {
		compatible = "operating-points-v2";
		opp-0   { opp-hz = /bits/ 64 < 0 >;     }; /* OFF */

		opp-100 { opp-hz = /bits/ 64 < 769 >;   }; /*  1. 100 MHz */

		opp-211 { opp-hz = /bits/ 64 < 1611 >;  }; /*  2. 211 MHz */

		opp-278 { opp-hz = /bits/ 64 < 2124 >;  }; /*  3. 278 MHz */

		opp-384 { opp-hz = /bits/ 64 < 2929 >;  }; /*  4. 384 MHz */

		opp-537 { opp-hz = /bits/ 64 < 4101 >;  }; /*  5. 537 MHz */

		opp-557 { opp-hz = /bits/ 64 < 4248 >;  }; /*  6. 557 MHz */

		opp-700 { opp-hz = /bits/ 64 < 5346 >;  }; /*  7. 700 MHz */

		opp-748 { opp-hz = /bits/ 64 < 5712 >;  }; /*  8. 748 MHz */

		opp-806 { opp-hz = /bits/ 64 < 6152 >;  }; /*  9. 806 MHz */

		opp-922 { opp-hz = /bits/ 64 < 7031 >;  }; /* 10. 922 MHz */
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		operating-points-v2 = <&gpu_bw_tbl>;
		/*
		 * active-only flag is used while registering the bus
		 * governor.It helps release the bus vote when the CPU
		 * subsystem is inactiv3
		 */
		qcom,active-only;
	};

	msm_gpu: qcom,kgsl-3d0@1c00000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x1c00000 0x40000
		       0xa0000 0x6fff>;
		reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
		interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;
		qcom,chipid = <0x05000500>;

		qcom,initial-pwrlevel = <2>;

		qcom,idle-timeout = <80>; //msecs
		qcom,strtstp-sleepwake;

		qcom,highest-bank-bit = <14>;

		qcom,snapshot-size = <1048576>; //bytes

		clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
			<&gcc GCC_OXILI_AHB_CLK>,
			<&gcc GCC_BIMC_GFX_CLK>,
			<&gcc GCC_BIMC_GPU_CLK>,
			<&gcc GCC_OXILI_TIMER_CLK>,
			<&gcc GCC_OXILI_AON_CLK>;

		clock-names = "core_clk", "iface_clk",
			      "mem_iface_clk", "alt_mem_iface_clk",
			      "rbbmtimer_clk", "alwayson_clk";


		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;
		qcom,bus-width = <16>;
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <11>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<26 512 0 0>,	    /*    off        */
				<26 512 0  806400>, /* 1. 100.80 MHz */
				<26 512 0 1689600>, /* 2. 211.20 MHz */
				<26 512 0 2227200>, /* 3. 278.40 MHz */
				<26 512 0 3072000>, /* 4. 384.00 MHz */
				<26 512 0 4300800>, /* 5. 537.60 MHz */
				<26 512 0 4454400>, /* 6. 556.80 MHz */
				<26 512 0 5299200>, /* 7. 662.40 MHz */
				<26 512 0 5990400>, /* 8. 748.80 MHz */
				<26 512 0 6451200>, /* 9. 806.40 MHz */
				<26 512 0 7372800>; /* 10. 921.60 MHz */

		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gdsc_oxili_cx>;
		vdd-supply = <&gdsc_oxili_gx>;

		/* CPU latency parameter */
		qcom,pm-qos-active-latency = <360>;
		qcom,pm-qos-wakeup-latency = <360>;

		/*  Quirks  */
		qcom,gpu-quirk-two-pass-use-wfi;
		qcom,gpu-quirk-dp2clockgating-disable;
		qcom,gpu-quirk-lmloadkill-disable;

		/* Enable context aware freq. scaling */
		qcom,enable-ca-jump;

		/* Context aware jump busy penalty in us */
		qcom,ca-busy-penalty = <12000>;

		/* Context aware jump target power level */
		qcom,ca-target-pwrlevel = <1>;

		/* Enable gpu cooling device */
		#cooling-cells = <2>;

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells= <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			qcom,mempool-max-pages = <32768>;

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <65536>;
			};
		};

		qcom,gpu-coresights {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-coresight";

			/* Trace bus */
			qcom,gpu-coresight@0 {
				reg = <0>;
				coresight-name = "coresight-gfx";
				coresight-atid = <67>;
				port {
					gfx_out_funnel_mm: endpoint {
						remote-endpoint =
						<&funnel_mm_in_gfx>;
					};
				};
			};
		};

		/* Power levels */
		qcom,gpu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			/* TURBO */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <450000000>;
				qcom,bus-freq = <9>;
				qcom,bus-min = <9>;
				qcom,bus-max = <9>;
			};

			/* NOM+ */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <400000000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <6>;
				qcom,bus-max = <9>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <375000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <8>;
			};

			/* SVS+ */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <300000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <7>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <216000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <1>;
				qcom,bus-max = <4>;
			};

			/* XO */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <19200000>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};
	};

	kgsl_msm_iommu: qcom,kgsl-iommu@1c40000 {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1c40000 0x10000>;

		clocks = <&gcc GCC_OXILI_AHB_CLK>,
			 <&gcc GCC_BIMC_GFX_CLK>;

		clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";

		qcom,secure_align_mask = <0xfff>;
		qcom,retention;
		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0>;
			qcom,iommu-dma = "disabled";
			qcom,gpu-offset = <0x48000>;
		};
	};
};