#include "sdm660-pinctrl.dtsi" / { aliases { spi1 = &spi_1; spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; spi5 = &spi_5; spi6 = &spi_6; spi7 = &spi_7; spi8 = &spi_8; i2c1 = &i2c_1; i2c2 = &i2c_2; i2c3 = &i2c_3; i2c4 = &i2c_4; i2c5 = &i2c_5; i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; }; }; &soc { i2c_1: i2c@c175000 { /* BLSP1 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc175000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp1 4 64 0x20000020 0x20>, <&dma_blsp1 5 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 2 0x00>; qcom,i2c-clk = <&tlmm 3 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_1_active>; pinctrl-1 = <&i2c_1_sleep>; pinctrl-2 = <&i2c_1_bitbang>; status = "disabled"; }; i2c_2: i2c@c176000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc176000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp1 6 64 0x20000020 0x20>, <&dma_blsp1 7 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 6 0x00>; qcom,i2c-clk = <&tlmm 7 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; pinctrl-2 = <&i2c_2_bitbang>; status = "disabled"; }; i2c_3: i2c@c177000 { /* BLSP1 QUP3 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc177000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 10 0x00>; qcom,i2c-clk = <&tlmm 11 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; pinctrl-2 = <&i2c_3_bitbang>; status = "disabled"; }; i2c_4: i2c@c178000 { /* BLSP1 QUP4 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc178000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp1 10 64 0x20000020 0x20>, <&dma_blsp1 11 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 14 0x00>; qcom,i2c-clk = <&tlmm 15 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; pinctrl-2 = <&i2c_4_bitbang>; status = "disabled"; }; i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc1b5000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp2 4 64 0x20000020 0x20>, <&dma_blsp2 5 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 18 0x00>; qcom,i2c-clk = <&tlmm 19 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; pinctrl-2 = <&i2c_5_bitbang>; status = "disabled"; }; i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc1b6000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp2 6 64 0x20000020 0x20>, <&dma_blsp2 7 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 22 0x00>; qcom,i2c-clk = <&tlmm 23 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_6_active>; pinctrl-1 = <&i2c_6_sleep>; pinctrl-2 = <&i2c_6_bitbang>; status = "disabled"; }; i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc1b7000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp2 8 64 0x20000020 0x20>, <&dma_blsp2 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 26 0x00>; qcom,i2c-clk = <&tlmm 27 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_7_active>; pinctrl-1 = <&i2c_7_sleep>; pinctrl-2 = <&i2c_7_bitbang>; status = "disabled"; }; i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0xc1b8000 0x600>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma_blsp2 10 64 0x20000020 0x20>, <&dma_blsp2 11 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <84>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; qcom,i2c-dat = <&tlmm 30 0x00>; qcom,i2c-clk = <&tlmm 31 0x00>; pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; pinctrl-0 = <&i2c_8_active>; pinctrl-1 = <&i2c_8_sleep>; pinctrl-2 = <&i2c_8_bitbang>; status = "disabled"; }; spi_1: spi@c175000 { /* BLSP1 QUP1 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc175000 0x600>, <0xc144000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <4>; qcom,bam-producer-pipe-index = <5>; qcom,master-id = <86>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_1_active>; pinctrl-1 = <&spi_1_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; status = "disabled"; }; spi_2: spi@c176000 { /* BLSP1 QUP2 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc176000 0x600>, <0xc144000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <6>; qcom,bam-producer-pipe-index = <7>; qcom,master-id = <86>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_2_active>; pinctrl-1 = <&spi_2_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; status = "disabled"; }; spi_3: spi@c177000 { /* BLSP1 QUP3 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc177000 0x600>, <0xc144000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <8>; qcom,bam-producer-pipe-index = <9>; qcom,master-id = <86>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_3_active>; pinctrl-1 = <&spi_3_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; status = "disabled"; }; spi_4: spi@c178000 { /* BLSP1 QUP4 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc178000 0x600>, <0xc144000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <10>; qcom,bam-producer-pipe-index = <11>; qcom,master-id = <86>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_4_active>; pinctrl-1 = <&spi_4_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; status = "disabled"; }; spi_5: spi@c1b5000 { /* BLSP2 QUP1 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc1b5000 0x600>, <0xc184000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <4>; qcom,bam-producer-pipe-index = <5>; qcom,master-id = <84>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_5_active>; pinctrl-1 = <&spi_5_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>; status = "disabled"; }; spi_6: spi@c1b6000 { /* BLSP2 QUP2 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc1b6000 0x600>, <0xc184000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <6>; qcom,bam-producer-pipe-index = <7>; qcom,master-id = <84>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_6_active>; pinctrl-1 = <&spi_6_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>; status = "disabled"; }; spi_7: spi@c1b7000 { /* BLSP2 QUP3 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc1b7000 0x600>, <0xc184000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <8>; qcom,bam-producer-pipe-index = <9>; qcom,master-id = <84>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_7_active>; pinctrl-1 = <&spi_7_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>; status = "disabled"; }; spi_8: spi@c1b8000 { /* BLSP2 QUP4 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0xc1b8000 0x600>, <0xc184000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; qcom,use-bam; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <10>; qcom,bam-producer-pipe-index = <11>; qcom,master-id = <84>; qcom,use-pinctrl; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi_8_active>; pinctrl-1 = <&spi_8_sleep>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>; status = "disabled"; }; blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */ compatible = "qcom,msm-hsuart-v14"; reg = <0xc16f000 0x200>, <0xc144000 0x1f000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart1_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 107 0 1 &intc 0 0 238 0 2 &tlmm 1 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xfd>; qcom,bam-tx-ep-pipe-index = <0>; qcom,bam-rx-ep-pipe-index = <1>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart1_sleep>; pinctrl-1 = <&blsp1_uart1_active>; qcom,msm-bus,name = "buart1"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */ compatible = "qcom,msm-hsuart-v14"; reg = <0xc170000 0x200>, <0xc144000 0x1f000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart2_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 108 0 1 &intc 0 0 238 0 2 &tlmm 5 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xfd>; qcom,bam-tx-ep-pipe-index = <2>; qcom,bam-rx-ep-pipe-index = <3>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart2_sleep>; pinctrl-1 = <&blsp1_uart2_active>; qcom,msm-bus,name = "buart2"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */ compatible = "qcom,msm-hsuart-v14"; reg = <0xc1af000 0x200>, <0xc184000 0x1f000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp2_uart1_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 113 0 1 &intc 0 0 239 0 2 &tlmm 17 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xfd>; qcom,bam-tx-ep-pipe-index = <0>; qcom,bam-rx-ep-pipe-index = <1>; qcom,master-id = <84>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>, <&clock_gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp2_uart1_tx_sleep>, <&blsp2_uart1_rxcts_sleep>, <&blsp2_uart1_rfr_sleep>; pinctrl-1 = <&blsp2_uart1_tx_active>, <&blsp2_uart1_rxcts_active>, <&blsp2_uart1_rfr_active>; qcom,msm-bus,name = "buart3"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <84 512 0 0>, <84 512 500 800>; status = "disabled"; }; blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */ compatible = "qcom,msm-hsuart-v14"; reg = <0xc1b0000 0x200>, <0xc184000 0x1f000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp2_uart2_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 0 114 0 1 &intc 0 0 239 0 2 &tlmm 25 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xfd>; qcom,bam-tx-ep-pipe-index = <2>; qcom,bam-rx-ep-pipe-index = <3>; qcom,master-id = <84>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, <&clock_gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp2_uart2_sleep>; pinctrl-1 = <&blsp2_uart2_active>; qcom,msm-bus,name = "buart4"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <84 512 0 0>, <84 512 500 800>; status = "disabled"; }; };