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Qualcomm Technologies, Inc. Display Clock Controller Binding
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Required properties :
- compatible : shall contain only one of the following:
"qcom,sdm845-dispcc"
"qcom,lahaina-dispcc"
"qcom,shima-dispcc"
"qcom,holi-dispcc"
"qcom,sm8150-dispcc"
"qcom,sm8150-dispcc-v2"
"qcom,yupik-dispcc"
"qcom,scshrike-dispcc"
"qcom,scshrike-dispcc-v2"
"qcom,sm6150-dispcc"
"qcom,sa6155-dispcc"
"qcom,monaco-dispcc"
"qcom,blair-dispcc"
"qcom,scuba-dispcc"
"qcom,direwolf-dispcc0"
"qcom,direwolf-dispcc1"
"qcom,bengal-dispcc"
"qcom,lemans-dispcc0"
"qcom,lemans-dispcc1"
"qcom,kona-dispcc"
"qcom,scuba-dispcc"
"qcom,lemans-dispcc0"
"qcom,lemans-dispcc1"
"qcom,sm8250-dispcc"
"qcom,crow-dispcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.
- #power-domain-cells : from generic power domain binding, shall contain 1.
Example:
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x100000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
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