1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
Qualcomm Technologies, Inc. Global Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-ipq4019"
"qcom,gcc-ipq8074"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
"qcom,gcc-msm8974"
"qcom,gcc-msm8974pro"
"qcom,gcc-msm8974pro-ac"
"qcom,gcc-msm8994"
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
"qcom,gcc-qcs404"
"qcom,gcc-sdm630"
"qcom,gcc-sdm660"
"qcom,gcc-sdm845"
"qcom,lahaina-gcc"
"qcom,sm8150-gcc"
"qcom,gcc-sm8250"
"qcom,sm8150-gcc-v2"
"qcom,sa8155-gcc"
"qcom,sa8155-gcc-v2"
"qcom,shima-gcc"
"qcom,holi-gcc"
"qcom,sdxlemur-gcc"
"qcom,waipio-gcc"
"qcom,diwali-gcc"
"qcom,kalama-gcc"
"qcom,kalama-gcc-v2"
"qcom,cinder-gcc"
"qcom,cinder-gcc-v2"
"qcom,khaje-gcc"
"qcom,gcc-sc8180x"
"qcom,monaco-gcc"
"qcom,sdxpinn-gcc"
"qcom,scuba-gcc"
"qcom,sdxbaagha-gcc"
"qcom,lemans-gcc"
"qcom,sa410m-gcc"
"qcom,direwolf-gcc"
"qcom,crow-gcc"
"qcom,monaco_auto-gcc"
- reg : shall contain base register location and length
- vdd_cx-supply: The vdd_cx logic rail supply.
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
Optional properties :
- #power-domain-cells : shall contain 1
- QTI TSENS (thermal sensor device) on some devices can
be part of GCC and hence the TSENS properties can also be
part of the GCC/clock-controller node.
For more details on the TSENS properties please refer
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
- protected-clocks : Protected clock specifier list as per common clock
binding.
- qcom,critical-clocks : List of clock specifiers that should be enabled during
probe and not registered with the clock framework.
- qcom,critical-devices : List of device phandles whose associated clocks
should be enabled during probe and not registered with the clock framework.
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
Example of GCC with TSENS properties:
clock-controller@900000 {
compatible = "qcom,gcc-apq8064";
reg = <0x00900000 0x4000>;
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#thermal-sensor-cells = <1>;
};
Example of GCC with protected-clocks properties:
clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
Example of GCC with qcom,critical-clocks properties:
clock-controller@100000 {
compatible = "qcom,waipio-gcc", "syscon";
reg = <0x100000 0x1f4200>;
#clock-cells = <1>;
#reset-cells = <1>;
qcom,critical-clocks = <GCC_QUPV3_WRAP0_S5_CLK>,
<GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<GCC_QUPV3_WRAP_0_S_AHB_CLK>;
};
Example of GCC with qcom,critical-devices properties:
clock-controller@100000 {
compatible = "qcom,waipio-gcc", "syscon";
reg = <0x100000 0x1f4200>;
#clock-cells = <1>;
#reset-cells = <1>;
qcom,critical-devices = <&qupv3_se5_i2c>;
};
|
