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* Inline Crypto Engine (ICE)
Required properties:
- compatible : should be "qcom,ice"
- reg : <register mapping>
Optional properties:
- interrupt-names : name describing the interrupts for ICE IRQ
- interrupts : <interrupt mapping for ICE IRQ>
- qcom,enable-ice-clk : should enable clocks for ICE HW
- clocks : List of phandle and clock specifier pairs
- clock-names : List of clock input name strings sorted in the same
order as the clocks property.
- qocm,op-freq-hz : max clock speed sorted in the same order as the clocks
property.
- qcom,instance-type : describe the storage type for which ICE node is defined
currently, only "ufs" and "sdcc" are supported storage type
- vdd-hba-supply : regulated supply to be used by ICE HW
- qcom,bus-vector-names : bus vectors mapping
Example:
ufs_ice: ufsice@630000 {
compatible = "qcom,ice";
reg = <0x630000 0x8000>;
interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";
interrupts = <0 258 0>, <0 257 0>;
qcom,enable-ice-clk;
clock-names = "ice_core_clk_src", "ice_core_clk";
clocks = <&clock_gcc clk_ufs_ice_core_clk_src>,
<&clock_gcc clk_gcc_ufs_ice_core_clk>;
qcom,op-freq-hz = <300000000>, <0>;
qcom,instance-type = "ufs";
status = "disabled";
};
ufs_card_ice: ufscardice@1db0000 {
compatible = "qcom,ice_card";
reg = <0x1db0000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ufs_core_clk", "bus_clk",
"iface_clk", "ice_core_clk";
clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>,
<&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,
<&clock_gcc GCC_UFS_CARD_AHB_CLK>,
<&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>;
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
vdd-hba-supply = <&ufs_card_gdsc>;
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "ufs_card";
};
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