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Qualcomm Technologies, Inc. NPU powerlevels
Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines
a series of clock frequencies. These frequencies are for the corresponding
clocks in the clocks property of the msm_npu device.
qcom,npu-pwrlevels bindings:
Required Properties:
- #address-cells: Should be set to 1
- #size-cells: Should be set to 0
- compatible: Must be qcom,npu-pwrlevels
- initial-pwrlevel: NPU initial wakeup power level, this is the index of the
child node.
qcom,npu-pwrlevel: This is a child node defining power levels.
qcom,npu-pwrlevels must contain at least one power level node. Each child node
has the following properties:
Required Properties:
- reg: Index of the powerlevel (0 = lowest performance)
- clk-freq: List of clock frequencies (in Hz) of each clock for the current
powerlevel. List of clocks and order described in:
Documentation/devicetree/bindings/media/msm-npu.txt
Example:
qcom,npu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,npu-pwrlevels";
initial-pwrlevel = <4>;
qcom,npu-pwrlevel@0 {
reg = <0>;
clk-freq = <9600000
9600000
19200000
19200000
19200000
19200000
9600000
60000000
19200000
19200000
30000000
19200000
19200000
19200000
19200000
19200000
9600000
19200000
0>;
};
qcom,npu-pwrlevel@1 {
reg = <1>;
clk-freq = <300000000
300000000
19200000
100000000
19200000
19200000
300000000
150000000
19200000
19200000
60000000
100000000
100000000
37500000
100000000
19200000
300000000
19200000
0>;
};
qcom,npu-pwrlevel@2 {
reg = <2>;
clk-freq = <350000000
350000000
19200000
150000000
19200000
19200000
350000000
200000000
37500000
19200000
120000000
150000000
150000000
75000000
150000000
19200000
350000000
19200000
0>;
};
qcom,npu-pwrlevel@3 {
reg = <3>;
clk-freq = <400000000
400000000
19200000
200000000
19200000
19200000
400000000
300000000
37500000
19200000
120000000
200000000
200000000
75000000
200000000
19200000
400000000
19200000
0>;
};
qcom,npu-pwrlevel@4 {
reg = <4>;
clk-freq = <600000000
600000000
19200000
300000000
19200000
19200000
600000000
403000000
75000000
19200000
240000000
300000000
300000000
150000000
300000000
19200000
600000000
19200000
0>;
};
qcom,npu-pwrlevel@5 {
reg = <5>;
clk-freq = <715000000
715000000
19200000
350000000
19200000
19200000
715000000
533000000
75000000
19200000
240000000
350000000
350000000
150000000
350000000
19200000
715000000
19200000
0>;
};
};
|
