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&soc {
/* QUPv3_0 Wrapper Instance */
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
ranges;
status = "ok";
/* Debug UART Instance */
qupv3_se5_2uart: qcom,qup_uart@894000 {
compatible = "qcom,geni-debug-uart";
reg = <0x894000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_2uart_tx_active>, <&qupv3_se5_2uart_rx_active>;
pinctrl-1 = <&qupv3_se5_2uart_sleep>;
status = "disabled";
};
};
};
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