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&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup0 5: SE 5
* Qup0 6: SE 6
* Qup0 7: SE 7
* Qup1 0: SE 8
* Qup1 1: SE 9
* Qup1 2: SE 10
* Qup1 3: SE 11
* Qup1 4: SE 12
* Qup1 5: SE 13
* Qup1 6: SE 14
* Qup1 7: SE 15
* Qup2 0: SE 16
* Qup2 1: SE 17
* Qup2 2: SE 18
* Qup2 3: SE 19
* Qup2 4: SE 20
* Qup2 5: SE 21
* Qup2 6: SE 22
* Qup2 7: SE 23
*/
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x9c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x563 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
status = "disabled";
};
/* 4-wire HSUART Instance */
qupv3_se2_4uart: qcom,qup_uart@988000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x988000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 124 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default", "active", "sleep";
pinctrl-0 = <&qupv3_se2_default_cts>,
<&qupv3_se2_default_rtsrx>, <&qupv3_se2_default_tx>;
pinctrl-1 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>;
pinctrl-2 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
qupv3_se4_spi: spi@990000 {
compatible = "qcom,spi-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se6_4uart: qcom,qup_uart@998000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x998000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 157 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default", "active", "sleep";
pinctrl-0 = <&qupv3_se6_default_cts>,
<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
<&qupv3_se6_tx>;
pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
<&qupv3_se6_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x83 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
/* GNSS UART Instance */
qupv3_se13_2uart: qcom,qup_uart@a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default", "active", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_default>;
pinctrl-1 = <&qupv3_se13_2uart_active>;
pinctrl-2 = <&qupv3_se13_2uart_sleep>;
status = "disabled";
};
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0xa3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
/* Debug UART Instance */
qupv3_se17_2uart: qcom,qup_uart@884000 {
compatible = "qcom,geni-debug-uart";
reg = <0x884000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se17_2uart_active>;
pinctrl-1 = <&qupv3_se17_2uart_sleep>;
status = "disabled";
};
};
};
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