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®ulator {
L8G0: pm8540_g0_l8: regulator-pm8540_g0-l8 {
regulator-name = "ldog8";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
};
L3G0: pm8540_g0_l3: regulator-pm8540_g0-l3 {
regulator-name = "ldog3";
regulator-min-microvolt = <1130000>;
regulator-max-microvolt = <1260000>;
};
gcc_ufs_card_gdsc: gcc_ufs_card_gdsc {
regulator-name = "gcc_ufs_card_gdsc";
};
L10C0: pm8540_c0_l10: regulator-pm8540_c0-l10 {
regulator-name = "ldoc10";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2960000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
L3C0: pm8540_c0_l3: regulator-pm8540_c0-l3 {
regulator-name = "ldoc3";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
&soc {
ufs2phy_mem: ufsphy_mem@1da7000 {
compatible = "qcom,ufs-phy-qmp-v4-direwolf";
reg = <0x1da7000 0xe10>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
vdda-phy-supply = <&L8G0>;
vdda-pll-supply = <&L3G0>;
vdda-phy-max-microamp = <85700>;
vdda-pll-max-microamp = <18300>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk",
"ref_clk_parent";
clocks = <&dummycc RPMH_CXO_CLK>,
<&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
<&gcc GCC_UFS_REF_CLKREF_CLK>;
resets = <&ufshc2_mem 0>;
status = "disabled";
};
ufshc2_mem: ufshc@1da4000 {
compatible = "qcom,ufshc";
reg = <0x1da4000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs2phy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
vdd-hba-supply = <&gcc_ufs_card_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L10C0>;
vcc-voltage-level = <2504000 2504000>;
vcc-max-microamp = <800000>;
vccq-supply = <&L3C0>;
vccq-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L3C0>;
qcom,vddp-ref-clk-max-microamp = <100>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_CARD_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&gcc GCC_UFS_CARD_AHB_CLK>,
<&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_CARD_ICE_CORE_CLK>,
<&dummycc RPMH_CXO_CLK>,
<&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<1492582 0>, <102400 0>, /* HS G3 RA */
<2915200 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<1492582 0>, <204800 0>, /* HS G3 RA L2 */
<2915200 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<1492582 0>, <102400 0>, /* HS G3 RB */
<2915200 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_CARD_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x4a0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
status = "disabled";
};
};
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