path: root/qcom/khaje.dtsi

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,dispcc-khaje.h>
#include <dt-bindings/clock/qcom,gcc-khaje.h>
#include <dt-bindings/clock/qcom,gpucc-khaje.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
				opp-supported-hw = <ddrtype>;}

#define DDR_TYPE_LPDDR3		5
#define DDR_TYPE_LPDDR4X	7

/ {
	model = "Qualcomm Technologies, Inc. Khaje SoC";
	compatible = "qcom,khaje";
	qcom,msm-id = <518 0x10000>;
	interrupt-parent = <&wakegic>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	mem-offline {
		compatible = "qcom,mem-offline";
		offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
				<0x1 0xc0000000 0x0 0x80000000>,
				<0x2 0xc0000000 0x1 0x40000000>;
		granule = <512>;
	};

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
		swr0 = &swr0;
		swr1 = &swr1;
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 7>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
			};

			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 7>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L1_I_1: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_1: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 7>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L1_I_2: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_2: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 7>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L1_I_3: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_3: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1638>;
			dynamic-power-coefficient = <282>;
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 1 7>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x101>;
			capacity-dmips-mhz = <1638>;
			dynamic-power-coefficient = <282>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 1 7>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L1_I_101: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_101: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x102>;
			capacity-dmips-mhz = <1638>;
			dynamic-power-coefficient = <282>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 1 7>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L1_I_102: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_102: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x103>;
			capacity-dmips-mhz = <1638>;
			dynamic-power-coefficient = <282>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 1 7>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L1_I_103: l1-icache {
				compatible = "arm,arch-cache";
			};

			L1_D_103: l1-dcache {
				compatible = "arm,arch-cache";
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	firmware: firmware {
		android {
			compatible = "android,firmware";
			vbmeta {
				compatible="android,vbmeta";
				parts = "vbmeta,boot,system,vendor,dtbo,recovery";
			};

			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro,barrier=1,discard";
					fsmgr_flags = "wait,slotselect,avb";
					status = "ok";
				};
			};
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp_region@45700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x45700000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_region@45e00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x45e00000 0x0 0x140000>;
		};

		sec_apps_mem: sec_apps_region@45fff000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x45fff000 0x0 0x1000>;
		};

		smem_mem: smem_region@46000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x46000000 0x0 0x200000>;
		};

		removed_mem: removed_region@60000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x60000000 0x0 0x3900000>;
		};

		pil_modem_mem: modem_region@4ab00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x4ab00000 0x0 0x6900000>;
		};

		pil_video_mem: pil_video_region@51400000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x51400000 0x0 0x500000>;
		};

		wlan_msa_mem: wlan_msa_region@51900000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x51900000 0x0 0x100000>;
		};

		pil_cdsp_mem: cdsp_regions@51a00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x51a00000 0x0 0x1e00000>;
		};

		pil_adsp_mem: pil_adsp_region@53800000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x53800000 0x0 0x1e00000>;
		};

		pil_ipa_fw_mem: ipa_fw_region@55600000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x55600000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: ipa_gsi_region@55610000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x55610000 0x0 0x5000>;
		};

		pil_gpu_mem: gpu_region@55615000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x55615000 0x0 0x2000>;
		};

		user_contig_mem: user_contig_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1400000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		cdsp_sec_mem: cdsp_sec_regions@46200000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x46200000 0x0 0x1e00000>;
		};

		secure_display_memory: secure_display_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x5c00000>;
		};

		cont_splash_memory: cont_splash_region@5c000000 {
			reg = <0x0 0x5c000000 0x0 0x00f00000>;
			label = "cont_splash_region";
		};

		disp_rdump_memory: disp_rdump_region@5c000000 {
			reg = <0x0 0x5c000000 0x0 0x00f00000>;
			label = "disp_rdump_region";
		};

		dfps_data_memory: dfps_data_region@5cf00000 {
			reg = <0x0 0x5cf00000 0x0 0x0100000>;
			label = "dfps_data_region";
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			size = <0 0x800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};

	chosen {
		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
	};

	soc: soc { };
};

#include "bengal-coresight.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@f200000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0xf200000 0x10000>,     /* GICD */
		      <0xf300000 0x100000>;    /* GICR * 8 */
		interrupts = <1 9 4>;
	};

	jtag_mm0: jtagmm@9040000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9040000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU0>;
	};

	jtag_mm1: jtagmm@9140000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9140000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU1>;
	};

	jtag_mm2: jtagmm@9240000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9240000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU2>;
	};

	jtag_mm3: jtagmm@9340000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9340000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU3>;
	};

	jtag_mm4: jtagmm@9440000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9440000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU4>;
	};

	jtag_mm5: jtagmm@9540000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9540000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU5>;
	};

	jtag_mm6: jtagmm@9640000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9640000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU6>;
	};

	jtag_mm7: jtagmm@9740000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x9740000 0x1000>;
		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU7>;
	};

	qcom,memshare {
		compatible = "qcom,memshare";

		qcom,client_1 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <0>;
			qcom,allocate-boot-time;
			label = "modem";
		};

		qcom,client_2 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <2>;
			label = "modem";
		};

		mem_client_3_size: qcom,client_3 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x500000>;
			qcom,client-id = <1>;
			qcom,allocate-on-request;
			label = "modem";
		};
	};

	slim_aud: slim@a5c0000 {
		cell-index = <1>;
		compatible = "qcom,slim-ngd";
		reg = <0xa5c0000 0x2c000>,
			<0xa584000 0x20000>, <0xa66e000 0x2000>;
		reg-names = "slimbus_physical",
			"slimbus_bam_physical", "slimbus_lpass_mem";
		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
		qcom,apps-ch-pipes = <0x0>;
		qcom,ea-pc = <0x3b0>;
		status = "ok";

		/* Slimbus Slave DT for WCN3990 */
		btfmslim_codec: wcn3990 {
			compatible = "qcom,btfmslim_slave";
			elemental-addr = [00 01 20 02 17 02];
			qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
			qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
		};
	};

	wakegic: wake-gic {
		compatible = "qcom,mpm-gic-khaje", "qcom,mpm-gic";
		interrupts-extended = <&wakegic GIC_SPI 197
						IRQ_TYPE_EDGE_RISING>;
		reg = <0x45f01b8 0x1000>,
			<0xf111008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
		reg-names = "vmpm", "ipc";
		qcom,num-mpm-irqs = <96>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <3>;
	};

	wakegpio: wake-gpio {
		compatible = "qcom,mpm-gpio";
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <2>;
	};

	bluetooth: bt_wcn3990 {
		compatible = "qca,wcn3990";
		qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
		qca,bt-vdd-io-supply =   <&L9A>;  /* IO */
		qca,bt-vdd-core-supply = <&L17A>; /* RFA */
		qca,bt-vdd-pa-supply =   <&L23A>; /* CH0 */
		qca,bt-vdd-xtal-supply = <&L16A>; /* XO */

		qca,bt-vdd-io-voltage-level = <1700000 1900000>;
		qca,bt-vdd-core-voltage-level = <1304000 1304000>;
		qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
		qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;

		qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
		qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
		qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
		qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 1 0xf08>,
			     <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 0 0xf08>;
		clock-frequency = <19200000>;
	};

	dcc: dcc_v2@1be2000 {
		compatible = "qcom,dcc-v2";
		reg = <0x1be2000 0x1000>,
			<0x1bee000 0x2000>;
		reg-names = "dcc-base", "dcc-ram-base";
		dcc-ram-offset = <0x2000>;

		link_list1 {
			qcom,curr-link-list = <3>;
			qcom,data-sink = "sram";
			qcom,link-list = <DCC_READ 0x0F1880B4 1 0>,
				<DCC_READ 0x0F1980B4 1 0>,
				<DCC_READ 0x0F1A80B4 1 0>,
				<DCC_READ 0x0F1B80B4 1 0>,
				<DCC_READ 0x0F0880B4 1 0>,
				<DCC_READ 0x0F0980B4 1 0>,
				<DCC_READ 0x0F0A80B4 1 0>,
				<DCC_READ 0x0F0B80B4 1 0>,
				<DCC_READ 0x0F1D1228 1 0>,
				<DCC_READ 0x0F1880B0 1 0>,
				<DCC_READ 0x0F1980B0 1 0>,
				<DCC_READ 0x0F1A80B0 1 0>,
				<DCC_READ 0x0F1B80B0 1 0>,
				<DCC_READ 0x0F0880B0 1 0>,
				<DCC_READ 0x0F0980B0 1 0>,
				<DCC_READ 0x0F0A80B0 1 0>,
				<DCC_READ 0x0F0B80B0 1 0>,
				<DCC_READ 0x0F1880B8 1 0>,
				<DCC_READ 0x0F1980B8 1 0>,
				<DCC_READ 0x0F1A80B8 1 0>,
				<DCC_READ 0x0F1B80B8 1 0>,
				<DCC_READ 0x0F0880B8 1 0>,
				<DCC_READ 0x0F0980B8 1 0>,
				<DCC_READ 0x0F0A80B8 1 0>,
				<DCC_READ 0x0F0B80B8 1 0>,
				<DCC_READ 0x0F1D160C 1 0>,
				<DCC_READ 0x0F1D120C 1 0>,
				<DCC_READ 0x0F1D1434 1 0>,
				<DCC_READ 0x0F1D141C 5 0>,
				<DCC_READ 0x0F1D1448 1 0>,
				<DCC_READ 0x0F1D144C 1 0>,
				<DCC_READ 0xA754520 1 0>,
				<DCC_READ 0xA751020 1 0>,
				<DCC_READ 0xA751024 1 0>,
				<DCC_READ 0xA751030 1 0>,
				<DCC_READ 0xA751200 1 0>,
				<DCC_READ 0xA751214 1 0>,
				<DCC_READ 0xA751228 1 0>,
				<DCC_READ 0xA75123C 1 0>,
				<DCC_READ 0xA751250 1 0>,
				<DCC_READ 0xA751204 1 0>,
				<DCC_READ 0xA751218 1 0>,
				<DCC_READ 0xA75122C 1 0>,
				<DCC_READ 0xA751240 1 0>,
				<DCC_READ 0xA751254 1 0>,
				<DCC_READ 0xA751208 1 0>,
				<DCC_READ 0xA75121C 1 0>,
				<DCC_READ 0xA751230 1 0>,
				<DCC_READ 0xA751244 1 0>,
				<DCC_READ 0xA751258 1 0>,
				<DCC_READ 0xA754510 1 0>,
				<DCC_READ 0xA754514 1 0>,
				<DCC_READ 0xA750010 1 0>,
				<DCC_READ 0xA750014 1 0>,
				<DCC_READ 0xA750900 1 0>,
				<DCC_READ 0xA750904 1 0>,
				<DCC_READ 0x0A402028 1 0>,
				<DCC_READ 0x0A900010 1 0>,
				<DCC_READ 0x0A900014 1 0>,
				<DCC_READ 0x0A900018 1 0>,
				<DCC_READ 0x0A900030 1 0>,
				<DCC_READ 0x0A900038 1 0>,
				<DCC_READ 0x0A900040 1 0>,
				<DCC_READ 0x0A900048 1 0>,
				<DCC_READ 0x0A9000D0 1 0>,
				<DCC_READ 0x0A900210 1 0>,
				<DCC_READ 0x0A900230 1 0>,
				<DCC_READ 0x0A900250 1 0>,
				<DCC_READ 0x0A900270 1 0>,
				<DCC_READ 0x0A900290 1 0>,
				<DCC_READ 0x0A9002B0 1 0>,
				<DCC_READ 0x0A900208 1 0>,
				<DCC_READ 0x0A900228 1 0>,
				<DCC_READ 0x0A900248 1 0>,
				<DCC_READ 0x0A900268 1 0>,
				<DCC_READ 0x0A900288 1 0>,
				<DCC_READ 0x0A9002A8 1 0>,
				<DCC_READ 0x0A90020C 1 0>,
				<DCC_READ 0x0A90022C 1 0>,
				<DCC_READ 0x0A90024C 1 0>,
				<DCC_READ 0x0A90026C 1 0>,
				<DCC_READ 0x0A90028C 1 0>,
				<DCC_READ 0x0A9002AC 1 0>,
				<DCC_READ 0x0A900404 1 0>,
				<DCC_READ 0x0A900408 1 0>,
				<DCC_READ 0x0A900400 1 0>,
				<DCC_READ 0x0A900D04 1 0>,
				<DCC_READ 0x0A4B0010 1 0>,
				<DCC_READ 0x0A4B0014 1 0>,
				<DCC_READ 0x0A4B0018 1 0>,
				<DCC_READ 0x0A4B0210 1 0>,
				<DCC_READ 0x0A4B0230 1 0>,
				<DCC_READ 0x0A4B0250 1 0>,
				<DCC_READ 0x0A4B0270 1 0>,
				<DCC_READ 0x0A4B0290 1 0>,
				<DCC_READ 0x0A4B02B0 1 0>,
				<DCC_READ 0x0A4B0208 1 0>,
				<DCC_READ 0x0A4B0228 1 0>,
				<DCC_READ 0x0A4B0248 1 0>,
				<DCC_READ 0x0A4B0268 1 0>,
				<DCC_READ 0x0A4B0288 1 0>,
				<DCC_READ 0x0A4B02A8 1 0>,
				<DCC_READ 0x0A4B020C 1 0>,
				<DCC_READ 0x0A4B022C 1 0>,
				<DCC_READ 0x0A4B024C 1 0>,
				<DCC_READ 0x0A4B026C 1 0>,
				<DCC_READ 0x0A4B028C 1 0>,
				<DCC_READ 0x0A4B02AC 1 0>,
				<DCC_READ 0x0A4B0400 1 0>,
				<DCC_READ 0x0A4B0404 1 0>,
				<DCC_READ 0x0A4B0408 1 0>,
				<DCC_READ 0x4488100 1 0>,
				<DCC_READ 0x4488400 2 0>,
				<DCC_READ 0x4488410 1 0>,
				<DCC_READ 0x4488420 2 0>,
				<DCC_READ 0x4488430 2 0>,
				<DCC_READ 0x448c100 1 0>,
				<DCC_READ 0x448c400 2 0>,
				<DCC_READ 0x448c410 1 0>,
				<DCC_READ 0x448c420 2 0>,
				<DCC_READ 0x448c430 2 0>,
				<DCC_READ 0x4490100 1 0>,
				<DCC_READ 0x4490400 2 0>,
				<DCC_READ 0x4490410 1 0>,
				<DCC_READ 0x4490420 2 0>,
				<DCC_READ 0x4490430 2 0>,
				<DCC_READ 0x4494100 1 0>,
				<DCC_READ 0x4494400 2 0>,
				<DCC_READ 0x4494410 1 0>,
				<DCC_READ 0x4494420 2 0>,
				<DCC_READ 0x4494430 2 0>,
				<DCC_READ 0x449810c 1 0>,
				<DCC_READ 0x4498400 2 0>,
				<DCC_READ 0x4498410 1 0>,
				<DCC_READ 0x4498420 2 0>,
				<DCC_READ 0x4498430 2 0>,
				<DCC_READ 0x44a0100 1 0>,
				<DCC_READ 0x44a0400 2 0>,
				<DCC_READ 0x44a0410 1 0>,
				<DCC_READ 0x44a0420 2 0>,
				<DCC_READ 0x44a0430 2 0>,
				<DCC_READ 0x44b0560 1 0>,
				<DCC_READ 0x44b05a0 1 0>,
				<DCC_READ 0x44b1800 1 0>,
				<DCC_READ 0x44b408c 1 0>,
				<DCC_READ 0x44b409c 1 0>,
				<DCC_READ 0x44b0520 1 0>,
				<DCC_READ 0x44b5070 2 0>,
				<DCC_READ 0x44bc220 1 0>,
				<DCC_READ 0x44bc400 7 0>,
				<DCC_READ 0x44bc420 9 0>,
				<DCC_READ 0x44bd800 1 0>,
				<DCC_READ 0x44c5800 1 0>,
				<DCC_READ 0x4480040 2 0>,
				<DCC_READ 0x4480810 2 0>,
				<DCC_READ 0x44b0a40 1 0>,
				<DCC_READ 0x4506044 1 0>,
				<DCC_READ 0x45061dc 1 0>,
				<DCC_READ 0x45061ec 1 0>,
				<DCC_READ 0x4506028 2 0>,
				<DCC_READ 0x4506094 1 0>,
				<DCC_READ 0x4506608 1 0>,
				<DCC_READ 0x447d02c 4 0>,
				<DCC_READ 0x447d040 1 0>,
				<DCC_READ 0x450002c 2 0>,
				<DCC_READ 0x4500094 1 0>,
				<DCC_READ 0x450009c 1 0>,
				<DCC_READ 0x45000c4 2 0>,
				<DCC_READ 0x45003dc 1 0>,
				<DCC_READ 0x45005d8 1 0>,
				<DCC_READ 0x450102c 2 0>,
				<DCC_READ 0x4501094 1 0>,
				<DCC_READ 0x450109c 1 0>,
				<DCC_READ 0x45010c4 2 0>,
				<DCC_READ 0x45013dc 1 0>,
				<DCC_READ 0x45015d8 1 0>,
				<DCC_READ 0x450202c 2 0>,
				<DCC_READ 0x4502094 1 0>,
				<DCC_READ 0x450209c 1 0>,
				<DCC_READ 0x45020c4 2 0>,
				<DCC_READ 0x45023dc 1 0>,
				<DCC_READ 0x45025d8 1 0>,
				<DCC_READ 0x450302c 2 0>,
				<DCC_READ 0x4503094 1 0>,
				<DCC_READ 0x450309c 1 0>,
				<DCC_READ 0x45030c4 2 0>,
				<DCC_READ 0x45033dc 1 0>,
				<DCC_READ 0x45035d8 1 0>,
				<DCC_READ 0x450402c 2 0>,
				<DCC_READ 0x4504094 1 0>,
				<DCC_READ 0x450409c 1 0>,
				<DCC_READ 0x45040c8 2 0>,
				<DCC_READ 0x45043dc 1 0>,
				<DCC_READ 0x45045d8 1 0>,
				<DCC_READ 0x450502c 2 0>,
				<DCC_READ 0x4505094 1 0>,
				<DCC_READ 0x450509c 1 0>,
				<DCC_READ 0x45050c4 2 0>,
				<DCC_READ 0x45053dc 1 0>,
				<DCC_READ 0x45055d8 1 0>,
				<DCC_READ 0x141102C 1 0>,
				<DCC_READ 0x1436004 1 0>,
				<DCC_READ 0x1471154 1 0>,
				<DCC_READ 0x141050C 1 0>,
				<DCC_READ 0x143600C 1 0>,
				<DCC_READ 0x1436018 1 0>,
				<DCC_READ 0x147C000 1 0>,
				<DCC_READ 0x147D000 1 0>,
				<DCC_READ 0x1436048 1 0>,
				<DCC_READ 0x1436040 1 0>,
				<DCC_READ 0x5991004 1 0>,
				<DCC_READ 0x599100c 1 0>,
				<DCC_READ 0x5991010 1 0>,
				<DCC_READ 0x5991014 1 0>,
				<DCC_READ 0x5991054 1 0>,
				<DCC_READ 0x5991060 1 0>,
				<DCC_READ 0x599106c 1 0>,
				<DCC_READ 0x5991070 1 0>,
				<DCC_READ 0x5991074 1 0>,
				<DCC_READ 0x5991078 1 0>,
				<DCC_READ 0x599107c 1 0>,
				<DCC_READ 0x599108c 1 0>,
				<DCC_READ 0x5991098 1 0>,
				<DCC_READ 0x599109c 1 0>,
				<DCC_READ 0x5991540 1 0>,
				<DCC_READ 0x5995000 1 0>,
				<DCC_READ 0x5995004 1 0>,
				<DCC_READ 0x599101C 1 0>,
				<DCC_READ 0x5991020 1 0>,
				<DCC_READ 0x5990000 1 0>,
				<DCC_READ 0x5990100 1 0>,
				<DCC_READ 0x5991508 1 0>,
				<DCC_READ 0x59910A4 1 0>,
				<DCC_READ 0x5991578 1 0>,
				<DCC_READ 0x5990010 1 0>,
				<DCC_READ 0x5990110 1 0>,
				<DCC_READ 0xf189000 1 0>,
				<DCC_READ 0xf18900c 1 0>,
				<DCC_READ 0xf189c0c 1 0>,
				<DCC_READ 0xf189c10 1 0>,
				<DCC_READ 0xf189c20 1 0>,
				<DCC_READ 0xf199000 1 0>,
				<DCC_READ 0xf19900c 1 0>,
				<DCC_READ 0xf199c0c 1 0>,
				<DCC_READ 0xf199c10 1 0>,
				<DCC_READ 0xf199c20 1 0>,
				<DCC_READ 0xf1a9000 1 0>,
				<DCC_READ 0xf1a900c 1 0>,
				<DCC_READ 0xf1a9c0c 1 0>,
				<DCC_READ 0xf1a9c10 1 0>,
				<DCC_READ 0xf1a9c20 1 0>,
				<DCC_READ 0xf1b9000 1 0>,
				<DCC_READ 0xf1b900c 1 0>,
				<DCC_READ 0xf1b9c0c 1 0>,
				<DCC_READ 0xf1b9c10 1 0>,
				<DCC_READ 0xf1b9c18 1 0>,
				<DCC_READ 0xf089000 1 0>,
				<DCC_READ 0xf08900c 1 0>,
				<DCC_READ 0xf089c0c 1 0>,
				<DCC_READ 0xf089c10 1 0>,
				<DCC_READ 0xf089c20 1 0>,
				<DCC_READ 0xf099000 1 0>,
				<DCC_READ 0xf09900c 1 0>,
				<DCC_READ 0xf099c0c 1 0>,
				<DCC_READ 0xf099c10 1 0>,
				<DCC_READ 0xf099c20 1 0>,
				<DCC_READ 0xf0a9000 1 0>,
				<DCC_READ 0xf0a900c 1 0>,
				<DCC_READ 0xf0a9c0c 1 0>,
				<DCC_READ 0xf0a9c10 1 0>,
				<DCC_READ 0xf0a9c20 1 0>,
				<DCC_READ 0xf0b9000 1 0>,
				<DCC_READ 0xf0b900c 1 0>,
				<DCC_READ 0xf0b9c0c 1 0>,
				<DCC_READ 0xf0b9c10 1 0>,
				<DCC_READ 0xf0b9c20 1 0>,
				<DCC_READ 0xf112000 1 0>,
				<DCC_READ 0xf11200c 1 0>,
				<DCC_READ 0xf112c0c 1 0>,
				<DCC_READ 0xf112c10 1 0>,
				<DCC_READ 0xf112c20 1 0>,
				<DCC_READ 0xf012000 1 0>,
				<DCC_READ 0xf01200c 1 0>,
				<DCC_READ 0xf012c0c 1 0>,
				<DCC_READ 0xf012c10 1 0>,
				<DCC_READ 0xf012c20 1 0>,
				<DCC_READ 0xf1d2000 1 0>,
				<DCC_READ 0xf1d200c 1 0>,
				<DCC_READ 0xf1d2c0c 1 0>,
				<DCC_READ 0xf1d2c10 1 0>,
				<DCC_READ 0xf1d2c20 1 0>,
				<DCC_READ 0xf011014 1 0>,
				<DCC_READ 0xf011018 1 0>,
				<DCC_READ 0xf011218 1 0>,
				<DCC_READ 0xf011234 1 0>,
				<DCC_READ 0xf011220 1 0>,
				<DCC_READ 0xf011264 1 0>,
				<DCC_READ 0xf011290 1 0>,
				<DCC_READ 0xf111014 1 0>,
				<DCC_READ 0xf111018 1 0>,
				<DCC_READ 0xf111218 1 0>,
				<DCC_READ 0xf111234 1 0>,
				<DCC_READ 0xf111264 1 0>,
				<DCC_READ 0xf111290 1 0>,
				<DCC_READ 0x0F521700 1 0>,
				<DCC_READ 0x0F523700 1 0>,
				<DCC_READ 0x0F112C18 1 0>,
				<DCC_READ 0x0F012C18 1 0>,
				<DCC_READ 0x0F513A84 1 0>,
				<DCC_READ 0x0F513A88 1 0>,
				<DCC_READ 0x01B60110 1 0>,
				<DCC_READ 0x1900010 1 0>,
				<DCC_READ 0x1900020 1 0>,
				<DCC_READ 0x1900024 1 0>,
				<DCC_READ 0x1900028 1 0>,
				<DCC_READ 0x190002C 1 0>,
				<DCC_READ 0x1900030 1 0>,
				<DCC_READ 0x1900034 1 0>,
				<DCC_READ 0x1900038 1 0>,
				<DCC_READ 0x190003C 1 0>,
				<DCC_READ 0x1900300 1 0>,
				<DCC_READ 0x1900304 1 0>,
				<DCC_READ 0x1900308 1 0>,
				<DCC_READ 0x190030C 1 0>,
				<DCC_READ 0x1900310 1 0>,
				<DCC_READ 0x1900314 1 0>,
				<DCC_READ 0x1900900 1 0>,
				<DCC_READ 0x1900904 1 0>,
				<DCC_READ 0x1900B00 1 0>,
				<DCC_READ 0x1900D00 1 0>,
				<DCC_READ 0x1909100 1 0>,
				<DCC_READ 0x1909104 1 0>,
				<DCC_READ 0x1480140 1 0>,
				<DCC_READ 0x1481140 1 0>,
				<DCC_READ 0x1415008 1 0>,
				<DCC_READ 0x1416008 1 0>,
				<DCC_READ 0x44B0120 1 0>,
				<DCC_READ 0x44B0124 1 0>,
				<DCC_READ 0x44B0128 1 0>,
				<DCC_READ 0x44B012C 1 0>,
				<DCC_READ 0x44B0130 1 0>,
				<DCC_READ 0x44B0100 1 0>,
				<DCC_READ 0x44B0020 1 0>,
				<DCC_READ 0x44C4000 1 0>,
				<DCC_READ 0x44C4020 1 0>,
				<DCC_READ 0x44C4030 1 0>,
				<DCC_READ 0x44C4100 1 0>,
				<DCC_READ 0x44C410C 1 0>,
				<DCC_READ 0x44C4400 1 0>,
				<DCC_READ 0x44C4410 1 0>,
				<DCC_READ 0x44C4420 1 0>,
				<DCC_READ 0x1900240 1 0>,
				<DCC_READ 0x1900244 1 0>,
				<DCC_READ 0x1900248 1 0>,
				<DCC_READ 0x190024C 1 0>,
				<DCC_READ 0x1900250 1 0>,
				<DCC_READ 0x1900258 1 0>,
				<DCC_READ 0x1411004 1 0>,
				<DCC_READ 0x1411028 1 0>,
				<DCC_READ 0x1458004 1 0>,
				<DCC_READ 0x1880108 1 0>,
				<DCC_READ 0x1880110 1 0>,
				<DCC_READ 0x1880120 1 0>,
				<DCC_READ 0x1880124 1 0>,
				<DCC_READ 0x1880128 1 0>,
				<DCC_READ 0x188012C 1 0>,
				<DCC_READ 0x1880130 1 0>,
				<DCC_READ 0x1880134 1 0>,
				<DCC_READ 0x1880138 1 0>,
				<DCC_READ 0x188013C 1 0>,
				<DCC_READ 0x1880300 1 0>,
				<DCC_READ 0x1880304 1 0>,
				<DCC_READ 0x1880308 1 0>,
				<DCC_READ 0x188030C 1 0>,
				<DCC_READ 0x1880310 1 0>,
				<DCC_READ 0x1880314 1 0>,
				<DCC_READ 0x1880318 1 0>,
				<DCC_READ 0x188031C 1 0>,
				<DCC_READ 0x1880700 1 0>,
				<DCC_READ 0x1880704 1 0>,
				<DCC_READ 0x1880708 1 0>,
				<DCC_READ 0x188070C 1 0>,
				<DCC_READ 0x1880710 1 0>,
				<DCC_READ 0x1880714 1 0>,
				<DCC_READ 0x1880718 1 0>,
				<DCC_READ 0x188071C 1 0>,
				<DCC_READ 0x1881100 1 0>,
				<DCC_READ 0x1880240 1 0>,
				<DCC_READ 0x1880248 1 0>,
				<DCC_READ 0xF017000 1 0>,
				<DCC_READ 0xF01700C 1 0>,
				<DCC_READ 0xF017010 1 0>,
				<DCC_READ 0xF017014 1 0>,
				<DCC_READ 0xF017018 1 0>,
				<DCC_READ 0xF017020 1 0>,
				<DCC_READ 0x1414008 1 0>,
				<DCC_READ 0x1414004 1 0>,
				<DCC_READ 0x5991554 1 0>,
				<DCC_READ 0x5991544 1 0>,
				<DCC_READ 0x599155C 1 0>,
				<DCC_READ 0x440B00C 1 0>,
				<DCC_READ 0x440B014 1 0>,
				<DCC_READ 0x0F522C14 1 0>,
				<DCC_READ 0x0F522C1C 1 0>,
				<DCC_READ 0x0F522C10 1 0>,
				<DCC_READ 0x0F524C10 1 0>,
				<DCC_READ 0x0F524C14 1 0>,
				<DCC_READ 0x0F524C18 1 0>,
				<DCC_READ 0x0F524C1C 1 0>,
				<DCC_READ 0x0F521920 1 0>,
				<DCC_READ 0x0F52102C 1 0>,
				<DCC_READ 0x0F521044 1 0>,
				<DCC_READ 0x0F521710 1 0>,
				<DCC_READ 0x0F52176C 1 0>,
				<DCC_READ 0x0F523920 1 0>,
				<DCC_READ 0x0F52302C 1 0>,
				<DCC_READ 0x0F523044 1 0>,
				<DCC_READ 0x0F523710 1 0>,
				<DCC_READ 0x0F52376C 1 0>,
				<DCC_READ 0x0F116000 1 0>,
				<DCC_READ 0x0F116004 1 0>,
				<DCC_READ 0x0F11602C 1 0>,
				<DCC_READ 0x0F016000 1 0>,
				<DCC_READ 0x0F016004 1 0>,
				<DCC_READ 0x0F01602C 1 0>,
				<DCC_READ 0x0F111250 1 0>,
				<DCC_READ 0x0F111254 1 0>,
				<DCC_READ 0x0F111258 1 0>,
				<DCC_READ 0x0F11125C 1 0>,
				<DCC_READ 0x0F111260 1 0>,
				<DCC_READ 0x0F188078 1 0>,
				<DCC_READ 0x0F188084 1 0>,
				<DCC_READ 0x0F198078 1 0>,
				<DCC_READ 0x0F198084 1 0>,
				<DCC_READ 0x0F1A8078 1 0>,
				<DCC_READ 0x0F1A8084 1 0>,
				<DCC_READ 0x0F1B8078 1 0>,
				<DCC_READ 0x0F1B8084 1 0>,
				<DCC_READ 0x0F521818 1 0>,
				<DCC_READ 0x0F52181C 1 0>,
				<DCC_READ 0x0F521828 1 0>,
				<DCC_READ 0x0F523818 1 0>,
				<DCC_READ 0x0F52381C 1 0>,
				<DCC_READ 0x0F523828 1 0>,
				<DCC_READ 0x0F522C18 1 0>,
				<DCC_READ 0x0F111310 1 0>,
				<DCC_READ 0x0F111314 1 0>,
				<DCC_READ 0x0F111318 1 0>,
				<DCC_READ 0x0F01125C 1 0>,
				<DCC_READ 0x0F011258 1 0>,
				<DCC_READ 0x0F011310 1 0>,
				<DCC_READ 0x0F011314 1 0>,
				<DCC_READ 0x0F011318 1 0>,
				<DCC_WRITE 0x9870010 0x14000 0>,
				<DCC_READ 0xF011600 1 0>,
				<DCC_READ 0xF011608 1 0>,
				<DCC_READ 0xF01160C 1 0>,
				<DCC_READ 0xF011610 1 0>,
				<DCC_READ 0xF011614 1 0>,
				<DCC_READ 0xF011618 1 0>,
				<DCC_READ 0xF01161C 1 0>,
				<DCC_READ 0xF011620 1 0>,
				<DCC_READ 0xF011624 1 0>,
				<DCC_READ 0xF011628 1 0>,
				<DCC_READ 0xF01162C 1 0>,
				<DCC_READ 0xF011630 1 0>,
				<DCC_READ 0xF011634 1 0>,
				<DCC_READ 0xF011638 1 0>,
				<DCC_READ 0xF01163C 1 0>,
				<DCC_READ 0xF011640 1 0>,
				<DCC_READ 0xF011644 1 0>,
				<DCC_READ 0xF011648 1 0>,
				<DCC_READ 0xF01164C 1 0>,
				<DCC_READ 0xF011650 1 0>,
				<DCC_READ 0xF011654 1 0>,
				<DCC_READ 0xF011658 1 0>,
				<DCC_READ 0xF01165C 1 0>,
				<DCC_READ 0xF011664 1 0>,
				<DCC_READ 0xF111600 1 0>,
				<DCC_READ 0xF111608 1 0>,
				<DCC_READ 0xF11160C 1 0>,
				<DCC_READ 0xF111610 1 0>,
				<DCC_READ 0xF111614 1 0>,
				<DCC_READ 0xF111618 1 0>,
				<DCC_READ 0xF11161C 1 0>,
				<DCC_READ 0xF111620 1 0>,
				<DCC_READ 0xF111624 1 0>,
				<DCC_READ 0xF111628 1 0>,
				<DCC_READ 0xF11162C 1 0>,
				<DCC_READ 0xF111630 1 0>,
				<DCC_READ 0xF111634 1 0>,
				<DCC_READ 0xF111638 1 0>,
				<DCC_READ 0xF11163C 1 0>,
				<DCC_READ 0xF111640 1 0>,
				<DCC_READ 0xF111644 1 0>,
				<DCC_READ 0xF111648 1 0>,
				<DCC_READ 0xF111650 1 0>,
				<DCC_READ 0xF111654 1 0>,
				<DCC_READ 0xF111658 1 0>,
				<DCC_READ 0xF11165C 1 0>,
				<DCC_READ 0xF111664 1 0>,
				<DCC_READ 0xF011400 1 0>,
				<DCC_READ 0xF111400 1 0>,
				<DCC_WRITE 0x9870010 0x0 0>,
				<DCC_READ 0x06130010 1 0>,
				<DCC_READ 0x06130014 1 0>,
				<DCC_READ 0x06130018 1 0>,
				<DCC_READ 0x06130210 1 0>,
				<DCC_READ 0x06130230 1 0>,
				<DCC_READ 0x06130250 1 0>,
				<DCC_READ 0x06130270 1 0>,
				<DCC_READ 0x06130290 1 0>,
				<DCC_READ 0x061302B0 1 0>,
				<DCC_READ 0x06130208 1 0>,
				<DCC_READ 0x06130228 1 0>,
				<DCC_READ 0x06130248 1 0>,
				<DCC_READ 0x06130268 1 0>,
				<DCC_READ 0x06130288 1 0>,
				<DCC_READ 0x061302A8 1 0>,
				<DCC_READ 0x0613020C 1 0>,
				<DCC_READ 0x0613022C 1 0>,
				<DCC_READ 0x0613024C 1 0>,
				<DCC_READ 0x0613026C 1 0>,
				<DCC_READ 0x0613028C 1 0>,
				<DCC_READ 0x061302AC 1 0>,
				<DCC_READ 0x06130400 1 0>,
				<DCC_READ 0x06130404 1 0>,
				<DCC_READ 0x06130408 1 0>,
				<DCC_READ 0x6082028  1 0>,
				<DCC_READ 0x0143300C 1 0>,
				<DCC_READ 0x0B3B0010 1 0>,
				<DCC_READ 0x0B3B0014 1 0>,
				<DCC_READ 0x0B3B0018 1 0>,
				<DCC_READ 0x0B3B0210 1 0>,
				<DCC_READ 0x0B3B0230 1 0>,
				<DCC_READ 0x0B3B0250 1 0>,
				<DCC_READ 0x0B3B0270 1 0>,
				<DCC_READ 0x0B3B0290 1 0>,
				<DCC_READ 0x0B3B02B0 1 0>,
				<DCC_READ 0x0B3B0208 1 0>,
				<DCC_READ 0x0B3B0228 1 0>,
				<DCC_READ 0x0B3B0248 1 0>,
				<DCC_READ 0x0B3B0268 1 0>,
				<DCC_READ 0x0B3B0288 1 0>,
				<DCC_READ 0x0B3B02A8 1 0>,
				<DCC_READ 0x0B3B020C 1 0>,
				<DCC_READ 0x0B3B022C 1 0>,
				<DCC_READ 0x0B3B024C 1 0>,
				<DCC_READ 0x0B3B026C 1 0>,
				<DCC_READ 0x0B3B028C 1 0>,
				<DCC_READ 0x0B3B02AC 1 0>,
				<DCC_READ 0x0B3B0400 1 0>,
				<DCC_READ 0x0B3B0404 1 0>,
				<DCC_READ 0x0B3B0408 1 0>,
				<DCC_READ 0x0B302028 1 0>,
				<DCC_READ 0x0B300044 1 0>,
				<DCC_READ 0x0B300304 1 0>,
				<DCC_READ 0x5C6F000 1 0>,
				<DCC_READ 0x5C42000 1 0>,
				<DCC_READ 0x5C42400 1 0>,
				<DCC_READ 0x5C23000 1 0>;
		};

		link_list2 {
			qcom,curr-link-list = <2>;
			qcom,data-sink = "sram";
			qcom,link-list = <DCC_READ 0x01480140 1 0>,
				<DCC_READ 0x01481140 1 0>,
				<DCC_READ 0x0148014C 1 0>,
				<DCC_READ 0x0148114C 1 0>,
				<DCC_READ 0x01477008 1 0>,
				<DCC_READ 0x01439000 1 0>,
				<DCC_READ 0x01415010 1 0>,
				<DCC_READ 0x01416010 1 0>,
				<DCC_READ 0x0142A00C 1 0>,
				<DCC_READ 0x1400000 1 0>,
				<DCC_READ 0x1400004 1 0>,
				<DCC_READ 0x1400008 1 0>,
				<DCC_READ 0x140000C 1 0>,
				<DCC_READ 0x1400010 1 0>,
				<DCC_READ 0x1400014 1 0>,
				<DCC_READ 0x1400018 1 0>,
				<DCC_READ 0x140001C 1 0>,
				<DCC_READ 0x1400020 1 0>,
				<DCC_READ 0x1400024 1 0>,
				<DCC_READ 0x1401000 1 0>,
				<DCC_READ 0x1401004 1 0>,
				<DCC_READ 0x1401008 1 0>,
				<DCC_READ 0x140100C 1 0>,
				<DCC_READ 0x1401010 1 0>,
				<DCC_READ 0x1401014 1 0>,
				<DCC_READ 0x1401018 1 0>,
				<DCC_READ 0x140101C 1 0>,
				<DCC_READ 0x1401020 1 0>,
				<DCC_READ 0x1401024 1 0>,
				<DCC_READ 0x1402000 1 0>,
				<DCC_READ 0x1402004 1 0>,
				<DCC_READ 0x1402008 1 0>,
				<DCC_READ 0x140200C 1 0>,
				<DCC_READ 0x1402010 1 0>,
				<DCC_READ 0x1402014 1 0>,
				<DCC_READ 0x1402018 1 0>,
				<DCC_READ 0x140201C 1 0>,
				<DCC_READ 0x1402020 1 0>,
				<DCC_READ 0x1402024 1 0>,
				<DCC_READ 0x1403000 1 0>,
				<DCC_READ 0x1403004 1 0>,
				<DCC_READ 0x1403008 1 0>,
				<DCC_READ 0x140300C 1 0>,
				<DCC_READ 0x1403010 1 0>,
				<DCC_READ 0x1403014 1 0>,
				<DCC_READ 0x1403018 1 0>,
				<DCC_READ 0x140301C 1 0>,
				<DCC_READ 0x1403020 1 0>,
				<DCC_READ 0x1403024 1 0>,
				<DCC_READ 0x1404000 1 0>,
				<DCC_READ 0x1404004 1 0>,
				<DCC_READ 0x1404008 1 0>,
				<DCC_READ 0x140400C 1 0>,
				<DCC_READ 0x1404010 1 0>,
				<DCC_READ 0x1404014 1 0>,
				<DCC_READ 0x1404018 1 0>,
				<DCC_READ 0x140401C 1 0>,
				<DCC_READ 0x1404020 1 0>,
				<DCC_READ 0x1404024 1 0>,
				<DCC_READ 0x1405000 1 0>,
				<DCC_READ 0x1405004 1 0>,
				<DCC_READ 0x1405008 1 0>,
				<DCC_READ 0x140500C 1 0>,
				<DCC_READ 0x1405010 1 0>,
				<DCC_READ 0x1405014 1 0>,
				<DCC_READ 0x1405018 1 0>,
				<DCC_READ 0x140501C 1 0>,
				<DCC_READ 0x1405020 1 0>,
				<DCC_READ 0x1405024 1 0>,
				<DCC_READ 0x1406000 1 0>,
				<DCC_READ 0x1406004 1 0>,
				<DCC_READ 0x1406008 1 0>,
				<DCC_READ 0x140600C 1 0>,
				<DCC_READ 0x1406010 1 0>,
				<DCC_READ 0x1406014 1 0>,
				<DCC_READ 0x1406018 1 0>,
				<DCC_READ 0x140601C 1 0>,
				<DCC_READ 0x1406020 1 0>,
				<DCC_READ 0x1406024 1 0>,
				<DCC_READ 0x1407000 1 0>,
				<DCC_READ 0x1407004 1 0>,
				<DCC_READ 0x1407008 1 0>,
				<DCC_READ 0x140700C 1 0>,
				<DCC_READ 0x1407010 1 0>,
				<DCC_READ 0x1407014 1 0>,
				<DCC_READ 0x1407018 1 0>,
				<DCC_READ 0x140701C 1 0>,
				<DCC_READ 0x1407020 1 0>,
				<DCC_READ 0x1407024 1 0>,
				<DCC_READ 0x1407028 1 0>,
				<DCC_READ 0x140702C 1 0>,
				<DCC_READ 0x1407030 1 0>,
				<DCC_READ 0x1407034 1 0>,
				<DCC_READ 0x1408000 1 0>,
				<DCC_READ 0x1408004 1 0>,
				<DCC_READ 0x1408008 1 0>,
				<DCC_READ 0x140800C 1 0>,
				<DCC_READ 0x1408010 1 0>,
				<DCC_READ 0x1408014 1 0>,
				<DCC_READ 0x1408018 1 0>,
				<DCC_READ 0x140801C 1 0>,
				<DCC_READ 0x1408020 1 0>,
				<DCC_READ 0x1408024 1 0>,
				<DCC_READ 0x1409000 1 0>,
				<DCC_READ 0x1409004 1 0>,
				<DCC_READ 0x1409008 1 0>,
				<DCC_READ 0x140900C 1 0>,
				<DCC_READ 0x1409010 1 0>,
				<DCC_READ 0x1409014 1 0>,
				<DCC_READ 0x1409018 1 0>,
				<DCC_READ 0x140901C 1 0>,
				<DCC_READ 0x1409020 1 0>,
				<DCC_READ 0x1409024 1 0>,
				<DCC_READ 0x141001C 1 0>,
				<DCC_READ 0x14103EC 1 0>,
				<DCC_READ 0x1414024 1 0>,
				<DCC_READ 0x1415004 1 0>,
				<DCC_READ 0x1415008 1 0>,
				<DCC_READ 0x141500C 1 0>,
				<DCC_READ 0x1415034 1 0>,
				<DCC_READ 0x1416004 1 0>,
				<DCC_READ 0x1416008 1 0>,
				<DCC_READ 0x141600C 1 0>,
				<DCC_READ 0x1416038 1 0>,
				<DCC_READ 0x141703C 1 0>,
				<DCC_READ 0x1417040 1 0>,
				<DCC_READ 0x141A004 1 0>,
				<DCC_READ 0x141A008 1 0>,
				<DCC_READ 0x141A00C 1 0>,
				<DCC_READ 0x141A01C 1 0>,
				<DCC_READ 0x141A020 1 0>,
				<DCC_READ 0x141A034 1 0>,
				<DCC_READ 0x141A038 1 0>,
				<DCC_READ 0x141A060 1 0>,
				<DCC_READ 0x141A064 1 0>,
				<DCC_READ 0x141E00C 1 0>,
				<DCC_READ 0x141E010 1 0>,
				<DCC_READ 0x141F02C 1 0>,
				<DCC_READ 0x141F148 1 0>,
				<DCC_READ 0x141F14C 1 0>,
				<DCC_READ 0x141F15C 1 0>,
				<DCC_READ 0x141F278 1 0>,
				<DCC_READ 0x141F27C 1 0>,
				<DCC_READ 0x141F28C 1 0>,
				<DCC_READ 0x141F3A8 1 0>,
				<DCC_READ 0x141F3AC 1 0>,
				<DCC_READ 0x141F3BC 1 0>,
				<DCC_READ 0x141F4D8 1 0>,
				<DCC_READ 0x141F4DC 1 0>,
				<DCC_READ 0x141F4EC 1 0>,
				<DCC_READ 0x141F608 1 0>,
				<DCC_READ 0x141F60C 1 0>,
				<DCC_READ 0x141F61C 1 0>,
				<DCC_READ 0x141F738 1 0>,
				<DCC_READ 0x141F73C 1 0>,
				<DCC_READ 0x141F74C 1 0>,
				<DCC_READ 0x1420010 1 0>,
				<DCC_READ 0x1420014 1 0>,
				<DCC_READ 0x1426018 1 0>,
				<DCC_READ 0x142601C 1 0>,
				<DCC_READ 0x1426030 1 0>,
				<DCC_READ 0x1426034 1 0>,
				<DCC_READ 0x1427024 1 0>,
				<DCC_READ 0x1428014 1 0>,
				<DCC_READ 0x1428018 1 0>,
				<DCC_READ 0x142802C 1 0>,
				<DCC_READ 0x1428030 1 0>,
				<DCC_READ 0x1429004 1 0>,
				<DCC_READ 0x1429008 1 0>,
				<DCC_READ 0x142900C 1 0>,
				<DCC_READ 0x1429040 1 0>,
				<DCC_READ 0x1429044 1 0>,
				<DCC_READ 0x142A000 1 0>,
				<DCC_READ 0x142A004 1 0>,
				<DCC_READ 0x142A008 1 0>,
				<DCC_READ 0x142A154 1 0>,
				<DCC_READ 0x142A158 1 0>,
				<DCC_READ 0x142B13C 1 0>,
				<DCC_READ 0x142B140 1 0>,
				<DCC_READ 0x142B158 1 0>,
				<DCC_READ 0x142B15C 1 0>,
				<DCC_READ 0x142E00C 1 0>,
				<DCC_READ 0x142E010 1 0>,
				<DCC_READ 0x142F00C 1 0>,
				<DCC_READ 0x142F010 1 0>,
				<DCC_READ 0x1432004 1 0>,
				<DCC_READ 0x1432008 1 0>,
				<DCC_READ 0x143200C 1 0>,
				<DCC_READ 0x1432034 1 0>,
				<DCC_READ 0x1432080 1 0>,
				<DCC_READ 0x1438010 1 0>,
				<DCC_READ 0x1438014 1 0>,
				<DCC_READ 0x1438028 1 0>,
				<DCC_READ 0x143802C 1 0>,
				<DCC_READ 0x143B000 1 0>,
				<DCC_READ 0x143B004 1 0>,
				<DCC_READ 0x143B008 1 0>,
				<DCC_READ 0x143B00C 1 0>,
				<DCC_READ 0x143B010 1 0>,
				<DCC_READ 0x143B014 1 0>,
				<DCC_READ 0x143B018 1 0>,
				<DCC_READ 0x143B01C 1 0>,
				<DCC_READ 0x143B020 1 0>,
				<DCC_READ 0x143B024 1 0>,
				<DCC_READ 0x143D01C 1 0>,
				<DCC_READ 0x143D020 1 0>,
				<DCC_READ 0x143E000 1 0>,
				<DCC_READ 0x143E004 1 0>,
				<DCC_READ 0x143E008 1 0>,
				<DCC_READ 0x143E00C 1 0>,
				<DCC_READ 0x143E010 1 0>,
				<DCC_READ 0x143E014 1 0>,
				<DCC_READ 0x143E018 1 0>,
				<DCC_READ 0x143E01C 1 0>,
				<DCC_READ 0x143E020 1 0>,
				<DCC_READ 0x143E024 1 0>,
				<DCC_READ 0x143E060 1 0>,
				<DCC_READ 0x143F000 1 0>,
				<DCC_READ 0x143F004 1 0>,
				<DCC_READ 0x143F008 1 0>,
				<DCC_READ 0x143F00C 1 0>,
				<DCC_READ 0x143F010 1 0>,
				<DCC_READ 0x143F014 1 0>,
				<DCC_READ 0x143F018 1 0>,
				<DCC_READ 0x143F01C 1 0>,
				<DCC_READ 0x143F020 1 0>,
				<DCC_READ 0x143F024 1 0>,
				<DCC_READ 0x1442018 1 0>,
				<DCC_READ 0x144201C 1 0>,
				<DCC_READ 0x1442030 1 0>,
				<DCC_READ 0x1442034 1 0>,
				<DCC_READ 0x1445004 1 0>,
				<DCC_READ 0x1445008 1 0>,
				<DCC_READ 0x144500C 1 0>,
				<DCC_READ 0x1445020 1 0>,
				<DCC_READ 0x1445024 1 0>,
				<DCC_READ 0x1445048 1 0>,
				<DCC_READ 0x144504C 1 0>,
				<DCC_READ 0x1445060 1 0>,
				<DCC_READ 0x1445064 1 0>,
				<DCC_READ 0x144507C 1 0>,
				<DCC_READ 0x1445080 1 0>,
				<DCC_READ 0x1446004 1 0>,
				<DCC_READ 0x1446008 1 0>,
				<DCC_READ 0x1446024 1 0>,
				<DCC_READ 0x1446150 1 0>,
				<DCC_READ 0x1448024 1 0>,
				<DCC_READ 0x144D004 1 0>,
				<DCC_READ 0x144D008 1 0>,
				<DCC_READ 0x144E004 1 0>,
				<DCC_READ 0x144E008 1 0>,
				<DCC_READ 0x144F004 1 0>,
				<DCC_READ 0x144F008 1 0>,
				<DCC_READ 0x1451000 1 0>,
				<DCC_READ 0x1451004 1 0>,
				<DCC_READ 0x145101C 1 0>,
				<DCC_READ 0x1451020 1 0>,
				<DCC_READ 0x1451038 1 0>,
				<DCC_READ 0x145103C 1 0>,
				<DCC_READ 0x1451054 1 0>,
				<DCC_READ 0x1451058 1 0>,
				<DCC_READ 0x1452004 1 0>,
				<DCC_READ 0x1452008 1 0>,
				<DCC_READ 0x1452028 1 0>,
				<DCC_READ 0x145202C 1 0>,
				<DCC_READ 0x1454004 1 0>,
				<DCC_READ 0x1455000 1 0>,
				<DCC_READ 0x1455004 1 0>,
				<DCC_READ 0x1457000 1 0>,
				<DCC_READ 0x1457004 1 0>,
				<DCC_READ 0x1457008 1 0>,
				<DCC_READ 0x145700C 1 0>,
				<DCC_READ 0x1457010 1 0>,
				<DCC_READ 0x145A000 1 0>,
				<DCC_READ 0x145A004 1 0>,
				<DCC_READ 0x145A008 1 0>,
				<DCC_READ 0x145A00C 1 0>,
				<DCC_READ 0x145A010 1 0>,
				<DCC_READ 0x145B000 1 0>,
				<DCC_READ 0x145B004 1 0>,
				<DCC_READ 0x145B00C 1 0>,
				<DCC_READ 0x1463020 1 0>,
				<DCC_READ 0x1469000 1 0>,
				<DCC_READ 0x1469004 1 0>,
				<DCC_READ 0x1469008 1 0>,
				<DCC_READ 0x146900C 1 0>,
				<DCC_READ 0x1469010 1 0>,
				<DCC_READ 0x146B000 1 0>,
				<DCC_READ 0x146B004 1 0>,
				<DCC_READ 0x146B008 1 0>,
				<DCC_READ 0x146B00C 1 0>,
				<DCC_READ 0x146B010 1 0>,
				<DCC_READ 0x146B014 1 0>,
				<DCC_READ 0x146B018 1 0>,
				<DCC_READ 0x146B01C 1 0>,
				<DCC_READ 0x146B020 1 0>,
				<DCC_READ 0x146C000 1 0>,
				<DCC_READ 0x146C004 1 0>,
				<DCC_READ 0x146C00C 1 0>,
				<DCC_READ 0x1475000 1 0>,
				<DCC_READ 0x1475004 1 0>,
				<DCC_READ 0x147500C 1 0>,
				<DCC_READ 0x1477000 1 0>,
				<DCC_READ 0x1477004 1 0>,
				<DCC_READ 0x147700C 1 0>,
				<DCC_READ 0x1478030 1 0>,
				<DCC_READ 0x1479000 1 0>,
				<DCC_READ 0x1479004 1 0>,
				<DCC_READ 0x147900C 1 0>,
				<DCC_READ 0x147A000 1 0>,
				<DCC_READ 0x147A004 1 0>,
				<DCC_READ 0x147A00C 1 0>,
				<DCC_READ 0x1480018 1 0>,
				<DCC_READ 0x1480144 1 0>,
				<DCC_READ 0x1481144 1 0>,
				<DCC_READ 0x148B004 1 0>,
				<DCC_READ 0x1490004 1 0>,
				<DCC_READ 0x1490008 1 0>,
				<DCC_READ 0x1490024 1 0>,
				<DCC_READ 0x1490028 1 0>,
				<DCC_READ 0x149002C 1 0>,
				<DCC_READ 0x1490034 1 0>,
				<DCC_READ 0x1495000 1 0>,
				<DCC_READ 0x1495004 1 0>,
				<DCC_READ 0x149500C 1 0>,
				<DCC_READ 0x14B5000 1 0>,
				<DCC_READ 0x14C4000 1 0>,
				<DCC_READ 0x14C5000 1 0>,
				<DCC_READ 0x14C6000 1 0>,
				<DCC_READ 0x14C7000 1 0>,
				<DCC_READ 0x440C000 1 0>,
				<DCC_READ 0x440C004 1 0>,
				<DCC_READ 0x440C008 1 0>,
				<DCC_READ 0x440C040 1 0>,
				<DCC_READ 0x440C044 1 0>,
				<DCC_READ 0x440C048 1 0>,
				<DCC_READ 0x440C04C 1 0>,
				<DCC_READ 0x440C050 1 0>,
				<DCC_READ 0x440C054 1 0>,
				<DCC_READ 0x440C058 1 0>,
				<DCC_READ 0x440C05C 1 0>,
				<DCC_READ 0x440C060 1 0>,
				<DCC_READ 0x440C068 1 0>,
				<DCC_READ 0x440C06C 1 0>,
				<DCC_READ 0x440E050 1 0>,
				<DCC_READ 0x440E054 1 0>,
				<DCC_READ 0x440E0A0 1 0>,
				<DCC_READ 0x440E0A4 1 0>,
				<DCC_READ 0x440F010 1 0>;
		};
	};

	timer@f120000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0xf120000 0x1000>;
		clock-frequency = <19200000>;

		frame@f121000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 7 0x4>;
			reg = <0xf121000 0x1000>,
			      <0xf122000 0x1000>;
		};

		frame@f123000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0xf123000 0x1000>;
			status = "disabled";
		};

		frame@f124000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0xf124000 0x1000>;
			status = "disabled";
		};

		frame@f125000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0xf125000 0x1000>;
			status = "disabled";
		};

		frame@f126000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0xf126000 0x1000>;
			status = "disabled";
		};

		frame@f127000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0xf127000 0x1000>;
			status = "disabled";
		};

		frame@f128000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0xf128000 0x1000>;
			status = "disabled";
		};
	};

	arm64_cpu_erp {
		compatible = "arm,arm64-cpu-erp";
		interrupt-names = "pri-dbe-irq",
				  "sec-dbe-irq",
				  "pri-ext-irq",
				  "sec-ext-irq";
		interrupts = <0 43 4>,
			     <0 44 4>,
			     <0 41 4>,
			     <0 42 4>;
		poll-delay-ms = <5000>;
	};

	l2cache_pmu {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "qcom,l2cache-pmu";
		ranges;

		cluster0@f111000 {
			cluster-id = <0>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xf111000 0x1000>;
		};

		cluster1@f011000 {
			cluster-id = <1>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xf011000 0x1000>;
		};
	};

	qcom,msm-imem@c125000 {
		compatible = "qcom,msm-imem";
		reg = <0xc125000 0x1000>;
		ranges = <0x0 0xc125000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 0xc8>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	restart@440b000 {
		compatible = "qcom,pshold";
		reg = <0x440b000 0x4>,
		      <0x03d3000 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom_seecom: qseecom@61800000 {
		compatible = "qcom,qseecom";
		reg = <0x61800000 0x2100000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,support-fde;
		qcom,fde-key-size;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,msm-bus,name = "qseecom-noc";
		qcom,msm-bus,num-cases = <4>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST 0 0>,
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST 200000 400000>,
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST 300000 800000>,
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST 400000 1000000>;
		clock-names =
			"core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		clocks =
			<&rpmcc QSEECOM_CE1_CLK>,
			<&rpmcc QSEECOM_CE1_CLK>,
			<&rpmcc QSEECOM_CE1_CLK>,
			<&rpmcc QSEECOM_CE1_CLK>;
		qcom,ce-opp-freq = <192000000>;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_smcinvoke: smcinvoke@61800000 {
		compatible = "qcom,smcinvoke";
		reg = <0x61800000 0x2100000>;
		reg-names = "secapp-region";
	};

	qcom_rng: qrng@1b53000 {
		compatible = "qcom,msm-rng";
		reg = <0x1b53000 0x1000>;
		qcom,msm-rng-iface-clk;
		qcom,no-qrng-config;
		qcom,msm-bus,name = "msm-rng-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<MSM_BUS_MASTER_AMPSS_M0
			MSM_BUS_SLAVE_PRNG 0 0>,    /* No vote */
			<MSM_BUS_MASTER_AMPSS_M0
			MSM_BUS_SLAVE_PRNG 0 300000>;  /* 75 MHz */
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
		clock-names = "iface_clk";
	};

	qcom_tzlog: tz-log@c125720 {
		compatible = "qcom,tz-log";
		reg = <0xc125720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	qcom_cedev: qcedev@1b20000 {
		compatible = "qcom,qcedev";
		reg = <0x1b20000 0x20000>,
			<0x1b04000 0x24000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <3>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,bam-ee = <0>;
		qcom,msm-bus,name = "qcedev-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<MSM_BUS_MASTER_CRYPTO_CORE0
				MSM_BUS_SLAVE_FIRST 0 0>,
				<MSM_BUS_MASTER_CRYPTO_CORE0
				MSM_BUS_SLAVE_FIRST 393600 393600>;
		clock-names =
			"core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		clocks =
			<&rpmcc QCEDEV_CE1_CLK>,
			<&rpmcc QCEDEV_CE1_CLK>,
			<&rpmcc QCEDEV_CE1_CLK>,
			<&rpmcc QCEDEV_CE1_CLK>;
		qcom,ce-opp-freq = <192000000>;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x0086 0x0011>,
			 <&apps_smmu 0x0096 0x0011>;
		qcom,iommu-dma = "atomic";

		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x92 0>,
				<&apps_smmu 0x98 0x1>,
				<&apps_smmu 0x9F 0>;
			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
		};

		qcom_cedev_s_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "secure_context";
			iommus = <&apps_smmu 0x93 0>,
				<&apps_smmu 0x9C 0x1>,
				<&apps_smmu 0x9E 0>;
			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
			qcom,secure-context-bank;
		};
	};

	qcom_crypto: qcrypto@1b20000 {
		compatible = "qcom,qcrypto";
		reg = <0x1b20000 0x20000>,
			<0x1b04000 0x24000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,bam-ee = <0>;
		qcom,ce-hw-shared;
		qcom,clk-mgmt-sus-res;
		qcom,msm-bus,name = "qcrypto-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST
			0 0>,
			<MSM_BUS_MASTER_CRYPTO_CORE0
			MSM_BUS_SLAVE_FIRST
			393600 393600>;
		clock-names =
			"core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		clocks =
			<&rpmcc QCRYPTO_CE1_CLK>,
			<&rpmcc QCRYPTO_CE1_CLK>,
			<&rpmcc QCRYPTO_CE1_CLK>,
			<&rpmcc QCRYPTO_CE1_CLK>;
		qcom,use-sw-aes-cbc-ecb-ctr-algo;
		qcom,use-sw-aes-xts-algo;
		qcom,use-sw-aes-ccm-algo;
		qcom,use-sw-ahash-algo;
		qcom,use-sw-aead-algo;
		qcom,use-sw-hmac-algo;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x0084 0x0011>,
			<&apps_smmu 0x0094 0x0011>;
		qcom,iommu-dma = "atomic";
	};

	qcom,mpm2-sleep-counter@4403000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0x4403000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <1 6 4>;
	};

	eud: qcom,msm-eud@1610000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x1610000 0x2000>,
		      <0x1612000 0x1000>,
		      <0x3E5018 0x4>;
		reg-names = "eud_base", "eud_mode_mgr2",
				"eud_tcsr_check_reg";
		qcom,secure-eud-en;
		qcom,eud-tcsr-check-enable;
		qcom,eud-clock-vote-req;
		clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
		clock-names = "eud_ahb2phy_clk";
		status = "ok";
	};

	qcom,msm-gladiator-v2@f100000 {
		compatible = "qcom,msm-gladiator-v2";
		reg = <0xf100000 0xdc00>;
		reg-names = "gladiator_base";
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "atb_clk";
		clocks = <&rpmcc RPM_QDSS_CLK>;
	};

	wdog: qcom,wdt@f017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xf017000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9360>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
	};

	rpm_bus: qcom,rpm-smd {
		compatible = "qcom,rpm-smd";
		rpm-channel-name = "rpm_requests";
		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
		rpm-channel-type = <15>; /* SMD_APPS_RPM */
	};

	qcom,chd_silver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
				      0x0f1a80b0 0x0f1b80b0>;
		qcom,config-arr = <0x0f1880b8 0x0f1980b8
				   0x0f1a80b8 0x0f1b80b8>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
				      0x0f0a80b0 0x0f0b80b0>;
		qcom,config-arr = <0x0f0880b8 0x0f0980b8
				   0x0f0a80b8 0x0f0b80b8>;
	};

	qcom,ghd {
		compatible = "qcom,gladiator-hang-detect";
		qcom,threshold-arr = <0x0f1d141c 0x0f1d1420
				      0x0f1d1424 0x0f1d1428
				      0x0f1d142c 0x0f1d1430>;
		qcom,config-reg = <0x0f1d1434>;
	};

	qcom,lpass@ab00000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xab00000 0x00100>;

		vdd_lpi_cx-supply = <&L3A_LEVEL>;
		qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
		qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		vdd_lpi_mx-supply = <&L2A_LEVEL>;
		qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;

		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,minidump-id = <5>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&pil_adsp_mem>;
		qcom,complete-ramdump;
		qcom,minidump-as-elf32;

		/* Inputs from lpass */
		interrupts-extended = <&intc 0 282 1>,
				      <&adsp_smp2p_in 0 0>,
				      <&adsp_smp2p_in 2 0>,
				      <&adsp_smp2p_in 1 0>,
				      <&adsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				  "qcom,err-fatal",
				  "qcom,proxy-unvote",
				  "qcom,err-ready",
				  "qcom,stop-ack";

		/* Outputs to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
	};

	qcom,turing@b300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xb300000 0x100000>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <601>;
		qcom,minidump-id = <7>;
		qcom,sysmon-id = <7>;
		qcom,ssctl-instance-id = <0x17>;
		qcom,firmware-name = "cdsp";
		memory-region = <&pil_cdsp_mem>;
		qcom,complete-ramdump;
		qcom,minidump-as-elf32;

		/* Inputs from turing */
		interrupts-extended = <&intc 0 265 1>,
				      <&cdsp_smp2p_in 0 0>,
				      <&cdsp_smp2p_in 2 0>,
				      <&cdsp_smp2p_in 1 0>,
				      <&cdsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				  "qcom,err-fatal",
				  "qcom,proxy-unvote",
				  "qcom,err-ready",
				  "qcom,stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
	};

	mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <&dump_mem>;

		c0_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x0>;
		};

		c1_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x1>;
		};

		c2_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x2>;
		};

		c3_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x3>;
		};

		c100_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x4>;
		};

		c101_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x5>;
		};

		c102_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x6>;
		};

		c103_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x7>;
		};

		c_scandump {
			qcom,dump-size = <0x40000>;
			qcom,dump-id = <0xeb>;
		};

		l1_icache0 {
			qcom,dump-size = <0x8900>;
			qcom,dump-id = <0x60>;
		};

		l1_icache1 {
			qcom,dump-size = <0x8900>;
			qcom,dump-id = <0x61>;
		};

		l1_icache2 {
			qcom,dump-size = <0x8900>;
			qcom,dump-id = <0x62>;
		};

		l1_icache3 {
			qcom,dump-size = <0x8900>;
			qcom,dump-id = <0x63>;
		};

		l1_icache100 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x64>;
		};

		l1_icache101 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x65>;
		};

		l1_icache102 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x66>;
		};

		l1_icache103 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x67>;
		};

		l1_dcache0 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x80>;
		};

		l1_dcache1 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x81>;
		};

		l1_dcache2 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x82>;
		};

		l1_dcache3 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x83>;
		};

		l1_dcache100 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x84>;
		};

		l1_dcache101 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x85>;
		};

		l1_dcache102 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x86>;
		};

		l1_dcache103 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x87>;
		};

		l2_tlb0 {
			qcom,dump-size = <0x2100>;
			qcom,dump-id = <0x120>;
		};

		l2_tlb1 {
			qcom,dump-size = <0x2100>;
			qcom,dump-id = <0x121>;
		};

		l2_tlb2 {
			qcom,dump-size = <0x2100>;
			qcom,dump-id = <0x122>;
		};

		l2_tlb3 {
			qcom,dump-size = <0x2100>;
			qcom,dump-id = <0x123>;
		};

		l2_tlb100 {
			qcom,dump-size = <0x4900>;
			qcom,dump-id = <0x124>;
		};

		l2_tlb101 {
			qcom,dump-size = <0x4900>;
			qcom,dump-id = <0x125>;
		};

		l2_tlb102 {
			qcom,dump-size = <0x4900>;
			qcom,dump-id = <0x126>;
		};

		l2_tlb103 {
			qcom,dump-size = <0x4900>;
			qcom,dump-id = <0x127>;
		};

		rpm_sw {
			qcom,dump-size = <0x28000>;
			qcom,dump-id = <0xea>;
		};

		pmic {
			qcom,dump-size = <0x40000>;
			qcom,dump-id = <0xe4>;
		};

		fcm {
			qcom,dump-size = <0x8400>;
			qcom,dump-id = <0xee>;
		};

		tmc_etf {
			qcom,dump-size = <0x8000>;
			qcom,dump-id = <0xf0>;
		};

		etr_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x100>;
		};

		etf_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x101>;
		};

		misc_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe8>;
		};
	};

	sdhc_1: sdhci@4744000 {
		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
		reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
		      <0x4748000 0x8000>;
		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";

		interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
				<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
				<&tlmm 19 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";

		qcom,bus-width = <8>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
						192000000 384000000>;
		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;

		qcom,scaling-lower-bus-speed-mode = "DDR52";

		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <9>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
			/* No vote */
			<78 512 0 0>, <1 606 0 0>,
			/* 400 KB/s*/
			<78 512 1046 1600>,
			<1 606 1600 1600>,
			/* 20 MB/s */
			<78 512 20480 80000>,
			<1 606 80000 80000>,
			/* 25 MB/s */
			<78 512 25600 250000>,
			<1 606 50000 133320>,
			/* 50 MB/s */
			<78 512 51200 250000>,
			<1 606 65000 133320>,
			/* 100 MB/s */
			<78 512 102400 250000>,
			<1 606 65000 133320>,
			/* 200 MB/s */
			<78 512 204800 800000>,
			<1 606 200000 300000>,
			/* 400 MB/s */
			<78 512 204800 800000>,
			<1 606 200000 300000>,
			/* Max. bandwidth */
			<78 512 1338562 4096000>,
			<1 606 1338562 4096000>;
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
			100750000 200000000 400000000 4294967295>;

		/* PM QoS */
		qcom,pm-qos-irq-type = "affine_irq";
		qcom,pm-qos-irq-latency = <26 26>;
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
		qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;

		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
		clock-names = "iface_clk", "core_clk", "ice_core_clk";

		qcom,ice-clk-rates = <300000000 100000000>;

		/* Add support for gcc hw reset */
		resets = <&gcc GCC_SDCC1_BCR>;
		reset-names = "core_reset";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
		qcom,nonremovable;
		status = "disabled";
	};

	sdhc_2: sdhci@4784000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x4784000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <4>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000
				50000000 100000000 202000000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
				      "SDR104";

		qcom,devfreq,freq-table = <50000000 202000000>;

		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <8>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
			/* No vote */
			<81 512 0 0>, <1 608 0 0>,
			/* 400 KB/s*/
			<81 512 1046 3200>,
			<1 608 1600 1600>,
			/* 20 MB/s */
			<81 512 52286 250000>,
			<1 608 80000 133320>,
			/* 25 MB/s */
			<81 512 65360 250000>,
			<1 608 100000 133320>,
			/* 50 MB/s */
			<81 512 130718 250000>,
			<1 608 133320 133320>,
			/* 100 MB/s */
			<81 512 261438 250000>,
			<1 608 150000 133320>,
			/* 200 MB/s */
			<81 512 261438 800000>,
			<1 608 300000 300000>,
			/* Max. bandwidth */
			<81 512 1338562 4096000>,
			<1 608 1338562 4096000>;
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
			100750000 200000000 4294967295>;

		/* PM QoS */
		qcom,pm-qos-irq-type = "affine_irq";
		qcom,pm-qos-irq-latency = <26 26>;
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;


		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
		qcom,vbias-skip-wa;

		status = "disabled";
	};

	ufsphy_mem: ufsphy_mem@4807000 {
		reg = <0x4807000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&gcc GCC_UFS_CLKREF_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc@4804000 {
		compatible = "qcom,ufshc";
		reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		spm-level = <5>;

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<50000000 200000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		qcom,msm-bus,name = "ufshc_mem";
		qcom,msm-bus,num-cases = <22>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<123 512 0 0>, <1 757 0 0>,          /* No vote */
		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */
		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */
		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */
		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */
		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */
		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
		"MAX";

		/* PM QoS */
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-cpu-group-latency-us = <26 26>;
		qcom,pm-qos-default-cpu = <0>;

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
		pinctrl-0 = <&ufs_dev_reset_assert>;
		pinctrl-1 = <&ufs_dev_reset_deassert>;

		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";
		non-removable;

		status = "disabled";
	};

	thermal_zones: thermal-zones {};

	tsens0:tsens@c222000 {
		compatible = "qcom,tsens24xx";
		reg = <0x04410000  0x8>,
			<0x04411000  0x1ff>;
		reg-names = "tsens_srot_physical",
			"tsens_tm_physical";
		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tsens-upper-lower", "tsens-critical";
		tsens-reinit-wa;
		#thermal-sensor-cells = <1>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	rpmcc: clock-controller {
		compatible = "qcom,rpmcc-bengal";
		#clock-cells = <1>;
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x200000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
		qcom,guard-memory;
		qcom,vm-nav-path;
	};

	gcc: clock-controller@1400000 {
		compatible = "qcom,khaje-gcc", "syscon";
		reg = <0x1400000 0x1f0000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@5f00000 {
		compatible = "qcom,khaje-dispcc", "syscon";
		reg = <0x05f00000 0x20000>;
		reg-names = "cc_base";
		clock-names = "cfg_ahb_clk";
		clocks = <&gcc GCC_DISP_AHB_CLK>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@5990000 {
		compatible = "qcom,khaje-gpucc", "syscon";
		reg = <0x5990000 0x9000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	mccc_debug: syscon@447d200 {
		compatible = "syscon";
		reg = <0x447d200 0x100>;
	};

	cpucc_debug: syscon@f11101c {
		compatible = "syscon";
		reg = <0xf11101c 0x4>;
	};

	debugcc: clock-controller@0 {
		compatible = "qcom,khaje-debugcc";
		qcom,gcc = <&gcc>;
		qcom,dispcc = <&dispcc>;
		qcom,gpucc = <&gpucc>;
		qcom,mccc = <&mccc_debug>;
		qcom,cpucc = <&cpucc_debug>;
		clock-names = "xo_clk_src";
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		#clock-cells = <1>;
	};

	cpufreq_hw: qcom,cpufreq-hw {
		compatible = "qcom,cpufreq-hw";
		reg = <0xf521000 0x1000>, <0xf523000 0x1000>;
		reg-names = "freq-domain0", "freq-domain1";
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		qcom,no-accumulative-counter;
		qcom,max-lut-entries = <12>;
		#freq-domain-cells = <2>;
	};

	qcom,cpufreq-hw-debug@0f521000 {
		compatible = "qcom,cpufreq-hw-debug";
		reg = <0x0f521000 0x800>;
		reg-names = "domain-top";
		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
	};

	tcsr_mutex_block: syscon@00340000 {
		compatible = "syscon";
		reg = <0x340000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	rpm_msg_ram: memory@045f0000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x45f0000 0x7000>;
	};

	apcs_glb: mailbox@0f111000 {
		compatible = "qcom,bengal-apcs-hmss-global";
		reg = <0xF111000 0x1000>;

		#mbox-cells = <1>;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
		restrict-access;
	};

	qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,rpc-latency-us = <611>;
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-adsp-sensors-pdr;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C01 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C02 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C03 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C04 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C05 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0C06 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x0C09 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x01C3 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x01C4 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x01C5 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x01C6 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

		qcom,msm_fastrpc_compute_cb14 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x01C7 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
		};

	};

	rpm-glink {
		compatible = "qcom,glink-rpm";
		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		mboxes = <&apcs_glb 0>;

		qcom,rpm_glink_ssr {
			qcom,glink-channels = "glink_ssr";
			qcom,notify-edges = <&glink_modem>,
					    <&glink_adsp>,
					    <&glink_cdsp>;
		};

	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_modem: modem {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apcs_glb 12>;
			mbox-names = "mpss_smem";
			interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 2>;
			};

			qcom,modem_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_cdsp>;
			};
		};

		glink_adsp: adsp {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&apcs_glb 8>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,apr_tal_rpmsg {
				qcom,glink-channels = "apr_audio_svc";
				qcom,intents = <0x200 20>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,adsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_cdsp>;
			};
		};

		glink_cdsp: cdsp {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&apcs_glb 28>;
			mbox-names = "cdsp_smem";
			interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-latency-us = <100>;
					qcom,qos-maxhold-ms = <20>;
				};
			};

			qcom,cdsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_adsp>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
			qcom,entry-name = "wlan";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 10>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 30>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	qfprom: qfprom@1b40000 {
		compatible = "qcom,qfprom";
		reg = <0x1b40000 0x7000>;
		#address-cells = <1>;
		#size-cells = <1>;
		read-only;
		ranges;

		stm_debug_fuse: stm@20f0 {
			reg = <0x20f0 0x4>;
		};

		feat_conf5: feat_conf5@6018 {
			reg = <0x6018 0x4>;
		};

		feat_conf10: feat_conf10@602c {
			reg = <0x602c 0x4>;
		};

		adsp_variant: adsp_variant@6011 {
			reg = <0x6011 0x1>;
			bits = <3 1>;
		};

		gpu_speed_bin: gpu_speed_bin@6006 {
			reg = <0x6006 0x2>;
			bits = <5 8>;
		};

		gpu_gaming_bin: gpu_gaming_bin@602d {
			reg = <0x602d 0x1>;
			bits = <5 1>;
		};

		feat_conf11: feat_conf11@6030 {
			reg = <0x6030 0x1>;
			bits = <0 8>;
		};
	};

	spmi_bus: qcom,spmi@1c40000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x1c40000 0x1100>,
			<0x1e00000 0x2000000>,
			<0x3e00000 0x100000>,
			<0x3f00000 0xa0000>,
			<0x1c0a000 0x26000>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
		qcom,ee = <0>;
		qcom,channel = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-controller;
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	icnss: qcom,icnss@C800000 {
		compatible = "qcom,icnss";
		reg = <0xC800000 0x800000>,
		      <0xb0000000 0x10000>;
		reg-names = "membase", "smmu_iova_ipa";
		iommus = <&apps_smmu 0x1A0 0x1>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
			     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
			     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
			     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
			     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
			     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
			     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
			     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
		qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
		qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
		qcom,iommu-dma = "fastmap";
		qcom,iommu-faults = "stall-disable", "HUPCF";
		qcom,iommu-geometry = <0xa0000000 0x10010000>;
		vdd-cx-mx-supply = <&L8A>;
		vdd-1.8-xo-supply = <&L16A>;
		vdd-1.3-rfa-supply = <&L17A>;
		vdd-3.3-ch0-supply = <&L23A>;
		qcom,vdd-cx-mx-config = <640000 640000>;
		qcom,vdd-3.3-ch0-config = <3000000 3312000>;
		qcom,smp2p_map_wlan_1_in {
			interrupts-extended = <&smp2p_wlan_1_in 0 0>,
					      <&smp2p_wlan_1_in 1 0>;
			interrupt-names = "qcom,smp2p-force-fatal-error",
					  "qcom,smp2p-early-crash-ind";
		};
	};

	qcom,venus@5ab0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x5ab0000 0x20000>;

		vdd-supply = <&gcc_venus_gdsc>;
		qcom,proxy-reg-names = "vdd";

		clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
			<&gcc GCC_VENUS_CTL_AXI_CLK>,
			<&gcc GCC_VIDEO_AHB_CLK>,
			<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
		clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
		qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
		qcom,mas-crypto = <&mas_crypto_c0>;

		qcom,core-freq = <240000000>;
		qcom,ahb-freq = <240000000>;

		qcom,pas-id = <9>;
		qcom,msm-bus,name = "pil-venus";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<63 512 0 0>,
			<63 512 0 304000>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&pil_video_mem>;
	};

	cx_ipeak_lm: cx_ipeak@3ed000 {
		compatible = "qcom,cx-ipeak-v2";
		reg = <0x3ed000 0xe008>;
	};

	pil_modem: qcom,mss@6080000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x6080000 0x100>;

		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,mas-crypto = <&mas_crypto_c0>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		qcom,proxy-reg-names = "vdd_cx";

		qcom,firmware-name = "modem";
		memory-region = <&pil_modem_mem>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,sysmon-id = <0>;
		qcom,ssctl-instance-id = <0x12>;
		qcom,pas-id = <4>;
		qcom,smem-id = <421>;
		qcom,minidump-id = <3>;
		qcom,aux-minidump-ids = <4>;
		qcom,complete-ramdump;
		qcom,sequential-fw-load;

		qcom,msm-bus,name = "pil-modem";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 8171520>;

		/* Inputs from mss */
		interrupts-extended = <&intc 0 307 1>,
				<&modem_smp2p_in 0 0>,
				<&modem_smp2p_in 2 0>,
				<&modem_smp2p_in 1 0>,
				<&modem_smp2p_in 3 0>,
				<&modem_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack",
				"qcom,shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
	};

	ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
		BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
		BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
		BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
		BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
		BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
		BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
	};

	suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY_DDR(   0, 8, 0x80); /*    0 MB/s */
		BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
		BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
		BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
		BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
		BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
		BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
		BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
	};

	cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
		compatible = "qcom,devbw-ddr";
		governor = "performance";
		qcom,src-dst-ports =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpu_cpu_ddr_bw>;
		qcom,count-unit = <0x10000>;
	};

	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
		compatible = "qcom,devbw-ddr";
		governor = "performance";
		qcom,src-dst-ports =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
		compatible = "qcom,devbw-ddr";
		governor = "performance";
		qcom,src-dst-ports =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
			qcom,target-dev = <&cpu0_cpu_ddr_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,stall-cycle-ev = <0xE7>;
			qcom,core-dev-table =
				< 1190400 MHZ_TO_MBPS( 547, 8) >,
				< 1516800 MHZ_TO_MBPS( 768, 8) >,
				< 1804800 MHZ_TO_MBPS(1017, 8) >;
		};

		cpu0_computemon: qcom,cpu0-computemon {
			compatible = "qcom,arm-compute-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
			qcom,core-dev-table =
				< 1190400 MHZ_TO_MBPS( 547, 8) >,
				< 1516800 MHZ_TO_MBPS( 768, 8) >,
				< 1804800 MHZ_TO_MBPS(1017, 8) >;
		};
	};

	cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
		compatible = "qcom,devbw-ddr";
		governor = "performance";
		qcom,src-dst-ports =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
		compatible = "qcom,devbw-ddr";
		governor = "performance";
		qcom,src-dst-ports =
			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
			qcom,target-dev = <&cpu4_cpu_ddr_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,stall-cycle-ev = <0x24>;
			qcom,core-dev-table =
				< 1056000 MHZ_TO_MBPS( 547, 8) >,
				< 1344000 MHZ_TO_MBPS(1017, 8) >,
				< 1766400 MHZ_TO_MBPS(1555, 8) >,
				< 2208000 MHZ_TO_MBPS(1804, 8) >,
				< 2803200 MHZ_TO_MBPS(2092, 8) >;
		};

		cpu4_computemon: qcom,cpu4-computemon {
			compatible = "qcom,arm-compute-mon";
			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
			qcom,core-dev-table =
				< 1056000 MHZ_TO_MBPS( 547, 8) >,
				< 1344000 MHZ_TO_MBPS( 768, 8) >,
				< 1766400 MHZ_TO_MBPS(1017, 8) >,
				< 2208000 MHZ_TO_MBPS(1804, 8) >,
				< 2803200 MHZ_TO_MBPS(2092, 8) >;
		};
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
		qcom,ipa-platform-type-msm;
		qcom,ipa-advertise-sg-support;
		qcom,ipa-napi-enable;
	};

	ipa_hw: qcom,ipa@0x5800000 {
		compatible = "qcom,ipa";
		reg = <0x5800000 0x34000>,
			<0x5804000 0x28000>;
		reg-names = "ipa-base", "gsi-base";
		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ipa-irq", "gsi-irq";
		qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
		qcom,ipa-hw-mode = <0>;
		qcom,platform-type = <1>; /* MSM platform */
		qcom,ee = <0>;
		qcom,use-ipa-tethering-bridge;
		qcom,modem-cfg-emb-pipe-flt;
		qcom,ipa-wdi2;
		qcom,ipa-wdi2_over_gsi;
		qcom,ipa-endp-delay-wa;
		qcom,ipa-fltrt-not-hashable;
		qcom,use-64-bit-dma-mask;
		qcom,arm-smmu;
		qcom,smmu-fast-map;
		qcom,use-ipa-pm;
		qcom,skip-ieob-mask-wa;
		clocks = <&rpmcc RPM_SMD_IPA_CLK>;
		clock-names = "core_clk";
		qcom,msm-bus,name = "ipa";
		qcom,msm-bus,num-cases = <5>;
		qcom,msm-bus,num-paths = <3>;
		qcom,msm-bus,vectors-KBps =
		/* No vote */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
		/* SVS2 */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
		/* SVS */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
		/* NOMINAL */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0  206000 4000000>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
		/* TURBO */
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
		qcom,bus-vector-names =
				"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
		qcom,throughput-threshold = <310 600 1000>;
		qcom,scaling-exceptions = <>;

		/* smp2p information */
		qcom,smp2p_map_ipa_1_out {
			compatible = "qcom,smp2p-map-ipa-1-out";
		qcom,smem-states = <&smp2p_ipa_1_out 0>;
			qcom,smem-state-names = "ipa-smp2p-out";
		};

		qcom,smp2p_map_ipa_1_in {
			compatible = "qcom,smp2p-map-ipa-1-in";
			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
			interrupt-names = "ipa-smp2p-in";
		};
	};

	ipa_smmu_ap: ipa_smmu_ap {
		compatible = "qcom,ipa-smmu-ap-cb";
		iommus = <&apps_smmu 0x0140 0x0>;
		qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
		/* modem tables in IMEM */
		qcom,iommu-dma = "fastmap";
		qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
		qcom,iommu-geometry = <0 0xB0000000>;
	};

	ipa_smmu_wlan: ipa_smmu_wlan {
		compatible = "qcom,ipa-smmu-wlan-cb";
		iommus = <&apps_smmu 0x0141 0x0>;
		/* ipa-uc ram */
		qcom,iommu-dma = "atomic";
	};

	ipa_smmu_uc: ipa_smmu_uc {
		compatible = "qcom,ipa-smmu-uc-cb";
		iommus = <&apps_smmu 0x0142 0x0>;
		qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
	};

	qcom,ipa_fws {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <0xf>;
		qcom,firmware-name = "ipa_fws";
		qcom,pil-force-shutdown;
		memory-region = <&pil_ipa_fw_mem>;
	};

	qcom,demux {
		compatible = "qcom,demux";
	};

tpdm_turing_llm: tpdm@8861000 {
		compatible = "qcom,coresight-dummy";

		coresight-name = "coresight-tpdm-turing_llm";
		qcom,dummy-source;

		port {
			tpdm_turing_llm_out_funnel_turing: endpoint {
				remote-endpoint =
				<&funnel_turing_in_tpdm_turing_llm>;
			};
		};
	};

	/delete-node/ tpdm@8a58000;
	tpdm_west: tpdm@8a58000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8a58000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-west";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		port {
			tpdm_west_out_tpda11: endpoint {
				remote-endpoint =
				<&tpda11_in_tpdm_west>;
			};
		};
	};

	tpdm_spdm: tpdm@800f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x0800f000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-spdm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		port {
			tpdm_spdm_out_tpda13: endpoint {
				remote-endpoint =
				<&tpda13_in_tpdm_spdm>;
			};
		};
	};

	/delete-node/ funnel@8861000;
	funnel_turing: funnel@8863000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8863000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-turing";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_turing_out_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_in_funnel_turing>;
					source = <&turing_etm0>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_turing_out_tpda5: endpoint {
					remote-endpoint =
					<&tpda5_in_funnel_turing>;
				};
			};

			port@2 {
				reg = <0>;
				funnel_turing_in_tpdm_turing: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_turing_out_funnel_turing>;
				};
			};

			port@3 {
				reg = <1>;
				funnel_turing_in_tpdm_turing_llm: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_turing_llm_out_funnel_turing>;
				};
			};

			port@4 {
				reg = <2>;
				funnel_turing_in_turing_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					<&turing_etm0_out_funnel_turing>;
				};
			};
		};
	};

	/delete-node/ tpda@8004000;
	tpda: tpda@8004000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x8004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,dsb-elem-size = <0 32>,
						<1 32>,
						<5 32>,
						<11 32>,
						<12 32>,
						<15 32>;
		qcom,cmb-elem-size = <7 32>,
						<8 32>,
						<10 32>,
						<15 64>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_out_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_in_tpda>;
				};
			};

			port@1 {
				reg = <0>;
				tpda0_in_tpdm_dl_ct: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_dl_ct_out_tpda0>;
				};
			};

			port@2 {
				reg = <1>;
				tpda1_in_funnel_gpu: endpoint {
					slave-mode;
					remote-endpoint =
					<&funnel_gpu_out_tpda1>;
				};
			};

			port@3 {
				reg = <5>;
				tpda5_in_funnel_turing: endpoint {
					slave-mode;
					remote-endpoint =
					<&funnel_turing_out_tpda5>;
				};
			};

			port@4 {
				reg = <7>;
				tpda7_in_tpdm_vsense: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_vsense_out_tpda7>;
				};
			};

			port@5 {
				reg = <8>;
				tpda8_in_tpdm_dcc: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_dcc_out_tpda8>;
				};
			};

			port@6 {
				reg = <10>;
				tpda10_in_tpdm_prng: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_prng_out_tpda10>;
				};
			};

			port@7 {
				reg = <11>;
				tpda11_in_tpdm_west: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_west_out_tpda11>;
				};
			};

			port@8 {
				reg = <12>;
				tpda12_in_tpdm_qm: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_qm_out_tpda12>;
				};
			};

			port@9 {
				reg = <13>;
				tpda13_in_tpdm_spdm: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_spdm_out_tpda13>;
				};
			};

			port@10 {
				reg = <15>;
				tpda15_in_tpdm_pimem: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_pimem_out_tpda15>;
				};
			};

		};
	};

	/delete-node/ cti@8867000;
	cti_turing_q6: cti@8862000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8862000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-turing-q6";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};
};

#include "bengal-gdsc.dtsi"
#include "khaje-usb.dtsi"
#include "bengal-ion.dtsi"
#include "bengal-bus.dtsi"
#include "bengal-vidc.dtsi"
#include "pm6125.dtsi"

&gcc_camss_top_gdsc {
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	status = "ok";
};

&gcc_vcodec0_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&gcc_venus_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu0_gdsc {
	status = "ok";
};

&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
	status = "ok";
};

&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
	status = "ok";
};

&mdss_core_gdsc {
	reg = <0x5f01004 0x4>;
	qcom,support-hw-trigger;
	status = "ok";
};

&gpu_cx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_gx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

#include "msm-arm-smmu-bengal.dtsi"
#include "pm6125-rpm-regulator.dtsi"
#include "khaje-regulator.dtsi"
#include "bengal-pm.dtsi"
#include "khaje-pinctrl.dtsi"
#include "bengal-qupv3.dtsi"
#include "bengal-gpu.dtsi"
#include "bengal-audio.dtsi"
#include "khaje-sde-pll.dtsi"
#include "khaje-sde.dtsi"

&soc {
	/delete-node/ gpu_bw_tbl;
	/delete-node/ gpubw;
	/delete-node/ gpu_opp_table;

	gpu_bw_tbl: gpu-bw-tbl {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 0, 8); /* 0 MB/s */
		BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */
		BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */
		BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */
		BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */
		BW_OPP_ENTRY(1555, 8); /*11863 MB/s */
		BW_OPP_ENTRY(1804, 8); /*13763 MB/s */
		BW_OPP_ENTRY(2092, 8); /*15960 MB/s */
	};

	gpubw: qcom,gpubw {
			compatible = "qcom,devbw";
			governor = "bw_vbif";
			qcom,src-dst-ports = <26 512>;
			operating-points-v2 = <&gpu_bw_tbl>;
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-1114800000 {
			opp-hz = /bits/ 64 <1114800000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
		};

		opp-1025000000 {
			opp-hz = /bits/ 64 <1025000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
		};

		opp-785000000 {
			opp-hz = /bits/ 64 <785000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
		};

		opp-465000000 {
			opp-hz = /bits/ 64 <465000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
		};

		opp-320000000 {
			opp-hz = /bits/ 64 <320000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
		};
	};
};

&msm_gpu {
	qcom,chipid = <0x06010001>;
	qcom,msm-bus,num-cases = <8>;
	qcom,msm-bus,vectors-KBps =
		<26 512 0 0>,
		<26 512 0 1600000>,   /*  1 bus=200  (LOW SVS) */
		<26 512 0 4376000>,   /*  2 bus=547  (LOW SVS) */
		<26 512 0 6144000>,   /*  3 bus=768  (SVS)     */
		<26 512 0 8136000>,   /*  4 bus=1017 (SVS_L1)  */
		<26 512 0 12440000>,  /*  5 bus=1555 (NOM)     */
		<26 512 0 14432000>,  /*  6 bus=1804 (TURBO)   */
		<26 512 0 16736000>;  /*  7 bus=2092 (TURBO_L1)   */

	/delete-node/ qcom,gpu-pwrlevel-bins;
	/*
	 * Speed-bin zero is default speed bin.
	 * For rest of the speed bins, speed-bin value
	 * is calculated as FMAX/4.8 MHz round up to zero
	 * decimal places plus two margin to account for
	 * clock jitters.
	 */
	qcom,gpu-pwrlevel-bins {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <0>;

			qcom,initial-pwrlevel = <6>;
			qcom,ca-target-pwrlevel = <5>;

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1260000000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
			};

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <1114800000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
			};

			/* TURBO */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@6 {
				reg = <6>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
			};

			/* XO */
			qcom,gpu-pwrlevel@7 {
				reg = <7>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};

		qcom,gpu-pwrlevels-1 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <235>;

			qcom,initial-pwrlevel = <5>;
			qcom,ca-target-pwrlevel = <4>;

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1114800000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
			};

			/* TURBO */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
			};

			/* XO */
			qcom,gpu-pwrlevel@6 {
				reg = <6>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};

		qcom,gpu-pwrlevels-2 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <216>;

			qcom,initial-pwrlevel = <4>;
			qcom,ca-target-pwrlevel = <3>;

			/* TURBO */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
			};

			/* XO */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};
	};
};

&qupv3_se1_i2c {
	status = "ok";
	#include "pm8008.dtsi"
};

&pm8008_regulators {
	/delete-property/ qcom,enable-ocp-broadcast;
};

&pm8008_8 {
	/* PM8008 IRQ STAT */
	interrupt-parent = <&tlmm>;
	interrupts = <25 IRQ_TYPE_EDGE_RISING>;

	pinctrl-names = "default";
	pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
};

&pm8008_regulators {
	vdd_l1_l2-supply = <&S6A>;
	vdd_l7-supply = <&S7A>;
};

&L1P {
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1300000>;
	qcom,min-dropout-voltage = <56000>;
};

&L2P {
	regulator-min-microvolt = <950000>;
	regulator-max-microvolt = <1150000>;
	qcom,min-dropout-voltage = <88000>;
};

&L3P {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2900000>;
	qcom,min-dropout-voltage = <96000>;
};

&L4P {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2900000>;
	qcom,min-dropout-voltage = <136000>;
};

&L5P {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2900000>;
	qcom,min-dropout-voltage = <240000>;
};

&L6P {
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <2900000>;
	qcom,min-dropout-voltage = <168000>;
};

&L7P {
	regulator-min-microvolt = <1650000>;
	regulator-max-microvolt = <1800000>;
	qcom,min-dropout-voltage = <112000>;
};

&qupv3_se4_2uart {
	status = "ok";
};

&qupv3_se3_4uart {
	status = "ok";
};

&pm6125_vadc {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&camera_therm_default &emmc_therm_default>;

	pa_therm0 {
		reg = <ADC_AMUX_THM1_PU2>;
		label = "pa_therm0";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	quiet_therm {
		reg = <ADC_AMUX_THM2_PU2>;
		label = "quiet_therm";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	camera_flash_therm {
		reg = <ADC_GPIO1_PU2>;
		label = "camera_flash_therm";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	emmc_ufs_therm {
		reg = <ADC_GPIO2_PU2>;
		label = "emmc_ufs_therm";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};
};

&pm6125_gpios {
	camera_therm {
		camera_therm_default: camera_therm_default {
			pins = "gpio3";
			bias-high-impedance;
		};
	};

	emmc_therm {
		emmc_therm_default: emmc_therm_default {
			pins = "gpio4";
			bias-high-impedance;
		};
	};

};

&spmi_bus {
	qcom,pm6125@0 {
		pm6125_adc_tm_iio: adc_tm@3400 {
			compatible = "qcom,adc-tm5-iio";
			reg = <0x3400 0x100>;
			#thermal-sensor-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			io-channels = <&pm6125_vadc ADC_GPIO1_PU2>,
					<&pm6125_vadc ADC_GPIO2_PU2>;

			camera_flash_therm {
				reg = <ADC_GPIO1_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			emmc_ufs_therm {
				reg = <ADC_GPIO2_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};
		};
	};
};

&pm6125_adc_tm {
	#address-cells = <1>;
	#size-cells = <0>;
	io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
			<&pm6125_vadc ADC_AMUX_THM2_PU2>,
			<&pm6125_vadc ADC_XO_THERM_PU2>;

	/* Channel nodes */
	pa_therm0 {
		reg = <ADC_AMUX_THM1_PU2>;
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
	};

	quiet_therm {
		reg = <ADC_AMUX_THM2_PU2>;
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
	};

	xo_therm {
		reg = <ADC_XO_THERM_PU2>;
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
	};
};

&msm_vidc {
	qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
	qcom,clock-freq-threshold = <300000000>;
};

#include "bengal-thermal.dtsi"
#include "camera/khaje-camera.dtsi"
#include "msm-rdbg.dtsi"

&cxip_cdev {
	status = "disabled";
};

&rpm_bus {
	rpm_smd_cdev: rpm-smd-cdev {
		compatible = "qcom,rpm-smd-cooling-device";
		#cooling-cells = <2>;
	};
};

&thermal_zones {
	mapss-lowc {
		cooling-maps {
			rpm_smd_vdd_cdev {
				trip = <&mapss_cap_trip>;
				cooling-device = <&rpm_smd_cdev 2 2>;
			};
		};
	};

	camera-lowc {
		cooling-maps {
			rpm_smd_vdd_cdev {
				trip = <&camera_cap_trip>;
				cooling-device = <&rpm_smd_cdev 2 2>;
			};
		};
	};
};