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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/clock/qcom,videocc-kona.h>
&soc {
msm_cvp: qcom,cvp@ab00000 {
compatible = "qcom,msm-cvp", "qcom,kona-cvp";
status = "ok";
reg = <0xab00000 0x100000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
/* LLCC Cache */
cache-slice-names = "cvp";
/* Supply */
cvp-supply = <&mvs1c_gdsc>;
cvp-core-supply = <&mvs1_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi1", "cvp_clk", "core_clk";
clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>,
<&clock_videocc VIDEO_CC_MVS1C_CLK>,
<&clock_videocc VIDEO_CC_MVS1_CLK>;
qcom,proxy-clock-names = "gcc_video_axi1",
"cvp_clk", "core_clk";
/* V2 clock frequency plan */
qcom,clock-configs = <0x0 0x1 0x1>;
qcom,allowed-clock-rates = <280000000 366000000 444000000>;
resets = <&clock_gcc GCC_VIDEO_AXI1_CLK_ARES>,
<&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>;
reset-names = "cvp_axi_reset", "cvp_core_reset";
qcom,reg-presets = <0xB0088 0x0>;
/* Buses */
cvp_cnoc {
compatible = "qcom,msm-cvp,bus";
label = "cvp-cnoc";
qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
cvp_bus_ddr {
compatible = "qcom,msm-cvp,bus";
label = "cvp-ddr";
qcom,bus-master = <MSM_BUS_MASTER_VIDEO_PROC>;
qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 6533000>;
};
/* MMUs */
cvp_non_secure_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_hlos";
iommus =
<&apps_smmu 0x2120 0x400>;
buffer-types = <0xfff>;
qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
};
cvp_secure_nonpixel_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_sec_nonpixel";
iommus =
<&apps_smmu 0x2124 0x400>;
buffer-types = <0x741>;
qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
qcom,iommu-vmid = <0xB>;
};
cvp_secure_pixel_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_sec_pixel";
iommus =
<&apps_smmu 0x2123 0x400>;
buffer-types = <0x106>;
qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
qcom,iommu-vmid = <0xA>;
};
/* Memory Heaps */
qcom,msm-cvp,mem_cdsp {
compatible = "qcom,msm-cvp,mem-cdsp";
memory-region = <&cdsp_mem>;
};
};
};
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