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&soc {
wsa_spkr_en: wsa_spkr_en_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};
};
&rx_macro {
compatible = "qcom,rx-macro";
reg = <0x0a600000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>,
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,rx-wsa-enable = <1>;
swr1: rx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <2>;
qcom,swrm-hctl-reg = <0x0a6a9098>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0x0a610000 0x0>;
interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <7>;
qcom,disable-div2-clk-switch = <1>;
qcom,swr-port-mapping = <1 HPH_L 0x1>,
<1 HPH_R 0x2>, <2 CLSH 0x1>,
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
<4 LO 0x1>, <5 DSD_L 0x1>,
<5 DSD_R 0x2>,
<7 SWRM_RX_PCM_IN 0xF>;
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
wsa883x_0221: wsa883x@02170221 {
compatible = "qcom,wsa883x";
reg = <0x2 0x2170221>;
qcom,spkr-sd-n-node = <&wsa_spkr_en>;
qcom,bolero-handle = <&bolero>;
cdc-vdd-1p8-supply = <&L19A>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "SpkrLeft";
};
};
};
&monaco_snd {
qcom,model = "monaco-idp-wsa-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <1>;
qcom,va-bolero-codec = <1>;
qcom,audio-routing =
"SpkrLeft IN", "AUX_OUT",
"TX SWR_INPUT", "VA_TX_SWR_CLK",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"TX_AIF1 CAP", "VA_TX_SWR_CLK",
"TX_AIF2 CAP", "VA_TX_SWR_CLK",
"TX_AIF3 CAP", "VA_TX_SWR_CLK",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK";
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
asoc-codec = <&stub_codec>, <&bolero>,
<&wsa883x_0221>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wsa-codec1";
qcom,wsa-max-devs = <1>;
qcom,wsa-devs = <&wsa883x_0221>;
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>;
};
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