1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
&soc {
msm_bus: qcom,kgsl-busmon {
label = "kgsl-busmon";
compatible = "qcom,kgsl-busmon";
};
gpu_bw_tbl: gpu-bw-tbl {
compatible = "operating-points-v2";
opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */
opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */
opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. 297 MHz */
opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */
opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. 557 MHz */
opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. 595 MHz */
opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. 672 MHz */
opp-739 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. 739 MHz */
};
/* Bus governor */
gpubw: qcom,gpubw {
compatible = "qcom,devbw";
governor = "bw_vbif";
qcom,src-dst-ports = <26 512>;
operating-points-v2 = <&gpu_bw_tbl>;
qcom,active-only;
};
msm_gpu: qcom,kgsl-3d0@1c00000 {
label = "kgsl-3d0";
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
reg = <0x1c00000 0x10000
0x1c10000 0x10000
0x00a0000 0x06fff>;
reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory",
"qfprom_memory";
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
qcom,id = <0>;
qcom,chipid = <0x03000620>;
qcom,initial-pwrlevel = <3>;
qcom,idle-timeout = <80>; //msecs
qcom,strtstp-sleepwake;
qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz
clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
<&gcc GCC_OXILI_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_BIMC_GPU_CLK>,
<&gcc GCC_GTCU_AHB_CLK>,
<&gcc GCC_GFX_TCU_CLK>,
<&gcc GCC_GFX_TBU_CLK>,
<&rpmcc RPM_SMD_BIMC_GPU_CLK>;
clock-names = "core_clk", "iface_clk", "mem_iface_clk",
"alt_mem_iface_clk", "gtcu_iface_clk",
"gtcu_clk", "gtbu_clk", "bimc_gpu_clk";
/* Bus Scale Settings */
qcom,gpubw-dev = <&gpubw>;
qcom,bus-control;
qcom,bus-width = <16>;
qcom,msm-bus,name = "grp3d";
qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<26 512 0 0>, /* off */
<26 512 0 806400>, /* 1. 100.80 MHz */
<26 512 0 1689600>, /* 2. 211.20 MHz */
<26 512 0 2380800>, /* 3. 297.60 MHz */
<26 512 0 3072000>, /* 4. 384.00 MHz */
<26 512 0 4454400>, /* 5. 556.80 MHz */
<26 512 0 4761600>, /* 6. 595.20 MHz */
<26 512 0 5376000>, /* 7. 672.00 MHz */
<26 512 0 5913600>; /* 8. 739.20 MHz */
/* GDSC regulator names */
regulator-names = "vdd";
/* GDSC oxili regulators */
vdd-supply = <&gdsc_oxili_gx>;
/* CPU latency parameter */
qcom,pm-qos-active-latency = <651>;
/* Enable gpu cooling device */
#cooling-cells = <2>;
/* Power levels */
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
/* TURBO */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <598000000>;
qcom,bus-freq = <7>;
qcom,bus-min = <7>;
qcom,bus-max = <7>;
};
/* NOM+ */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <523200000>;
qcom,bus-freq = <6>;
qcom,bus-min = <5>;
qcom,bus-max = <7>;
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <484800000>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
qcom,bus-max = <6>;
};
/* SVS+ */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <400000000>;
qcom,bus-freq = <4>;
qcom,bus-min = <3>;
qcom,bus-max = <5>;
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <270000000>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* XO */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <19200000>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
};
kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x1f00000 0x10000>;
/*
* The gpu can only program a single context bank
* at this fixed offset.
*/
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_GFX_TCU_CLK>,
<&gcc GCC_GTCU_AHB_CLK>,
<&gcc GCC_GFX_TBU_CLK>;
clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk",
"gtbu_clk";
qcom,retention;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&gfx_iommu 0>;
qcom,iommu-dma = "disabled";
qcom,gpu-offset = <0xa000>;
};
};
};
|
