path: root/qcom/sa8155-vm.dtsi

#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include "quin-vm-common.dtsi"
#include "pm8150-vm.dtsi"
/ {
	model = "Qualcomm Technologies, Inc. SA8155 Guest Virtual Machine";
	qcom,msm-name  = "SA8155 v2";
	qcom,msm-id = <362 0x20000>;
	aliases {
		hsuart0 = &qupv3_se17_4uart;
		serial0 = &qupv3_se12_2uart;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			capacity-dmips-mhz = <1024>;
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			capacity-dmips-mhz = <1024>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			capacity-dmips-mhz = <1024>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			capacity-dmips-mhz = <1024>;
		};

		CPU4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x4>;
			capacity-dmips-mhz = <414>;
		};

		CPU5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x5>;
			capacity-dmips-mhz = <414>;
		};

		CPU6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x6>;
			capacity-dmips-mhz = <414>;
		};

		CPU7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x7>;
			capacity-dmips-mhz = <414>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware: firmware {
		scm {
			compatible = "qcom,scm";
		};
	};
};

&soc {
	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_qseecom: qseecom@87900000 {
		compatible = "qcom,qseecom";
		reg = <0x87900000 0x2200000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,qsee-reentrancy-support = <2>;
	};
};

&soc {
	/* Rome 3.3V supply */
	vreg_wlan: vreg_wlan {
		compatible = "qcom,stub-regulator";
		regulator-name = "vreg_wlan";
	};

	/* PWR_CTR2_VDD_1P8 supply */
	vreg_conn_1p8: vreg_conn_1p8 {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_1p8";
		pinctrl-names = "default";
		pinctrl-0 = <&conn_power_1p8_active>;
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&tlmm 173 0>;
	};

	/* PWR_CTR1_VDD_PA supply */
	vreg_conn_pa: vreg_conn_pa {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_pa";
		pinctrl-names = "default";
		pinctrl-0 = <&conn_power_pa_active>;
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&tlmm 174 0>;
	};

	VDD_CX_LEVEL: VDD_MMCX_LEVEL:
	S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level {
		compatible = "qcom,stub-regulator";
		regulator-name = "pm8150_2_s9_level";
		regulator-min-microvolt
			= <RPMH_REGULATOR_LEVEL_RETENTION>;
		regulator-max-microvolt
			= <RPMH_REGULATOR_LEVEL_MAX>;
	};

	apps_smmu: apps-smmu@0x15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x100000>,
			<0x15182000 0x20>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,handoff-smrs = <0xffff 0x0>;
		qcom,multi-match-handoff-smr;
		qcom,disable-atos;
		#global-interrupts = <1>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
	};

	dma_dev@0x0 {
		compatible = "qcom,iommu-dma";
		memory-region = <&system_cma>;
	};

	qcom_rng: qrng@793000 {
		compatible = "qcom,msm-rng";
		reg = <0x793000 0x1000>;
		qcom,no-qrng-config;
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
		clock-names = "km_clk_src";
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm8150-pdc","qcom,pdc";
		reg = <0xb220000 0x30000>;
		qcom,pdc-ranges = <6 486 6>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};
};

#include "sm8150-pinctrl.dtsi"
#include "sa8155-vm-pcie.dtsi"
#include "sa8155-vm-qupv3.dtsi"
#include "sa8155-vm-usb.dtsi"

&tlmm {
	/delete-property/ wakeup-parent;
};

&regulator {
	usb30_prim_gdsc: usb30_prim_gdsc {
		regulator-name = "usb30_prim_gdsc";
	};

	usb30_sec_gdsc: usb30_sec_gdsc {
		regulator-name = "usb30_sec_gdsc";
	};

	pcie_0_gdsc: pcie_0_gdsc {
		regulator-name = "pcie_0_gdsc";
	};

	pcie_1_gdsc: pcie_1_gdsc {
		regulator-name = "pcie_1_gdsc";
	};

	L2A: pm8150_1_l2: regulator-pm8150-1-l2 {
		regulator-name = "ldoa2";
		regulator-min-microvolt = <3072000>;
		regulator-max-microvolt = <3072000>;
	};

	L5A: pm8150_1_l5: regulator-pm8150-1-l5 {
		regulator-name = "ldoa5";
		regulator-min-microvolt = <880000>;
		regulator-max-microvolt = <880000>;
	};

	L12A: pm8150_1_l12: regulator-pm8150-1-l12 {
		regulator-name = "ldoa12";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	L17A: pm8150_1_l17: regulator-pm8150-1-l17 {
		regulator-name = "ldoa17";
		regulator-min-microvolt = <2704000>;
		regulator-max-microvolt = <2960000>;
	};

	L8C: pm8150_2_l8: regulator-pm8150-2-l8 {
		regulator-name = "ldoc8";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-allow-set-load;
	};

	L13C: pm8150_2_l13: regulator-pm8150-2-l13 {
		regulator-name = "ldoc13";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <2960000>;
	};

	L15C: pm8150_2_l15: regulator-pm8150-2-l15 {
		regulator-name = "ldoc15";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1904000>;
	};

	L18C: pm8150_2_l18: regulator-pm8150-2-l18 {
		regulator-name = "ldoc18";
		regulator-min-microvolt = <880000>;
		regulator-max-microvolt = <880000>;
		regulator-allow-set-load;
	};

	S6A: pm8150_1_s6: regulator-pm8150-1-s6 {
		regulator-name = "smpa6";
		regulator-min-microvolt = <600000>;
		regulator-max-microvolt = <1352000>;
	};

	S4C: pm8150_2_s4: regulator-pm8150-2-s4 {
		regulator-name = "smpc4";
		regulator-min-microvolt = <800000>;
		regulator-max-microvolt = <1400000>;
	};

	S5C: pm8150_2_s5: regulator-pm8150-2-s5 {
		regulator-name = "smpc5";
		regulator-min-microvolt = <1824000>;
		regulator-max-microvolt = <2040000>;
	};
};

&hab {
	/delete-node/ mmidgrp1400;
	/delete-node/ mmidgrp1500;
};

&pcie0_msi {
	status = "ok";
};

&pcie0 {
	status = "ok";
};

&qupv3_se17_4uart {
	status = "ok";
};

&qupv3_se12_2uart {
	status = "disabled";
};
&soc {
	tcsr_compute_signal_glb: syscon@0x1fd8000 {
		compatible = "syscon";
		reg = <0x1fd8000 0x1000>;
	};

	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
		compatible = "syscon";
		reg = <0x1fd9000 0x1000>;
	};

	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
		compatible = "syscon";
		reg = <0x1fdd000 0x1000>;
	};

	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
		compatible = "syscon";
		reg = <0x1fdb000 0x1000>;
	};

	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
		compatible = "syscon";
		reg = <0x1fdf000 0x1000>;
	};

	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
		compatible = "qcom,hgsl-tcsr-sender";
		syscon = <&tcsr_compute_signal_sender0>;
		syscon-glb = <&tcsr_compute_signal_glb>;
	};

	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
		compatible = "qcom,hgsl-tcsr-sender";
		syscon = <&tcsr_compute_signal_sender1>;
		syscon-glb = <&tcsr_compute_signal_glb>;
	};

	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
		compatible = "qcom,hgsl-tcsr-receiver";
		syscon = <&tcsr_compute_signal_receiver0>;
		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
	};

	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
		compatible = "qcom,hgsl-tcsr-receiver";
		syscon = <&tcsr_compute_signal_receiver1>;
		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
	};

	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
		compatible = "qcom,hgsl";
		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";

		qcom,glb-db-senders = <&hgsl_tcsr_sender0
					&hgsl_tcsr_sender1>;
		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
					&hgsl_tcsr_receiver1>;
	};
};