1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup0 5: SE 5
* Qup0 6: SE 6
* Qup0 7: SE 7
* Qup1 0: SE 8
* Qup1 1: SE 9
* Qup1 2: SE 10
* Qup1 3: SE 11
* Qup1 4: SE 12
* Qup1 5: SE 13
* Qup2 0: SE 14
* Qup2 1: SE 15
* Qup2 2: SE 16
* Qup2 3: SE 17
* Qup2 4: SE 18
* Qup2 5: SE 19
*/
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
compatible = "qcom,geni-se-qup";
reg = <0xcc0000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x7a3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok";
/* HS UART Instance */
qupv3_se17_4uart: qcom,qup_uart@c8c000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xc8c000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 46 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>,
<&qupv3_se17_default_tx>;
pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
<&qupv3_se17_tx>;
pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
<&qupv3_se17_tx>;
pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,<&qupv3_se17_default_tx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
};
};
|
