sw5100: Integrate LW 2.0 r00040.3

Bug: 268128919
Change-Id: I2247c46a814126eca53321a464348f164933f728
Signed-off-by: Andrei Ciubotariu <aciubotariu@google.com>

13 files changed, 945 insertions, 355 deletions

diff --git a/Kbuild b/Kbuild
index ed4b633..8bda007 100755
--- a/Kbuild
+++ b/Kbuild
@@ -6,6 +6,7 @@ endif
 ifeq ($(CONFIG_ARCH_KALAMA), y)
 dtbo-y += gpu/kalama-gpu.dtbo \
 		gpu/kalama-v2-gpu.dtbo \
+		gpu/kalama-hhg-gpu.dtbo \
 		gpu/kalamap-hhg-gpu.dtbo
 endif
 
@@ -32,6 +33,10 @@ ifeq ($(CONFIG_ARCH_MONACO), y)
 dtbo-y += gpu/monaco-gpu.dtbo
 endif
 
+ifeq ($(CONFIG_ARCH_LEMANS), y)
+dtbo-y += gpu/lemans-gpu.dtbo
+endif
+
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
 clean-files    := *.dtb *.dtbo
diff --git a/gpu/kalama-gpu-pwrlevels.dtsi b/gpu/kalama-gpu-pwrlevels.dtsi
index 5ac4dcd..ba1cc5d 100755
--- a/gpu/kalama-gpu-pwrlevels.dtsi
+++ b/gpu/kalama-gpu-pwrlevels.dtsi
@@ -130,6 +130,15 @@
 				qcom,bus-min = <1>;
 				qcom,bus-max = <3>;
 			};
+			qcom,gpu-pwrlevel@10 {
+				reg = <10>;
+				qcom,gpu-freq = <124800000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <1>;
+			};
 		};
 
 		qcom,gpu-pwrlevels-1 {
@@ -203,6 +212,16 @@
 				qcom,bus-min = <1>;
 				qcom,bus-max = <3>;
 			};
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <124800000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <1>;
+			};
+
 		};
 	};
 };
diff --git a/gpu/kalama-hhg-gpu.dts b/gpu/kalama-hhg-gpu.dts
new file mode 100755
index 0000000..329f5a5
--- /dev/null
+++ b/gpu/kalama-hhg-gpu.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-kalama.h>
+#include <dt-bindings/clock/qcom,gpucc-kalama.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,kalama.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kalama-v2-gpu.dtsi"
+#include "kalama-hhg-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kalama HHG";
+	compatible = "qcom,kalama-hhg";
+	qcom,msm-id = <600 0x20000>;
+	qcom,board-id = <0 0>;
+};
+
diff --git a/gpu/kalama-v2-gpu-pwrlevels.dtsi b/gpu/kalama-v2-gpu-pwrlevels.dtsi
index ce49f80..1644d5c 100755
--- a/gpu/kalama-v2-gpu-pwrlevels.dtsi
+++ b/gpu/kalama-v2-gpu-pwrlevels.dtsi
@@ -123,6 +123,15 @@
 
 				qcom,acd-level = <0xc02f5ffd>;
 			};
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <124800000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <1>;
+			};
 		};
 
 		qcom,gpu-pwrlevels-1 {
@@ -222,6 +231,16 @@
 
 				qcom,acd-level = <0xc02f5ffd>;
 			};
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <124800000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <1>;
+			};
+
 		};
 	};
 };
diff --git a/gpu/kalama-v2-gpu.dts b/gpu/kalama-v2-gpu.dts
index 19ebd10..aa5678b 100755
--- a/gpu/kalama-v2-gpu.dts
+++ b/gpu/kalama-v2-gpu.dts
@@ -15,8 +15,8 @@
 
 / {
 	model = "Qualcomm Technologies, Inc. Kalama v2";
-	compatible = "qcom,kalama";
-	qcom,msm-id = <519 0x20000>, <536 0x20000>;
+	compatible = "qcom,kalama", "qcom,kalamap";
+	qcom,msm-id = <519 0x20000>, <536 0x20000>, <603 0x20000>, <604 0x20000>;
 	qcom,board-id = <0 0>;
 };
 
diff --git a/gpu/kalamap-hhg-gpu-pwrlevels.dtsi b/gpu/kalamap-hhg-gpu-pwrlevels.dtsi
new file mode 100755
index 0000000..1535b2a
--- /dev/null
+++ b/gpu/kalamap-hhg-gpu-pwrlevels.dtsi
@@ -0,0 +1,168 @@
+&msm_gpu {
+	qcom,initial-pwrlevel = <12>;
+
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels";
+
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <860000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+			qcom,bus-freq = <9>;
+			qcom,bus-min = <9>;
+			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0x882d5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <827000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+			qcom,bus-freq = <9>;
+			qcom,bus-min = <7>;
+			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0xa82d5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <794000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+			qcom,bus-freq = <8>;
+			qcom,bus-min = <6>;
+			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0xa82d5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <746000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+			qcom,bus-freq = <7>;
+			qcom,bus-min = <5>;
+			qcom,bus-max = <8>;
+
+			qcom,acd-level = <0x882e5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <719000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+			qcom,bus-freq = <7>;
+			qcom,bus-min = <5>;
+			qcom,bus-max = <8>;
+
+			qcom,acd-level = <0x882e5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <680000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+			qcom,bus-freq = <7>;
+			qcom,bus-min = <5>;
+			qcom,bus-max = <8>;
+
+			qcom,acd-level = <0x882e5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
+			qcom,gpu-freq = <615000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+			qcom,bus-freq = <6>;
+			qcom,bus-min = <3>;
+			qcom,bus-max = <7>;
+
+			qcom,acd-level = <0xa82f5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@7 {
+			reg = <7>;
+			qcom,gpu-freq = <550000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <2>;
+			qcom,bus-max = <7>;
+
+			qcom,acd-level = <0xe0285ffd>;
+		};
+
+		qcom,gpu-pwrlevel@8 {
+			reg = <8>;
+			qcom,gpu-freq = <475000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <5>;
+
+			qcom,acd-level = <0xe0285ffd>;
+		};
+
+		qcom,gpu-pwrlevel@9 {
+			reg = <9>;
+			qcom,gpu-freq = <401000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <4>;
+
+			qcom,acd-level = <0xc02a5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@10 {
+			reg = <10>;
+			qcom,gpu-freq = <348000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <3>;
+
+			qcom,acd-level = <0xe02b5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@11 {
+			reg = <11>;
+			qcom,gpu-freq = <295000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <3>;
+
+			qcom,acd-level = <0xe02d5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@12 {
+			reg = <12>;
+			qcom,gpu-freq = <220000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+			qcom,bus-freq = <1>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <3>;
+
+			qcom,acd-level = <0xc02f5ffd>;
+		};
+	};
+};
+
diff --git a/gpu/kalamap-hhg-gpu.dts b/gpu/kalamap-hhg-gpu.dts
index 13273df..c846622 100755
--- a/gpu/kalamap-hhg-gpu.dts
+++ b/gpu/kalamap-hhg-gpu.dts
@@ -11,12 +11,12 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "kalama-v2-gpu.dtsi"
-#include "kalama-hhg-gpu-pwrlevels.dtsi"
+#include "kalamap-hhg-gpu-pwrlevels.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Kalama HHG";
 	compatible = "qcom,kalamap-hhg";
-	qcom,msm-id = <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <601 0x20000>;
 	qcom,board-id = <0 0>;
 };
 
diff --git a/gpu/khaje-gpu.dts b/gpu/khaje-gpu.dts
index ccc520b..f9276eb 100755
--- a/gpu/khaje-gpu.dts
+++ b/gpu/khaje-gpu.dts
@@ -17,7 +17,7 @@
 	model = "Qualcomm Technologies, Inc. Khaje SoC";
 	compatible = "qcom,khaje", "qcom,khaje-qrd",
 			"qcom,khaje-atp", "qcom,khaje-idp";
-	qcom,msm-id = <518 0x10000>;
+	qcom,msm-id = <518 0x10000>, <586 0x10000>;
 	qcom,board-id = <0 0>;
 };
 
diff --git a/gpu/lemans-gpu.dts b/gpu/lemans-gpu.dts
new file mode 100755
index 0000000..8486802
--- /dev/null
+++ b/gpu/lemans-gpu.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-lemans.h>
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gpucc-lemans.h>
+#include <dt-bindings/interconnect/qcom,epss-l3.h>
+#include <dt-bindings/interconnect/qcom,lemans.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interconnect/qcom,epss-l3.h>
+
+#include "lemans-gpu.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans SoC";
+	compatible = "qcom,lemans";
+	qcom,msm-id = <532 0x10000>, <533 0x10000>, <534 0x10000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/gpu/lemans-gpu.dtsi b/gpu/lemans-gpu.dtsi
new file mode 100755
index 0000000..fcebf05
--- /dev/null
+++ b/gpu/lemans-gpu.dtsi
@@ -0,0 +1,268 @@
+
+#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
+
+&msm_gpu {
+	compatible = "qcom,kgsl-3d0";
+	status = "ok";
+	reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
+		<0x3de0000 0x10000>, <0x4900000 0x80000>,
+		<0x3dff000 0x1000>;
+	reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
+		"qdss_gfx", "fusa";
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq";
+
+	clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+		<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+		<&gpucc GPU_CC_AHB_CLK>,
+		<&gpucc GPU_CC_CX_GMU_CLK>,
+		<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+		<&gpucc GPU_CC_HUB_AON_CLK>,
+		<&gpucc GPU_CC_HUB_CX_INT_CLK>;
+	clock-names = "gcc_gpu_memnoc_gfx",
+			"gcc_gpu_snoc_dvm_gfx",
+			"gpu_cc_ahb",
+			"gpu_cc_cx_gmu",
+			"gpu_cc_hlos1_vote_gpu_smmu",
+			"gpu_cc_hub_aon",
+			"gpu_cc_hub_cx_int";
+
+	qcom,chipid = <0x06060300>;
+
+	qcom,initial-pwrlevel = <2>;
+
+	qcom,no-nap;
+
+	qcom,highest-bank-bit = <16>;
+
+	qcom,min-access-length = <32>;
+
+	qcom,ubwc-mode = <4>;
+
+	qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
+
+	nvmem-cells = <&gpu_speed_bin>;
+	nvmem-cell-names = "speed_bin";
+
+	qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
+
+	interconnect-names = "gpu_icc_path";
+	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+
+	qcom,bus-table-ddr7 =
+		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
+		<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
+		<MHZ_TO_KBPS(451, 4)>,  /* index=2  */
+		<MHZ_TO_KBPS(547, 4)>,  /* index=3  */
+		<MHZ_TO_KBPS(681, 4)>,  /* index=4  */
+		<MHZ_TO_KBPS(768, 4)>,  /* index=5  */
+		<MHZ_TO_KBPS(1017, 4)>, /* index=6  */
+		<MHZ_TO_KBPS(1353, 4)>, /* index=7  */
+		<MHZ_TO_KBPS(1555, 4)>, /* index=8  */
+		<MHZ_TO_KBPS(1708, 4)>, /* index=9  */
+		<MHZ_TO_KBPS(2092, 4)>, /* index=10  */
+		<MHZ_TO_KBPS(2133, 4)>; /* index=11  */
+
+
+	qcom,bus-table-ddr8 =
+		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
+		<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
+		<MHZ_TO_KBPS(451, 4)>,  /* index=2  */
+		<MHZ_TO_KBPS(547, 4)>,  /* index=3  */
+		<MHZ_TO_KBPS(681, 4)>,  /* index=4  */
+		<MHZ_TO_KBPS(768, 4)>,  /* index=5  */
+		<MHZ_TO_KBPS(1017, 4)>, /* index=6  */
+		<MHZ_TO_KBPS(1555, 4)>, /* index=7  */
+		<MHZ_TO_KBPS(1708, 4)>, /* index=8  */
+		<MHZ_TO_KBPS(2092, 4)>, /* index=9  */
+		<MHZ_TO_KBPS(2736, 4)>, /* index=10  */
+		<MHZ_TO_KBPS(3196, 4)>; /* index=11  */
+
+	qcom,bus-table-cnoc =
+		<0>,   /* Off */
+		<100>; /* On */
+
+	qcom,l3-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,l3-pwrlevels";
+
+		qcom,l3-pwrlevel@0 {
+			reg = <0>;
+			qcom,l3-freq = <0>;
+		};
+
+		qcom,l3-pwrlevel@1 {
+			reg = <1>;
+			qcom,l3-freq = <614400000>;
+		};
+
+		qcom,l3-pwrlevel@2 {
+			reg = <2>;
+			qcom,l3-freq = <1516800000>;
+		};
+	};
+
+	zap-shader {
+		memory-region = <&pil_gpu_mem>;
+	};
+
+	qcom,gpu-mempools {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,gpu-mempools";
+
+		/* 4K Page Pool configuration */
+		qcom,gpu-mempool@0 {
+			reg = <0>;
+			qcom,mempool-page-size = <4096>;
+			qcom,mempool-reserved = <2048>;
+		};
+		/* 8K Page Pool configuration */
+		qcom,gpu-mempool@1 {
+			reg = <1>;
+			qcom,mempool-page-size = <8192>;
+			qcom,mempool-reserved = <1024>;
+		};
+		/* 64K Page Pool configuration */
+		qcom,gpu-mempool@2 {
+			reg = <2>;
+			qcom,mempool-page-size = <65536>;
+			qcom,mempool-reserved = <256>;
+		};
+		/* 128K Page Pool configuration */
+		qcom,gpu-mempool@3 {
+			reg = <3>;
+			qcom,mempool-page-size = <131072>;
+			qcom,mempool-reserved = <128>;
+		};
+		/* 256K Page Pool configuration */
+		qcom,gpu-mempool@4 {
+			reg = <4>;
+			qcom,mempool-page-size = <262144>;
+			qcom,mempool-reserved = <80>;
+		};
+		/* 1M Page Pool configuration */
+		qcom,gpu-mempool@5 {
+			reg = <5>;
+			qcom,mempool-page-size = <1048576>;
+			qcom,mempool-reserved = <32>;
+		};
+	};
+
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels";
+
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <840000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+			qcom,bus-freq-ddr7 = <11>;
+			qcom,bus-min-ddr7 = <11>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <11>;
+			qcom,bus-min-ddr8 = <11>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <778000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+			qcom,bus-freq-ddr7 = <11>;
+			qcom,bus-min-ddr7 = <11>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <10>;
+			qcom,bus-min-ddr8 = <10>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <676000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+			qcom,bus-freq-ddr7 = <8>;
+			qcom,bus-min-ddr7 = <7>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <7>;
+			qcom,bus-min-ddr8 = <7>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+	};
+};
+
+&soc {
+	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+		compatible = "qcom,kgsl-smmu-v2";
+		reg = <0x03da0000 0x20000>;
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+
+		gfx3d_user: gfx3d_user {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x0 0xc00>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_lpac: gfx3d_lpac {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x1 0xc00>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_secure: gfx3d_secure {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x2 0xc00>;
+			qcom,iommu-dma = "disabled";
+		};
+	};
+
+	gmu: qcom,gmu@3d69000 {
+		compatible = "qcom,gpu-gmu";
+
+		reg = <0x3d6a000 0x34000>,
+			<0xb290000 0x10000>,
+			<0xb490000 0x10000>;
+
+		reg-names = "kgsl_gmu_reg",
+			"kgsl_gmu_pdc_cfg",
+			"kgsl_gmu_pdc_seq";
+
+		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+			<0 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
+
+		regulator-names = "vddcx", "vdd", "vdd-parent";
+
+		iommus = <&kgsl_smmu 0x5 0xc00>;
+		qcom,iommu-dma = "disabled";
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+		vdd-supply = <&gpu_cc_gx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_CXO_CLK>,
+			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&gpucc GPU_CC_AHB_CLK>,
+			<&gpucc GPU_CC_HUB_CX_INT_CLK>;
+
+		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+			"memnoc_clk", "ahb_clk", "hub_clk";
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+};
diff --git a/gpu/pineapple-gpu.dtsi b/gpu/pineapple-gpu.dtsi
index 8cd6dbf..c5dd9a5 100755
--- a/gpu/pineapple-gpu.dtsi
+++ b/gpu/pineapple-gpu.dtsi
@@ -14,10 +14,12 @@
 
 	clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 		<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
-		<&gpucc GPU_CC_AHB_CLK>;
+		<&gpucc GPU_CC_AHB_CLK>,
+		<&aoss_qmp QDSS_CLK>;
 	clock-names = "gcc_gpu_memnoc_gfx",
 			"gcc_gpu_snoc_dvm_gfx",
-			"gpu_cc_ahb";
+			"gpu_cc_ahb",
+			"apb_pclk";
 
 	qcom,gpu-model = "Adreno750";
 
@@ -73,8 +75,10 @@
 			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
 			qcom,bus-freq = <9>;
-			qcom,bus-min = <6>;
+			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0x882d5ffd>;
 		};
 		/* SVS_L2 */
 		qcom,gpu-pwrlevel@1 {
@@ -83,9 +87,10 @@
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
 			qcom,bus-freq = <7>;
-			qcom,bus-min = <6>;
+			qcom,bus-min = <5>;
 			qcom,bus-max = <9>;
 
+			qcom,acd-level = <0x882d5ffd>;
 		};
 		/* SVS_L1 */
 		qcom,gpu-pwrlevel@2 {
@@ -93,10 +98,11 @@
 			qcom,gpu-freq = <680000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
-			qcom,bus-freq = <6>;
+			qcom,bus-freq = <7>;
 			qcom,bus-min = <5>;
 			qcom,bus-max = <9>;
 
+			qcom,acd-level = <0xa82d5ffd>;
 		};
 		/* SVS */
 		qcom,gpu-pwrlevel@3 {
@@ -104,10 +110,11 @@
 			qcom,gpu-freq = <578000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
-			qcom,bus-freq = <3>;
-			qcom,bus-min = <2>;
+			qcom,bus-freq = <5>;
+			qcom,bus-min = <3>;
 			qcom,bus-max = <7>;
 
+			qcom,acd-level = <0x882e5ffd>;
 		};
 		/* Low_SVS */
 		qcom,gpu-pwrlevel@4 {
@@ -115,10 +122,11 @@
 			qcom,gpu-freq = <422000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
-			qcom,bus-freq = <3>;
-			qcom,bus-min = <1>;
-			qcom,bus-max = <4>;
+			qcom,bus-freq = <5>;
+			qcom,bus-min = <3>;
+			qcom,bus-max = <7>;
 
+			qcom,acd-level = <0xc02b5ffd>;
 		};
 		/* Low_SVS_D1 */
 		qcom,gpu-pwrlevel@5 {
@@ -128,7 +136,9 @@
 
 			qcom,bus-freq = <1>;
 			qcom,bus-min = <1>;
-			qcom,bus-max = <3>;
+			qcom,bus-max = <4>;
+
+			qcom,acd-level = <0xc02e5ffd>;
 		};
 	};
 
@@ -237,5 +247,63 @@
 		qcom,iommu-dma = "disabled";
 
 		qcom,ipc-core = <0x00400000 0x100000>;
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
+	coresight_cx_dgbc: qcom,gpu-coresight-cx {
+		compatible = "qcom,gpu-coresight-cx";
+
+		coresight-name = "coresight-gfx-cx";
+		coresight-atid = <52>;
+
+		out-ports {
+			port {
+				cx_dbgc_out_funnel_gfx: endpoint {
+					remote-endpoint =
+					  <&funnel_gfx_in_cx_dbgc>;
+				};
+			};
+		};
+	};
+
+	coresight_gx_dgbc: qcom,gpu-coresight-gx {
+		compatible = "qcom,gpu-coresight-gx";
+
+		coresight-name = "coresight-gfx";
+		coresight-atid = <53>;
+
+		out-ports {
+			port {
+				gx_dbgc_out_funnel_gfx: endpoint {
+					remote-endpoint =
+					  <&funnel_gfx_in_gx_dbgc>;
+				};
+			};
+		};
+	};
+};
+
+&funnel_gfx {
+	in-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			funnel_gfx_in_gx_dbgc: endpoint {
+			remote-endpoint =
+				<&gx_dbgc_out_funnel_gfx>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			funnel_gfx_in_cx_dbgc: endpoint {
+			remote-endpoint =
+				<&cx_dbgc_out_funnel_gfx>;
+			};
+		};
 	};
 };
diff --git a/gpu/sdmshrike-gpu.dtsi b/gpu/sdmshrike-gpu.dtsi
index fd534b3..b278d45 100755
--- a/gpu/sdmshrike-gpu.dtsi
+++ b/gpu/sdmshrike-gpu.dtsi
@@ -1,184 +1,184 @@
 
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
 
-&soc {
-	msm_gpu: qcom,kgsl-3d0@2c00000 {
-		label = "kgsl-3d0";
-		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
-		status = "ok";
-		reg = <0x2c00000 0x40000>, <0x780000 0x6fff>;
-		reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
+&msm_gpu {
+	label = "kgsl-3d0";
+	compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+	status = "ok";
+	reg = <0x2c00000 0x40000>, <0x780000 0x6fff>;
+	reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
 
-		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "kgsl_3d0_irq";
-		qcom,id = <0>;
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq";
+	qcom,id = <0>;
 
-		qcom,chipid = <0x6080000>;
+	qcom,chipid = <0x6080000>;
 
-		qcom,initial-pwrlevel = <5>;
+	qcom,initial-pwrlevel = <5>;
 
-		qcom,gpu-quirk-secvid-set-once;
-		qcom,gpu-quirk-cx-gdsc;
+	qcom,gpu-quirk-secvid-set-once;
+	qcom,gpu-quirk-cx-gdsc;
 
-		qcom,idle-timeout = <80>; /* msecs */
-		qcom,no-nap;
+	qcom,idle-timeout = <80>; /* msecs */
+	qcom,no-nap;
 
-		qcom,highest-bank-bit = <16>;
+	qcom,highest-bank-bit = <16>;
 
-		qcom,min-access-length = <32>;
+	qcom,min-access-length = <32>;
 
-		qcom,ubwc-mode = <3>;
+	qcom,ubwc-mode = <3>;
 
-		qcom,macrotiling-channels = <8>;
+	qcom,macrotiling-channels = <8>;
 
-		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
+	qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
 
-		#cooling-cells = <2>;
+	#cooling-cells = <2>;
 
-		clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
-			<&gpucc GPU_CC_CXO_CLK>,
-			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
-			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
-			<&gpucc GPU_CC_CX_GMU_CLK>,
-			<&gpucc GPU_CC_AHB_CLK>;
+	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+		<&gpucc GPU_CC_CXO_CLK>,
+		<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+		<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+		<&gpucc GPU_CC_CX_GMU_CLK>,
+		<&gpucc GPU_CC_AHB_CLK>;
 
-		clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
-					"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
-					"gmu_clk", "gpu_cc_ahb";
+	clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
+				"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
+				"gmu_clk", "gpu_cc_ahb";
 
-		qcom,isense-clk-on-level = <1>;
+	qcom,isense-clk-on-level = <1>;
 
-		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
-		interconnect-names = "gpu_icc_path";
+	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+	interconnect-names = "gpu_icc_path";
 
-		qcom,bus-table-ddr =
-			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
-			<MHZ_TO_KBPS(100, 4)>,  /* index=1  */
-			<MHZ_TO_KBPS(150, 4)>,  /* index=2  */
-			<MHZ_TO_KBPS(200, 4)>,  /* index=3  */
-			<MHZ_TO_KBPS(300, 4)>,  /* index=4  */
-			<MHZ_TO_KBPS(412, 4)>,  /* index=5  */
-			<MHZ_TO_KBPS(547, 4)>, /* index=6  */
-			<MHZ_TO_KBPS(681, 4)>, /* index=7  */
-			<MHZ_TO_KBPS(768, 4)>, /* index=8  */
-			<MHZ_TO_KBPS(1017, 4)>, /* index=9  */
-			<MHZ_TO_KBPS(1296, 4)>, /* index=10  */
-			<MHZ_TO_KBPS(1555, 4)>, /* index=11  */
-			<MHZ_TO_KBPS(1804, 4)>; /* index=12  */
+	qcom,bus-table-ddr =
+		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
+		<MHZ_TO_KBPS(100, 4)>,  /* index=1  */
+		<MHZ_TO_KBPS(150, 4)>,  /* index=2  */
+		<MHZ_TO_KBPS(200, 4)>,  /* index=3  */
+		<MHZ_TO_KBPS(300, 4)>,  /* index=4  */
+		<MHZ_TO_KBPS(412, 4)>,  /* index=5  */
+		<MHZ_TO_KBPS(547, 4)>, /* index=6  */
+		<MHZ_TO_KBPS(681, 4)>, /* index=7  */
+		<MHZ_TO_KBPS(768, 4)>, /* index=8  */
+		<MHZ_TO_KBPS(1017, 4)>, /* index=9  */
+		<MHZ_TO_KBPS(1296, 4)>, /* index=10  */
+		<MHZ_TO_KBPS(1555, 4)>, /* index=11  */
+		<MHZ_TO_KBPS(1804, 4)>; /* index=12  */
 
-		qcom,bus-table-cnoc =
-			<0>,   /* Off */
-			<100>; /* On */
+	qcom,bus-table-cnoc =
+		<0>,   /* Off */
+		<100>; /* On */
 
 
-		/* GDSC regulator names */
-		regulator-names = "vddcx", "vdd";
-		/* GDSC oxili regulators */
-		vddcx-supply = <&gpu_cx_gdsc>;
-		vdd-supply = <&gpu_gx_gdsc>;
+	/* GDSC regulator names */
+	regulator-names = "vddcx", "vdd";
+	/* GDSC oxili regulators */
+	vddcx-supply = <&gpu_cx_gdsc>;
+	vdd-supply = <&gpu_gx_gdsc>;
+
+	zap-shader {
+		memory-region = <&gpu_micro_code_mem>;
+	};
+
 
-		zap-shader {
-			memory-region = <&gpu_micro_code_mem>;
+	/* GPU Mempools */
+	qcom,gpu-mempools {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,gpu-mempools";
+
+		/* 4K Page Pool configuration */
+		qcom,gpu-mempool@0 {
+			reg = <0>;
+			qcom,mempool-page-size = <4096>;
+			qcom,mempool-reserved = <2048>;
+			qcom,mempool-allocate;
+		};
+		/* 8K Page Pool configuration */
+		qcom,gpu-mempool@1 {
+			reg = <1>;
+			qcom,mempool-page-size = <8192>;
+			qcom,mempool-reserved = <1024>;
+			qcom,mempool-allocate;
+		};
+		/* 64K Page Pool configuration */
+		qcom,gpu-mempool@2 {
+			reg = <2>;
+			qcom,mempool-page-size = <65536>;
+			qcom,mempool-reserved = <256>;
 		};
+		/* 1M Page Pool configuration */
+		qcom,gpu-mempool@3 {
+			reg = <3>;
+			qcom,mempool-page-size = <1048576>;
+			qcom,mempool-reserved = <32>;
+		};
+	};
+
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels";
 
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <514000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+			qcom,bus-freq = <12>;
+			qcom,bus-min = <11>;
+			qcom,bus-max = <12>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <500000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+			qcom,bus-freq = <12>;
+			qcom,bus-min = <10>;
+			qcom,bus-max = <12>;
+		};
 
-		/* GPU Mempools */
-		qcom,gpu-mempools {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "qcom,gpu-mempools";
-
-			/* 4K Page Pool configuration */
-			qcom,gpu-mempool@0 {
-				reg = <0>;
-				qcom,mempool-page-size = <4096>;
-				qcom,mempool-reserved = <2048>;
-				qcom,mempool-allocate;
-			};
-			/* 8K Page Pool configuration */
-			qcom,gpu-mempool@1 {
-				reg = <1>;
-				qcom,mempool-page-size = <8192>;
-				qcom,mempool-reserved = <1024>;
-				qcom,mempool-allocate;
-			};
-			/* 64K Page Pool configuration */
-			qcom,gpu-mempool@2 {
-				reg = <2>;
-				qcom,mempool-page-size = <65536>;
-				qcom,mempool-reserved = <256>;
-			};
-			/* 1M Page Pool configuration */
-			qcom,gpu-mempool@3 {
-				reg = <3>;
-				qcom,mempool-page-size = <1048576>;
-				qcom,mempool-reserved = <32>;
-			};
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <461000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <9>;
+			qcom,bus-max = <11>;
 		};
 
-		/* Power levels */
-		qcom,gpu-pwrlevels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			compatible = "qcom,gpu-pwrlevels";
-
-			qcom,gpu-pwrlevel@0 {
-				reg = <0>;
-				qcom,gpu-freq = <514000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
-				qcom,bus-freq = <12>;
-				qcom,bus-min = <11>;
-				qcom,bus-max = <12>;
-			};
-
-			qcom,gpu-pwrlevel@1 {
-				reg = <1>;
-				qcom,gpu-freq = <500000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
-				qcom,bus-freq = <12>;
-				qcom,bus-min = <10>;
-				qcom,bus-max = <12>;
-			};
-
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
-				qcom,gpu-freq = <461000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
-				qcom,bus-freq = <10>;
-				qcom,bus-min = <9>;
-				qcom,bus-max = <11>;
-			};
-
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
-				qcom,gpu-freq = <405000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
-				qcom,bus-freq = <9>;
-				qcom,bus-min = <8>;
-				qcom,bus-max = <10>;
-			};
-
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
-				qcom,gpu-freq = <315000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
-				qcom,bus-freq = <8>;
-				qcom,bus-min = <7>;
-				qcom,bus-max = <9>;
-			};
-
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
-				qcom,gpu-freq = <0>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
-				qcom,bus-freq = <0>;
-				qcom,bus-min = <0>;
-				qcom,bus-max = <0>;
-			};
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <405000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+			qcom,bus-freq = <9>;
+			qcom,bus-min = <8>;
+			qcom,bus-max = <10>;
+		};
+
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <315000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			qcom,bus-freq = <8>;
+			qcom,bus-min = <7>;
+			qcom,bus-max = <9>;
+		};
+
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <0>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+			qcom,bus-freq = <0>;
+			qcom,bus-min = <0>;
+			qcom,bus-max = <0>;
 		};
 	};
+};
 
+&soc {
 	kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 {
 		compatible = "qcom,kgsl-smmu-v2";
 
diff --git a/gpu/sm8150-gpu.dtsi b/gpu/sm8150-gpu.dtsi
index 22ef87f..3dc142d 100755
--- a/gpu/sm8150-gpu.dtsi
+++ b/gpu/sm8150-gpu.dtsi
@@ -1,222 +1,220 @@
 
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
 
-&soc {
-
-	msm_gpu: qcom,kgsl-3d0@2c00000 {
-		label = "kgsl-3d0";
-		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
-		status = "ok";
-		reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,
-				<0x6900000 0x44000>, <0x780000 0x6fff>;
-		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
-					"qdss_gfx", "qfprom_memory";
-		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "kgsl_3d0_irq";
-		qcom,id = <0>;
-
-		qcom,chipid = <0x06040000>;
-
-		qcom,initial-pwrlevel = <5>;
+&msm_gpu {
+	label = "kgsl-3d0";
+	compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+	status = "ok";
+	reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,
+			<0x6900000 0x44000>, <0x780000 0x6fff>;
+	reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
+				"qdss_gfx", "qfprom_memory";
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq";
+	qcom,id = <0>;
+
+	qcom,chipid = <0x06040000>;
+
+	qcom,initial-pwrlevel = <5>;
+
+	qcom,gpu-quirk-secvid-set-once;
+	qcom,gpu-quirk-cx-gdsc;
+
+	qcom,idle-timeout = <80>; //msecs
+	qcom,no-nap;
+
+	qcom,highest-bank-bit = <15>;
+
+	qcom,min-access-length = <32>;
+
+	qcom,ubwc-mode = <3>;
+
+	qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
+
+	#cooling-cells = <2>;
+
+	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+		<&gpucc GPU_CC_CXO_CLK>,
+		<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+		<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+		<&gpucc GPU_CC_CX_GMU_CLK>,
+		<&gpucc GPU_CC_AHB_CLK>;
+
+	clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
+				"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
+				"gmu_clk", "gpu_cc_ahb";
+
+	qcom,isense-clk-on-level = <1>;
+
+	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+	interconnect-names = "gpu_icc_path";
+
+	qcom,bus-table-ddr =
+		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
+		<MHZ_TO_KBPS(100, 4)>,  /* index=1  */
+		<MHZ_TO_KBPS(150, 4)>,  /* index=2  */
+		<MHZ_TO_KBPS(200, 4)>,  /* index=3  */
+		<MHZ_TO_KBPS(300, 4)>,  /* index=4  */
+		<MHZ_TO_KBPS(412, 4)>,  /* index=5  */
+		<MHZ_TO_KBPS(547, 4)>, /* index=6  */
+		<MHZ_TO_KBPS(681, 4)>, /* index=7  */
+		<MHZ_TO_KBPS(768, 4)>, /* index=8  */
+		<MHZ_TO_KBPS(1017, 4)>, /* index=9  */
+		<MHZ_TO_KBPS(1296, 4)>, /* index=10  */
+		<MHZ_TO_KBPS(1555, 4)>, /* index=11  */
+		<MHZ_TO_KBPS(1804, 4)>; /* index=12  */
+
+	qcom,bus-table-cnoc =
+		<0>,   /* Off */
+		<100>; /* On */
+
+
+	/* GDSC regulator names */
+	regulator-names = "vddcx", "vdd";
+	/* GDSC oxili regulators */
+	vddcx-supply = <&gpu_cx_gdsc>;
+	vdd-supply = <&gpu_gx_gdsc>;
+
+	zap-shader {
+		memory-region = <&gpu_micro_code_mem>;
+	};
 
-		qcom,gpu-quirk-secvid-set-once;
-		qcom,gpu-quirk-cx-gdsc;
+	qcom,l3-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		qcom,idle-timeout = <80>; //msecs
-		qcom,no-nap;
+		compatible = "qcom,l3-pwrlevels";
 
-		qcom,highest-bank-bit = <15>;
+		qcom,l3-pwrlevel@0 {
+			reg = <0>;
+			qcom,l3-freq = <0>;
+		};
 
-		qcom,min-access-length = <32>;
+		qcom,l3-pwrlevel@1 {
+			reg = <1>;
+			qcom,l3-freq = <864000000>;
+		};
 
-		qcom,ubwc-mode = <3>;
+		qcom,l3-pwrlevel@2 {
+			reg = <2>;
+			qcom,l3-freq = <1344000000>;
+		};
+	};
 
-		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
+	/* GPU Mempools */
+	qcom,gpu-mempools {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,gpu-mempools";
+
+		/* 4K Page Pool configuration */
+		qcom,gpu-mempool@0 {
+			reg = <0>;
+			qcom,mempool-page-size = <4096>;
+			qcom,mempool-reserved = <2048>;
+			qcom,mempool-allocate;
+		};
+		/* 8K Page Pool configuration */
+		qcom,gpu-mempool@1 {
+			reg = <1>;
+			qcom,mempool-page-size = <8192>;
+			qcom,mempool-reserved = <1024>;
+			qcom,mempool-allocate;
+		};
+		/* 64K Page Pool configuration */
+		qcom,gpu-mempool@2 {
+			reg = <2>;
+			qcom,mempool-page-size = <65536>;
+			qcom,mempool-reserved = <256>;
+		};
+		/* 1M Page Pool configuration */
+		qcom,gpu-mempool@3 {
+			reg = <3>;
+			qcom,mempool-page-size = <1048576>;
+			qcom,mempool-reserved = <32>;
+		};
+	};
 
-		#cooling-cells = <2>;
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
-			<&gpucc GPU_CC_CXO_CLK>,
-			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
-			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
-			<&gpucc GPU_CC_CX_GMU_CLK>,
-			<&gpucc GPU_CC_AHB_CLK>;
+		compatible = "qcom,gpu-pwrlevels";
 
-		clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
-					"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
-					"gmu_clk", "gpu_cc_ahb";
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <600000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
 
-		qcom,isense-clk-on-level = <1>;
+			qcom,bus-freq = <12>;
+			qcom,bus-min = <10>;
+			qcom,bus-max = <12>;
+		};
 
-		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
-		interconnect-names = "gpu_icc_path";
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <553850000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
-		qcom,bus-table-ddr =
-			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
-			<MHZ_TO_KBPS(100, 4)>,  /* index=1  */
-			<MHZ_TO_KBPS(150, 4)>,  /* index=2  */
-			<MHZ_TO_KBPS(200, 4)>,  /* index=3  */
-			<MHZ_TO_KBPS(300, 4)>,  /* index=4  */
-			<MHZ_TO_KBPS(412, 4)>,  /* index=5  */
-			<MHZ_TO_KBPS(547, 4)>, /* index=6  */
-			<MHZ_TO_KBPS(681, 4)>, /* index=7  */
-			<MHZ_TO_KBPS(768, 4)>, /* index=8  */
-			<MHZ_TO_KBPS(1017, 4)>, /* index=9  */
-			<MHZ_TO_KBPS(1296, 4)>, /* index=10  */
-			<MHZ_TO_KBPS(1555, 4)>, /* index=11  */
-			<MHZ_TO_KBPS(1804, 4)>; /* index=12  */
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <9>;
+			qcom,bus-max = <11>;
+		};
 
-		qcom,bus-table-cnoc =
-			<0>,   /* Off */
-			<100>; /* On */
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <486460000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
+			qcom,bus-freq = <9>;
+			qcom,bus-min = <8>;
+			qcom,bus-max = <10>;
+		};
 
-		/* GDSC regulator names */
-		regulator-names = "vddcx", "vdd";
-		/* GDSC oxili regulators */
-		vddcx-supply = <&gpu_cx_gdsc>;
-		vdd-supply = <&gpu_gx_gdsc>;
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <379650000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
-		zap-shader {
-			memory-region = <&gpu_micro_code_mem>;
+			qcom,bus-freq = <8>;
+			qcom,bus-min = <7>;
+			qcom,bus-max = <9>;
 		};
 
-		qcom,l3-pwrlevels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			compatible = "qcom,l3-pwrlevels";
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <309110000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
-			qcom,l3-pwrlevel@0 {
-				reg = <0>;
-				qcom,l3-freq = <0>;
-			};
+			qcom,bus-freq = <5>;
+			qcom,bus-min = <5>;
+			qcom,bus-max = <7>;
+		};
 
-			qcom,l3-pwrlevel@1 {
-				reg = <1>;
-				qcom,l3-freq = <864000000>;
-			};
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <215000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
-			qcom,l3-pwrlevel@2 {
-				reg = <2>;
-				qcom,l3-freq = <1344000000>;
-			};
+			qcom,bus-freq = <4>;
+			qcom,bus-min = <3>;
+			qcom,bus-max = <5>;
 		};
 
-		/* GPU Mempools */
-		qcom,gpu-mempools {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "qcom,gpu-mempools";
-
-			/* 4K Page Pool configuration */
-			qcom,gpu-mempool@0 {
-				reg = <0>;
-				qcom,mempool-page-size = <4096>;
-				qcom,mempool-reserved = <2048>;
-				qcom,mempool-allocate;
-			};
-			/* 8K Page Pool configuration */
-			qcom,gpu-mempool@1 {
-				reg = <1>;
-				qcom,mempool-page-size = <8192>;
-				qcom,mempool-reserved = <1024>;
-				qcom,mempool-allocate;
-			};
-			/* 64K Page Pool configuration */
-			qcom,gpu-mempool@2 {
-				reg = <2>;
-				qcom,mempool-page-size = <65536>;
-				qcom,mempool-reserved = <256>;
-			};
-			/* 1M Page Pool configuration */
-			qcom,gpu-mempool@3 {
-				reg = <3>;
-				qcom,mempool-page-size = <1048576>;
-				qcom,mempool-reserved = <32>;
-			};
-		};
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
+			qcom,gpu-freq = <0>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 
-		/* Power levels */
-		qcom,gpu-pwrlevels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			compatible = "qcom,gpu-pwrlevels";
-
-			qcom,gpu-pwrlevel@0 {
-				reg = <0>;
-				qcom,gpu-freq = <600000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
-
-				qcom,bus-freq = <12>;
-				qcom,bus-min = <10>;
-				qcom,bus-max = <12>;
-			};
-
-			qcom,gpu-pwrlevel@1 {
-				reg = <1>;
-				qcom,gpu-freq = <553850000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
-
-				qcom,bus-freq = <10>;
-				qcom,bus-min = <9>;
-				qcom,bus-max = <11>;
-			};
-
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
-				qcom,gpu-freq = <486460000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
-
-				qcom,bus-freq = <9>;
-				qcom,bus-min = <8>;
-				qcom,bus-max = <10>;
-			};
-
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
-				qcom,gpu-freq = <379650000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
-
-				qcom,bus-freq = <8>;
-				qcom,bus-min = <7>;
-				qcom,bus-max = <9>;
-			};
-
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
-				qcom,gpu-freq = <309110000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
-
-				qcom,bus-freq = <5>;
-				qcom,bus-min = <5>;
-				qcom,bus-max = <7>;
-			};
-
-			qcom,gpu-pwrlevel@5 {
-				reg = <5>;
-				qcom,gpu-freq = <215000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
-
-				qcom,bus-freq = <4>;
-				qcom,bus-min = <3>;
-				qcom,bus-max = <5>;
-			};
-
-			qcom,gpu-pwrlevel@6 {
-				reg = <6>;
-				qcom,gpu-freq = <0>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
-
-				qcom,bus-freq = <0>;
-				qcom,bus-min = <0>;
-				qcom,bus-max = <0>;
-			};
+			qcom,bus-freq = <0>;
+			qcom,bus-min = <0>;
+			qcom,bus-max = <0>;
 		};
-
 	};
+};
 
+&soc {
 	kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 {
 		compatible = "qcom,kgsl-smmu-v2";