diff options
| author | Sunil Paidimarri <hisunil@codeaurora.org> | 2019-02-20 15:24:04 -0800 |
|---|---|---|
| committer | Suraj Jaiswal <jsuraj@codeaurora.org> | 2019-10-25 14:55:33 +0530 |
| commit | bd481c874268930832bfad2f20f5664ac04ef3c6 (patch) | |
| tree | 64a0a5bf0050533deb8539cb60fae382479a69c9 | |
| parent | f4484b690e53142b4ac4721cd0236777798ac85c (diff) | |
| download | data-kernel-bd481c874268930832bfad2f20f5664ac04ef3c6.tar.gz | |
data-kernel: EMAC: Fix required PTP clock for accuracy
Fix the required PTP clock for accuracy.the
Fix sub_second_increment and addend configuration.
Change-Id: Ib2b68529d689c1d8c84aadf6a456df0abc77af8b
Acked-by: Rahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
| -rw-r--r-- | drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c | 2 | ||||
| -rw-r--r-- | drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c | 27 | ||||
| -rw-r--r-- | drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h | 2 |
3 files changed, 16 insertions, 15 deletions
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c index 4d5d51f..b5facb6 100644 --- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c +++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c @@ -1156,7 +1156,7 @@ static INT config_sub_second_increment(ULONG ptp_clock) } #else if (GET_VALUE(VARMAC_TCR, MAC_TCR_TSCFUPDT_LPOS, MAC_TCR_TSCFUPDT_HPOS) == 1) { - val = ((1 * 1000000000ull) / 50000000); + val = ((1 * 1000000000ull) / DWC_ETH_QOS_DEFAULT_PTP_CLOCK); } else { val = ((1 * 1000000000ull) / ptp_clock); diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c index 730d9fc..738f2e9 100644 --- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c +++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c @@ -4930,8 +4930,8 @@ static VOID DWC_ETH_QOS_config_timer_registers( #ifdef CONFIG_PPS_OUTPUT /* If default_addend is already programmed, then we expect that * sub_second_increment is also programmed already */ - if(pdata->default_addend == 0){ - hw_if->config_sub_second_increment(DWC_ETH_QOS_SYSCLOCK); // Using default 250MHz + if(pdata->default_addend == 0){ + hw_if->config_sub_second_increment(DWC_ETH_QOS_DEFAULT_PTP_CLOCK); // Using default 50MHz } else { u64 pclk; @@ -4941,7 +4941,7 @@ static VOID DWC_ETH_QOS_config_timer_registers( hw_if->config_sub_second_increment((u32)pclk); } #else - hw_if->config_sub_second_increment(DWC_ETH_QOS_SYSCLOCK); + hw_if->config_sub_second_increment(DWC_ETH_QOS_DEFAULT_PTP_CLOCK); #endif /* formula is : * addend = 2^32/freq_div_ratio; @@ -4958,12 +4958,12 @@ static VOID DWC_ETH_QOS_config_timer_registers( */ #ifdef CONFIG_PPS_OUTPUT if(pdata->default_addend == 0){ - temp = (u64)(50000000ULL << 32); + temp = (u64)((u64)DWC_ETH_QOS_DEFAULT_PTP_CLOCK << 32); pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK); - EMACDBG("Using default PTP clock = 250MHz\n"); + EMACDBG("Using default PTP clock = 50MHz\n"); } #else - temp = (u64)(50000000ULL << 32); + temp = (u64)((u64)DWC_ETH_QOS_DEFAULT_PTP_CLOCK << 32); pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK); #endif hw_if->config_addend(pdata->default_addend); @@ -6061,7 +6061,7 @@ static int DWC_ETH_QOS_handle_hwtstamp_ioctl(struct DWC_ETH_QOS_prv_data *pdata, /* If default_addend is already programmed, then we expect that * sub_second_increment is also programmed already */ if (pdata->default_addend == 0) { - hw_if->config_sub_second_increment(DWC_ETH_QOS_SYSCLOCK); // Using default 250MHz + hw_if->config_sub_second_increment(DWC_ETH_QOS_DEFAULT_PTP_CLOCK); // Using default 50MHz } else { u64 pclk; pclk = (u64) (pdata->default_addend) * DWC_ETH_QOS_SYSCLOCK; @@ -6070,7 +6070,7 @@ static int DWC_ETH_QOS_handle_hwtstamp_ioctl(struct DWC_ETH_QOS_prv_data *pdata, hw_if->config_sub_second_increment((u32)pclk); } #else - hw_if->config_sub_second_increment(DWC_ETH_QOS_SYSCLOCK); + hw_if->config_sub_second_increment(DWC_ETH_QOS_DEFAULT_PTP_CLOCK); #endif /* formula is : * addend = 2^32/freq_div_ratio; @@ -6087,12 +6087,13 @@ static int DWC_ETH_QOS_handle_hwtstamp_ioctl(struct DWC_ETH_QOS_prv_data *pdata, * */ #ifdef CONFIG_PPS_OUTPUT - if(pdata->default_addend == 0){ - temp = (u64)(50000000ULL << 32); - pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK); - EMACINFO("Using default PTP clock = 250MHz\n"); + if(pdata->default_addend == 0){ + temp = (u64)((u64)DWC_ETH_QOS_DEFAULT_PTP_CLOCK << 32); + pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK); + EMACINFO("Using default PTP clock = 50MHz\n"); + } #else - temp = (u64)(50000000ULL << 32); + temp = (u64)((u64)DWC_ETH_QOS_DEFAULT_PTP_CLOCK << 32); pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK); #endif hw_if->config_addend(pdata->default_addend); diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h index 3db1b0a..23aca7c 100644 --- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h +++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h @@ -427,7 +427,7 @@ extern void *ipc_emac_log_ctxt; #define DWC_ETH_QOS_SYSCLOCK 250000000 /* System clock is 250MHz */ #define DWC_ETH_QOS_SYSTIMEPERIOD 4 /* System time period is 4ns */ -#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 250000000 +#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 50000000 #define DWC_ETH_QOS_TX_QUEUE_CNT (pdata->tx_queue_cnt) #define DWC_ETH_QOS_RX_QUEUE_CNT (pdata->rx_queue_cnt) |