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authorSuraj Jaiswal <jsuraj@codeaurora.org>2019-03-11 17:13:42 +0530
committerSuraj Jaiswal <jsuraj@codeaurora.org>2019-10-25 15:09:22 +0530
commit6f35b39a62679d40883b01f0a4958c32f36ca52b (patch)
treee333c0f2c3b0a129c06539fa61c0378d38e55b8a /drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
parente3cf542a4e0dd791d3e56d3325a9f9493d11f1c4 (diff)
downloaddata-kernel-6f35b39a62679d40883b01f0a4958c32f36ca52b.tar.gz
data-kernel: EMAC: PPS Timestamp method
This change add support to changed the timestamp update method to Fine timestamp update method instead of Coarse Timestamp Update method since on driver we are using Fine method as default. Also , we are chaniging default PTP clock to 96Mhz to generate 19.2Mhz PPS frequency. Change-Id: Id5c4a22c0163b64762422df0cb3f1e0154515f60
Diffstat (limited to 'drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h')
-rw-r--r--drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
index 67fdd03..ee29121 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
@@ -427,8 +427,8 @@ extern void *ipc_emac_log_ctxt;
#define DWC_ETH_QOS_SYSCLOCK 250000000 /* System clock is 250MHz */
#define DWC_ETH_QOS_SYSTIMEPERIOD 4 /* System time period is 4ns */
-#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 50000000
-#define DWC_ETH_QOS_DEFAULT_LPASS_CLOCK 250000000
+#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 96000000
+#define DWC_ETH_QOS_DEFAULT_LPASS_PPS_FREQUENCY 19200000
#define DWC_ETH_QOS_TX_QUEUE_CNT (pdata->tx_queue_cnt)
#define DWC_ETH_QOS_RX_QUEUE_CNT (pdata->rx_queue_cnt)
@@ -1006,6 +1006,7 @@ struct hw_if_struct {
/* for hw time stamping */
INT(*config_hw_time_stamping)(UINT);
INT(*config_sub_second_increment)(unsigned long ptp_clock);
+ INT(*config_default_addend)(struct DWC_ETH_QOS_prv_data *pdata, unsigned long ptp_clock);
INT(*init_systime)(UINT, UINT);
INT(*config_addend)(UINT);
INT(*adjust_systime)(UINT, UINT, INT, bool);