data-kernel : Add Micrel PHY WOL support in emac driver

Change-Id: I322cf143d509e34fc25d61b435d1570f7f305c5a
Acked-by: Nisha Menon <nmenon@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>

4 files changed, 19 insertions, 5 deletions

diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c
index 5519a79..0a0f59f 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -795,6 +795,10 @@ void DWC_ETH_QOS_handle_phy_interrupt(struct DWC_ETH_QOS_prv_data *pdata)
 	EMACDBG(
 		"MICREL PHY Intr EN Reg (%#x) = %#x\n", DWC_ETH_QOS_MICREL_PHY_INTCS, micrel_intr_status);
 
+	/* Call ack interrupt to clear the WOL interrupt status fields */
+	if (pdata->phydev->drv->ack_interrupt)
+		pdata->phydev->drv->ack_interrupt(pdata->phydev);
+
 	/* Interrupt received for link state change */
 	if (phy_intr_status & LINK_STATE_MASK) {
 		EMACDBG("Interrupt received for link UP state\n");
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_ipa.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_ipa.c
index 52a3639..ad6e863 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_ipa.c
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_ipa.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
@@ -967,6 +967,7 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata)
 	struct ipa_perf_profile profile;
 	int ret = 0;
 	int i = 0;
+	u32 reg_val;
 
 
 	EMACDBG("%s - begin\n", __func__);
@@ -1088,6 +1089,13 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata)
     /* Mapped RX queue 0 to DMA channel 0 on successful IPA offload connect */
     MTL_RQDCM0R_RGWR(0x3020100);
 
+	/* Mapped RX queue 0 to DMA channel 0 on successful IPA offload connect */
+	if (pdata->res_data->early_eth_en) {
+		MTL_RQDCM0R_RGRD(reg_val);
+		reg_val &= ~IPA_RX_TO_DMA_CH_MAP_NUM;
+		MTL_RQDCM0R_RGWR(reg_val);
+	}
+
     ntn_ipa->uc_db_rx_addr = out.u.ntn.ul_uc_db_pa;
     ntn_ipa->uc_db_tx_addr = out.u.ntn.dl_uc_db_pa;
 
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c b/drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c
index 620e6d0..51788d9 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c
@@ -2257,12 +2257,12 @@ static INT DWC_ETH_QOS_resume(struct platform_device *pdev)
 	struct DWC_ETH_QOS_prv_data *pdata = netdev_priv(dev);
 	INT ret;
 
-	DBGPR("-->DWC_ETH_QOS_resume\n");
+	EMACDBG("-->DWC_ETH_QOS_resume\n");
 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,emac-smmu-embedded"))
 		return 0;
 
 	if (!dev || !netif_running(dev)) {
-		DBGPR("<--DWC_ETH_QOS_dev_resume\n");
+		EMACERR("<--DWC_ETH_QOS_dev_resume not possible\n");
 		return -EINVAL;
 	}
 
@@ -2294,7 +2294,7 @@ static INT DWC_ETH_QOS_resume(struct platform_device *pdev)
 	/* Set a wakeup event to ensure enough time for processing */
 	pm_wakeup_event(&pdev->dev, 5000);
 
-	DBGPR("<--DWC_ETH_QOS_resume\n");
+	EMACDBG("<--DWC_ETH_QOS_resume\n");
 
 	return ret;
 }
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
index ce9e19b..a5ef61b 100644
--- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
+++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h
@@ -348,6 +348,7 @@ extern void *ipc_emac_log_ctxt;
 #define LINK_UP 1
 #define LINK_DOWN 0
 #define ENABLE_PHY_INTERRUPTS 0xcc00
+#define MICREL_LINK_UP_INTR_STATUS		BIT(0)
 
 /* Default MTL queue operation mode values */
 #define DWC_ETH_QOS_Q_DISABLED	0x0
@@ -658,6 +659,7 @@ extern void *ipc_emac_log_ctxt;
 #define IPA_DMA_TX_CH 0
 #define IPA_DMA_RX_CH 0
 
+#define IPA_RX_TO_DMA_CH_MAP_NUM	BIT(0);
 
 #define EMAC_GDSC_EMAC_NAME "gdsc_emac"
 #define EMAC_VREG_RGMII_NAME "vreg_rgmii"