diff options
Diffstat (limited to 'drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h')
| -rw-r--r-- | drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h | 58 |
1 files changed, 54 insertions, 4 deletions
diff --git a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h index adcade2..ee29121 100644 --- a/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h +++ b/drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights +/* Copyright (c) 2017-2019, The Linux Foundation. All rights * reserved. * * This program is free software; you can redistribute it and/or modify @@ -124,7 +124,15 @@ #include <linux/mailbox_client.h> #include <linux/mailbox/qmp.h> #include <linux/mailbox_controller.h> - +#include <linux/ipc_logging.h> +#include <linux/inetdevice.h> +#include <net/inet_common.h> +#include <net/ipv6.h> +#include <linux/inet.h> +#include <asm/uaccess.h> +#ifdef CONFIG_MSM_BOOT_TIME_MARKER +#include <soc/qcom/boot_stats.h> +#endif /* QOS Version Control Macros */ /* #define DWC_ETH_QOS_VER_4_0 */ /* Default Configuration is for QOS version 4.1 and above */ @@ -133,6 +141,13 @@ #include <asm-generic/errno.h> +extern void *ipc_emac_log_ctxt; + +#define IPCLOG_STATE_PAGES 50 +#define __FILENAME__ (strrchr(__FILE__, '/') ? \ + strrchr(__FILE__, '/') + 1 : __FILE__) + + #ifdef CONFIG_PGTEST_OBJ #define DWC_ETH_QOS_CONFIG_PGTEST #endif @@ -336,6 +351,7 @@ #define LINK_UP 1 #define LINK_DOWN 0 #define ENABLE_PHY_INTERRUPTS 0xcc00 +#define MICREL_LINK_UP_INTR_STATUS BIT(0) /* Default MTL queue operation mode values */ #define DWC_ETH_QOS_Q_DISABLED 0x0 @@ -362,6 +378,7 @@ "<error>")))) #define DWC_ETH_QOS_MAC_ADDR_LEN 6 +#define DWC_ETH_QOS_MAC_ADDR_STR_LEN 18 #ifndef DWC_ETH_QOS_ENABLE_VLAN_TAG #define VLAN_HLEN 0 #endif @@ -410,7 +427,8 @@ #define DWC_ETH_QOS_SYSCLOCK 250000000 /* System clock is 250MHz */ #define DWC_ETH_QOS_SYSTIMEPERIOD 4 /* System time period is 4ns */ -#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 250000000 +#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 96000000 +#define DWC_ETH_QOS_DEFAULT_LPASS_PPS_FREQUENCY 19200000 #define DWC_ETH_QOS_TX_QUEUE_CNT (pdata->tx_queue_cnt) #define DWC_ETH_QOS_RX_QUEUE_CNT (pdata->rx_queue_cnt) @@ -645,6 +663,7 @@ #define IPA_DMA_TX_CH 0 #define IPA_DMA_RX_CH 0 +#define IPA_RX_TO_DMA_CH_MAP_NUM BIT(0); #define EMAC_GDSC_EMAC_NAME "gdsc_emac" #define EMAC_VREG_RGMII_NAME "vreg_rgmii" @@ -987,6 +1006,7 @@ struct hw_if_struct { /* for hw time stamping */ INT(*config_hw_time_stamping)(UINT); INT(*config_sub_second_increment)(unsigned long ptp_clock); + INT(*config_default_addend)(struct DWC_ETH_QOS_prv_data *pdata, unsigned long ptp_clock); INT(*init_systime)(UINT, UINT); INT(*config_addend)(UINT); INT(*adjust_systime)(UINT, UINT, INT, bool); @@ -1546,6 +1566,9 @@ struct DWC_ETH_QOS_res_data { bool is_pinctrl_names; int gpio_phy_intr_redirect; int gpio_phy_reset; + struct pinctrl *pinctrl; + struct pinctrl_state *rgmii_rxc_suspend_state; + struct pinctrl_state *rgmii_rxc_resume_state; /* Regulators */ struct regulator *gdsc_emac; @@ -1559,6 +1582,8 @@ struct DWC_ETH_QOS_res_data { struct clk *rgmii_clk; struct clk *ptp_clk; unsigned int emac_hw_version_type; + bool early_eth_en; + bool pps_lpass_conn_en; }; struct DWC_ETH_QOS_prv_ipa_data { @@ -1851,7 +1876,21 @@ struct DWC_ETH_QOS_prv_data { dev_t avb_class_b_dev_t; struct cdev* avb_class_b_cdev; struct class* avb_class_b_class; + struct delayed_work ipv6_addr_assign_wq; + bool print_kpi; +}; +struct ip_params { + UCHAR mac_addr[DWC_ETH_QOS_MAC_ADDR_LEN]; + bool is_valid_mac_addr; + char link_speed[32]; + bool is_valid_link_speed; + char ipv4_addr_str[32]; + struct in_addr ipv4_addr; + bool is_valid_ipv4_addr; + char ipv6_addr_str[48]; + struct in6_ifreq ipv6_addr; + bool is_valid_ipv6_addr; }; typedef enum { @@ -2003,6 +2042,8 @@ void DWC_ETH_QOS_set_clk_and_bus_config(struct DWC_ETH_QOS_prv_data *pdata, int #define EMAC_PHY_RESET "dev-emac-phy_reset_state" #define EMAC_PHY_INTR "dev-emac-phy_intr" #define EMAC_PIN_PPS0 "dev-emac_pin_pps_0" +#define EMAC_RGMII_RXC_SUSPEND "dev-emac-rgmii_rxc_suspend_state" +#define EMAC_RGMII_RXC_RESUME "dev-emac-rgmii_rxc_resume_state" #ifdef PER_CH_INT void DWC_ETH_QOS_handle_DMA_Int(struct DWC_ETH_QOS_prv_data *pdata, int chinx, bool); @@ -2016,6 +2057,8 @@ irqreturn_t DWC_ETH_QOS_PHY_ISR(int irq, void *dev_id); void DWC_ETH_QOS_dma_desc_stats_read(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_dma_desc_stats_init(struct DWC_ETH_QOS_prv_data *pdata); +int DWC_ETH_QOS_add_ipaddr(struct DWC_ETH_QOS_prv_data *); +int DWC_ETH_QOS_add_ipv6addr(struct DWC_ETH_QOS_prv_data *); /* For debug prints*/ #define DRV_NAME "qcom-emac-dwc-eqos" @@ -2054,7 +2097,14 @@ do {\ #define EMACINFO(fmt, args...) \ pr_info(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) #define EMACERR(fmt, args...) \ - pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) +do {\ + pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipc_emac_log_ctxt) { \ + ipc_log_string(ipc_emac_log_ctxt, \ + "%s: %s[%u]:[emac] ERROR:" fmt, __FILENAME__ , \ + __func__, __LINE__, ## args); \ + } \ +}while(0) #ifdef YDEBUG #define DBGPR(x...) printk(KERN_ALERT x) |