OMAP4: DSS: Calculation of DSS overlay threshold

Based on the method given by HW team, low & high threshold is
calculated which is based on many pipeline specific configuration.
The appropriate configuration of threshold causes the DSS to stay
in STANDBY for maximum time thus saves power.

Change-Id: I5efe8c889c6fc5e39a372173b14ce404d85637e4
Signed-off-by: Sujeet Baranwal <s-baranwal@ti.com>

5 files changed, 579 insertions, 9 deletions

diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
index 1a27feb303c..d10b7b30252 100644
--- a/drivers/video/omap2/dss/Makefile
+++ b/drivers/video/omap2/dss/Makefile
@@ -1,5 +1,5 @@
 obj-$(CONFIG_OMAP2_DSS) += omapdss.o
-omapdss-y := core.o dss.o dispc.o display.o manager.o overlay.o wb.o
+omapdss-y := core.o dss.o dispc.o display.o manager.o overlay.o wb.o fifothreshold.o
 omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
 omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
 omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index edfab8baa03..ff39c878e88 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1135,6 +1135,70 @@ void dispc_restore_context(void)
 #undef SR
 #undef RR
 
+static u32 dispc_calculate_threshold(enum omap_plane plane, u32 paddr,
+				u32 puv_addr, u16 width, u16 height,
+				s32 row_inc, s32 pix_inc)
+{
+	int shift;
+	u32 channel_no = plane;
+	struct sa_struct sa_info;
+	u32 val, burstsize, doublestride;
+	u32 rotation, bursttype, color_mode;
+	struct dispc_config dispc_reg_config;
+
+	if (width >= 1920)
+		return 1500;
+
+	/* Get the burst size */
+	shift = (plane == OMAP_DSS_GFX) ? 6 : 14;
+	val = dispc_read_reg(dispc_reg_att[plane]);
+	burstsize = FLD_GET(val, shift + 1, shift);
+	doublestride = FLD_GET(val, 22, 22);
+	rotation = (plane == OMAP_DSS_WB) ? 0 : FLD_GET(val, 13, 12);
+	bursttype = (plane == OMAP_DSS_WB) ? 0 : FLD_GET(val, 29, 29);
+	color_mode = FLD_GET(val, 4, 1);
+
+	/* base address for frame (Luma frame in case of YUV420) */
+	dispc_reg_config.ba = paddr;
+	/* base address for Chroma frame in case of YUV420 */
+	dispc_reg_config.bacbcr = puv_addr;
+	/* OrgSizeX for frame */
+	dispc_reg_config.sizex = width;
+	/* OrgSizeY for frame */
+	dispc_reg_config.sizey = height;
+	/* burst size */
+	dispc_reg_config.burstsize = burstsize;
+	/* pixel increment */
+	dispc_reg_config.pixelinc = pix_inc;
+	/* row increment */
+	dispc_reg_config.rowinc  = row_inc;
+	/* burst type: 1D/2D */
+	dispc_reg_config.bursttype = bursttype;
+	/* chroma DoubleStride when in YUV420 format */
+	dispc_reg_config.doublestride = doublestride;
+	/* Pixcel format of the frame.*/
+	dispc_reg_config.format = color_mode;
+	/* Rotation of frame */
+	dispc_reg_config.rotation = rotation;
+
+	/* DMA buffer allications - assuming reset values */
+	dispc_reg_config.gfx_top_buffer = 0;
+	dispc_reg_config.gfx_bottom_buffer = 0;
+	dispc_reg_config.vid1_top_buffer = 1;
+	dispc_reg_config.vid1_bottom_buffer = 1;
+	dispc_reg_config.vid2_top_buffer = 2;
+	dispc_reg_config.vid2_bottom_buffer = 2;
+	dispc_reg_config.vid3_top_buffer = 3;
+	dispc_reg_config.vid3_bottom_buffer = 3;
+	dispc_reg_config.wb_top_buffer = 4;
+	dispc_reg_config.wb_bottom_buffer = 4;
+
+	/* antiFlicker is off */
+	dispc_reg_config.antiflicker = 0;
+
+	return sa_calc_wrap(&dispc_reg_config, channel_no, &sa_info);
+}
+
 static inline void enable_clocks(bool enable)
 {
 	if (enable)
@@ -3010,6 +3074,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	s32 pix_inc;
 	u16 frame_height = height;
 	unsigned int field_offset = 0;
+	u32 fifo_high, fifo_low;
 
 	if (paddr == 0)
 		return -EINVAL;
@@ -3326,6 +3391,13 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	if ((plane != OMAP_DSS_VIDEO1) || (cpu_is_omap44xx()))
 		_dispc_setup_global_alpha(plane, global_alpha);
 
+	if (cpu_is_omap44xx()) {
+		fifo_low = dispc_calculate_threshold(plane, paddr + offset0,
+					puv_addr + offset0, width, height,
+					row_inc, pix_inc);
+		fifo_high = dispc_get_plane_fifo_size(plane) - 1;
+		dispc_setup_plane_fifo(plane, fifo_low, fifo_high);
+	}
 	return 0;
 }
 
@@ -5124,13 +5196,9 @@ int dispc_setup_wb(struct writeback_cache_data *wb)
 	u16 width = wb->input_width;
 	u16 height = wb->input_height;
 	u32 lines_to_skip = wb->line_skip;
-
+	u32 fifo_low, fifo_high;
 	enum omap_color_mode color_mode = wb->color_mode;  /* output color */
-
-	u32 fifo_low = wb->fifo_low;
-	u32 fifo_high = wb->fifo_high;
 	enum omap_writeback_source			source = wb->source;
-
 	enum omap_plane plane = OMAP_DSS_WB;
 
 	const int maxdownscale = 2;
@@ -5308,7 +5376,6 @@ int dispc_setup_wb(struct writeback_cache_data *wb)
 
 	/*WB PIC_SIZE is the final destination size*/
 	_dispc_set_pic_size(plane, out_width, out_height);
-	dispc_setup_plane_fifo(plane, fifo_low, fifo_high);
 
 	/* non interlaced */
 	ch_width = width;
@@ -5354,8 +5421,12 @@ int dispc_setup_wb(struct writeback_cache_data *wb)
 	pix_inc = dispc_read_reg(dispc_reg_att[plane]);
 	DSSDBG("vid[%d] attributes = %x\n", plane, pix_inc);
 
-	enable_clocks(0);
+	fifo_low = dispc_calculate_threshold(plane, paddr, puv_addr,
+					width, height, row_inc, pix_inc);
+	fifo_high = dispc_get_plane_fifo_size(plane) - 1;
+	dispc_setup_plane_fifo(plane, fifo_low, fifo_high);
 
+	enable_clocks(0);
 	return 0;
 }
 
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index f4fa5796384..56c363faf9f 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -212,6 +212,55 @@ struct writeback_cache_data {
 	u32					fifo_high;
 };
 
+struct ddma_config {
+	u16 twomode;
+	u16 antifckr;
+	u16 double_stride;
+	u16 bpp;
+	u16 bitmap;
+	u16 pixel_inc;
+	u16 max_burst;
+	u16 gballoc;
+	u16 vballoc;
+	u16 yuv420;
+	u32 rowincr;
+	u32 ba;
+	u32 size_x;
+	u32 size_y;
+};
+
+struct dispc_config {
+	u32 sizex, sizey;
+	u32 burstsize;
+	u32 pixelinc;
+	u32 rowinc;
+	u32 bursttype;
+	u32 antiflicker;
+	u32 doublestride;
+	u32 ba;
+	u32 bacbcr;
+	u32 format;
+	u32 rotation;
+	u32 gfx_top_buffer;
+	u32 gfx_bottom_buffer;
+	u32 vid1_top_buffer;
+	u32 vid1_bottom_buffer;
+	u32 vid2_top_buffer;
+	u32 vid2_bottom_buffer;
+	u32 vid3_top_buffer;
+	u32 vid3_bottom_buffer;
+	u32 wb_top_buffer;
+	u32 wb_bottom_buffer;
+};
+
+struct sa_struct {
+	u32 sa;
+	u32 min_sa;
+	u32 max_lt;
+	u32 min_lt;
+	u32 min_ht;
+};
+
 struct seq_file;
 struct platform_device;
 
@@ -519,6 +568,9 @@ void dispc_go_wb(void);
 void dispc_cancel_go_wb(void);
 void dispc_flush_wb(struct writeback_cache_data *wb);
 int dispc_setup_wb(struct writeback_cache_data *wb);
+u32 sa_calc_wrap(struct dispc_config *dispc_reg_config,
+			u32 channel_no, struct sa_struct *sa_info);
+
 
 /* VENC */
 #ifdef CONFIG_OMAP2_DSS_VENC
diff --git a/drivers/video/omap2/dss/fifothreshold.c b/drivers/video/omap2/dss/fifothreshold.c
new file mode 100644
index 00000000000..fda8fb1e8c6
--- /dev/null
+++ b/drivers/video/omap2/dss/fifothreshold.c
@@ -0,0 +1,446 @@
+#include <linux/kernel.h>
+#include "dss.h"
+
+#define YUV422_UYVY     10
+#define YUV422_YUV2     11
+
+/*
+ * bitpk : used to return partial bit vectors of bigger
+ * bit vector, as and when required in algorithm.
+ * Ex: bitpk(BaseAddress,28,27) = BaseAddress[28:27]
+ * works for 1 or 2-bit fields only
+ */
+u32 bitpk(unsigned long a, u32 left, u32 right)
+{
+	u32 j, k;
+	unsigned long i;
+	i = (a >> right);
+	j = ((left == right) ? (u32)1 : (u32)3);
+	k =  ((u32)i) & j;
+	return k;
+}
+
+/*
+ * dispc_reg_to_ddma converts the DISPC register values into information
+ * used by the DDMA. Ex: format=15 => BytesPerPixel = 3
+ * dispcRegConfig :: Dispc register information
+ * ChannelNo      :: ChannelNo
+ * y_nuv          :: 1->Luma frame parameters, calculation ;
+ *		     0->Chroma frame parameters and calculation
+ * bh_config       :: Output struct having information useful for the algorithm
+ */
+void dispc_reg_to_ddma(struct dispc_config *dispc_reg_config, u32 *channel_no,
+			 u32 *y_nuv, struct ddma_config *bh_config)
+{
+	u16 i;
+	/* GFX pipe specific conversions */
+	if (*channel_no == 0) {
+		/*
+		 * For bitmap formats the pixcel information is stored in bits.
+		 * This needs to be divided by 8 to convert into bytes.
+		 */
+		bh_config->bitmap = (dispc_reg_config->format <= 2) ? 8 : 1;
+		/*
+		 * In case of GFX there is no YUV420 mode:
+		 * yuv420: 1->nonYUV420 2-> YUV420
+		 */
+		bh_config->yuv420 = 1;
+		bh_config->pixel_inc = dispc_reg_config->pixelinc;
+		switch (dispc_reg_config->format) {
+		/* LUT for format<-->Bytesper pixel */
+		case 0:
+		case 3:
+			i = 1;
+			break;
+		case 1:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 10:
+		case 11:
+		case 15:
+			i = 2;
+			break;
+		case 9:
+			i = 3;
+			break;
+		default:
+			i = 4;
+			break;
+		}
+		bh_config->bpp = i;
+		i = 0;
+		/*
+		 * Chroma double_stride value of DISPC registers is invalid
+		 * for GFX  where there is np YUV420 format.
+		 */
+		bh_config->double_stride = 0;
+		bh_config->antifckr = dispc_reg_config->antiflicker;
+		bh_config->ba = dispc_reg_config->ba;
+		bh_config->size_x = dispc_reg_config->sizex;
+	} else {
+		/*
+		 * For all Video channels
+		 *
+		 * In Video there is no bitmap format, All format pixcel is
+		 * stored in multiples of bytes.
+		 */
+		bh_config->bitmap = 1;
+		/* No antiflicker mode for Video channels */
+		bh_config->antifckr = 0;
+		/*
+		 * 1->nonYUV420 2-> YUV420 : Used in breaking up the buffer
+		 * allocation:: Top:Luma, Bottom:Chroma
+		 */
+		bh_config->yuv420 = (dispc_reg_config->format == 0) ? 2 : 1;
+
+		switch (dispc_reg_config->format) {
+		/* LUT for format<-->Bytesper pixel */
+		/* bpp:1 for Luma bpp:2 for Chroma */
+		case 0:
+			i = (*y_nuv ? 1 : 2);
+			break;
+		case 1:
+		case 2:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 15:
+			i = 2;
+			break;
+		case 9:
+			i = 3;
+			break;
+		case 10:
+		case 11:
+			i = (dispc_reg_config->rotation == 1 ||
+				dispc_reg_config->rotation == 3) ? 4 : 2;
+			break;
+
+		/* Format 10,11 => YUV422. YUV422+No rotation : bpp =bpp/2 */
+		default:
+			i = 4;
+			break;
+		}
+
+		/*
+		 * PixcelIncrement = numberOfPixcelsInterleaving*BytesPerPixcel
+		 * + 1. For Chroma pixcelincrement should be doubled to leave
+		 * same number of Chroma pixels and Luma.
+		 */
+		bh_config->pixel_inc = (dispc_reg_config->format == 0) ?
+					((*y_nuv == 0) ?
+					((dispc_reg_config->pixelinc - 1) * 2) + 1 :
+					dispc_reg_config->pixelinc) :
+					dispc_reg_config->pixelinc;
+
+		/*
+		 * for YUV422+No rotation : bpp =bpp/2:: To correct Pixcel
+		 * increment accordingly use in stride calculation.
+		 */
+		bh_config->pixel_inc =
+			(((dispc_reg_config->format == YUV422_UYVY) ||
+			(dispc_reg_config->format == YUV422_YUV2)) &&
+					((dispc_reg_config->rotation == 0) ||
+					(dispc_reg_config->rotation == 2))) ?
+					((dispc_reg_config->pixelinc - 1)/2) + 1 :
+					bh_config->pixel_inc;
+		bh_config->bpp = i;
+		bh_config->double_stride = (dispc_reg_config->format == 0) ?
+					 ((*y_nuv == 0) ?
+					 dispc_reg_config->doublestride : 0) : 0;
+
+		/* Conditions in which SizeY is halfed = i; */
+		i = (((dispc_reg_config->rotation == 1 ||
+			dispc_reg_config->rotation == 3)
+			&& (dispc_reg_config->format == YUV422_UYVY ||
+			dispc_reg_config->format == YUV422_YUV2)) ||
+			(((dispc_reg_config->rotation == 1 ||
+			dispc_reg_config->rotation == 3) ||
+			(bh_config->double_stride == 1)) &&
+			((dispc_reg_config->format == 0)
+			&& (*y_nuv == 0)))) ? 1 : 0;
+
+		/* Choosing between ba for luma frame and bacbcr for
+		 * Chroma frame
+		 */
+		bh_config->ba = (dispc_reg_config->format == 0) ? ((*y_nuv == 1) ?
+				dispc_reg_config->ba : dispc_reg_config->bacbcr) :
+				dispc_reg_config->ba;
+
+		/* SizeX halfed for Chroma frame */
+		bh_config->size_x = (dispc_reg_config->format == 0) ?
+					((*y_nuv == 1) ?
+					dispc_reg_config->sizex :
+					((dispc_reg_config->sizex + 1) / 2 - 1)) :
+					dispc_reg_config->sizex;
+	}
+
+	bh_config->twomode = dispc_reg_config->bursttype;
+	bh_config->size_y = ((dispc_reg_config->sizey + 1) >> i) - 1;
+	bh_config->rowincr = dispc_reg_config->rowinc;
+	bh_config->max_burst = 1 << (dispc_reg_config->burstsize + 1);
+	/* Decoding the burstSize to be used in BH calculation algorithm */
+	bh_config->gballoc =
+		(dispc_reg_config->gfx_bottom_buffer == *channel_no) +
+		(dispc_reg_config->gfx_top_buffer == *channel_no);
+	bh_config->vballoc =
+		(dispc_reg_config->vid1_bottom_buffer == *channel_no) +
+		(dispc_reg_config->vid1_top_buffer == *channel_no) +
+		(dispc_reg_config->vid2_bottom_buffer == *channel_no) +
+		(dispc_reg_config->vid2_top_buffer == *channel_no) +
+		(dispc_reg_config->vid3_bottom_buffer == *channel_no) +
+		(dispc_reg_config->vid3_top_buffer == *channel_no) +
+		(dispc_reg_config->wb_bottom_buffer == *channel_no) +
+		(dispc_reg_config->wb_top_buffer == *channel_no);
+}
+
+/*
+ * sa_calc calculates SA and LT values for one set of DISPC reg inputs
+ * dispc_reg_config :: Dispc register information
+ * channel_no      :: channel_no
+ * y_nuv          :: 1->Luma frame parameters, calculation
+ *		     0->Chroma frame parameters and calculation
+ * sa_info         :: Output struct having information of SA and LT values
+ */
+void sa_calc(struct dispc_config *dispc_reg_config, u32 *channel_no,
+			u32 *y_nuv, struct sa_struct *sa_info)
+{
+	u32 Sorientation, mode, mode_0, mode_1;
+	int blkh_opt;
+	int pagemode;
+	long int sizeX_nopred, sizeX_pred;
+	u32 pict_16word;
+	long int pict_16word_ceil;
+	long int stride;
+	int stride_8k;
+	int stride_16k;
+	int stride_32k;
+	int stride_64k;
+	int stride_ok, stride_val;
+	long int linesRem;
+	u32 BA_bhbit, bh_max;
+	int burstHeight;
+	int i;
+	int bh2d_cond;
+	int C1, c1flag, C2;
+	long int Tot_mem;
+	struct ddma_config bh_config;
+
+	dispc_reg_to_ddma(dispc_reg_config, channel_no, y_nuv, &bh_config);
+
+	mode         = bitpk(bh_config.ba, 28, 27);
+	mode_1       = bitpk(bh_config.ba, 28, 28);
+	mode_0       = bitpk(bh_config.ba, 27, 27);
+	Sorientation = bitpk(bh_config.ba, 31, 31);
+
+	pagemode = (mode == 3);
+	blkh_opt = mode_1 ? 2 : 4;
+
+	bh_config.double_stride = (bh_config.double_stride == 1
+				&& bh_config.twomode == 1) ? 2 : 1;
+
+	/* SizeX in frame = number of pixels * BytesPerPixel */
+	sizeX_nopred = ((bh_config.size_x + 1) * bh_config.bpp) /
+			bh_config.bitmap;
+	/* Size including skipped pixels */
+	sizeX_pred = ((bh_config.size_x + 1) *
+		(bh_config.pixel_inc - 1 + bh_config.bpp)) / bh_config.bitmap;
+	stride = ((bh_config.rowincr - 1) + sizeX_pred) * bh_config.double_stride;
+	stride_8k = ((stride == 8192) && (mode_1 == 0) && (Sorientation == 1))
+			? 1 : 0;
+	stride_16k = (stride == 16384) && (((mode_0 != mode_1) &&
+			(Sorientation == 0)) ? 0 : 1);
+	stride_32k = (stride == 32768) && ((mode_1 == 1) ||
+			(Sorientation == 0));
+	stride_64k = (stride == 65536) && ((mode_0 == mode_1) ? 0 : 1) &&
+			(Sorientation == 0);
+	stride_ok = (stride_8k || stride_16k || stride_32k || stride_64k);
+	stride_val = stride_64k ? 16 : stride_32k ? 15 : stride_16k ? 14 : 13;
+
+	bh_config.size_y = bh_config.size_y + 1;
+	linesRem = bh_config.size_y;
+
+	/* Condition than enables 2D fetch of OCP */
+	bh2d_cond = (bh_config.twomode && (pagemode == 0)
+			&& stride_ok && (linesRem > 0));
+
+	/*
+	 * BH calculation algorithm depending on stride,NumberofLinesInFrame,
+	 * other parameters of Tiler alignment of base address.
+	 */
+	C1 = C2 = c1flag = 0;
+	for (i = 1; (i <= 5 && (linesRem > 0) && (c1flag == 0)); i++) {
+		if (bh2d_cond) {
+			/* 2D transfer */
+			BA_bhbit = bitpk(bh_config.ba,
+					stride_val + (mode_1 == 0),
+					stride_val);
+			bh_max = blkh_opt - BA_bhbit;
+
+			if (linesRem > bh_config.max_burst) {
+				burstHeight = (bh_config.max_burst > bh_max) ?
+						bh_max : bh_config.max_burst;
+			} else {
+				burstHeight = (linesRem > bh_max) ? bh_max :
+						 linesRem;
+			}
+			burstHeight = ((burstHeight == 3) ||
+					(bh_config.antifckr == 1
+					&& burstHeight == 4)) ?
+					2 : burstHeight;
+		} else {
+			burstHeight = 1;
+		}
+		if (((C1 + burstHeight) <= 4) && (c1flag == 0)) {
+			/*
+			 * C1 incremented until its >= 4. ensures howmany
+			 * full lines are requested just before SA reaches
+			 */
+			C1 = C1 + burstHeight;
+		} else {
+			if (c1flag == 0)
+				/*
+				 * After C1 saturated to 4, next burstHeight
+				 * decides C2: the number of partially filled
+				 * lines when SA condition is reached
+				 */
+				C2 = burstHeight;
+			c1flag = 1;
+		}
+		linesRem -= burstHeight;
+		bh_config.ba += stride * burstHeight;
+	}
+
+	/*
+	 * Total line buffer memory GFXBuffers+Vid/WB bufers allocated in terms
+	 * of 16Byte Word locations
+	 */
+	Tot_mem = (640 * bh_config.gballoc + 1024 * bh_config.vballoc) /
+				(4 * bh_config.yuv420);
+	/*
+	 * Ceil(rounded to higher integer) of Number of 16Byte Word locations
+	 * used by single line of frame.
+	 */
+	pict_16word_ceil = ((sizeX_nopred % 16) > 0) ?
+				(sizeX_nopred / 16) + 1 : (sizeX_nopred / 16);
+
+	/* Exact Number of 16Byte Word locations used by single line of frame */
+	pict_16word = sizeX_nopred / 16;
+
+	/*
+	 * Number of sets of 4 lines that can fully fit into the  memory
+	 * buffers allocated.
+	 */
+	i = Tot_mem / pict_16word_ceil;
+
+	sa_info->sa = (long int) (4 * (i - 1) * pict_16word + C1 *
+			pict_16word + C2 *
+			(Tot_mem - (pict_16word_ceil * i) - 8));
+
+	if (i == 0) {
+		/*
+		 * When line Size is more than line buffer size
+		 * (Valid only for 1D)
+		 */
+		sa_info->min_sa = (Tot_mem - 8);
+	} else if (i == 1) {
+		/*
+		 * When MemoryLineBufferSize > LineSize >
+		 * (MemoryLineBufferSize/2)
+		 */
+		sa_info->min_sa = pict_16word +
+				C2*(Tot_mem - pict_16word_ceil - 8);
+	} else {
+		/* All other cases */
+		sa_info->min_sa = ((4 * (i - 2) * pict_16word +
+					C1 * pict_16word) + C2 * (Tot_mem -
+					(pict_16word_ceil * i) - 8));
+	}
+
+	/* C2=0:: no partialy filed lines:: Then minLT = 0 */
+	sa_info->min_lt = (C2 == 0) ? 0 : (C2 - 1) * (Tot_mem -
+				(pict_16word_ceil * i));
+	sa_info->max_lt = ((sa_info->min_sa - 8) > sa_info->min_lt) ?
+				 (sa_info->min_sa - 8) : sa_info->min_lt;
+
+	if (bh_config.antifckr == 1) {
+		if (C2 == 0)
+			sa_info->min_lt = 0;
+		else {
+			if (C1 == 3)
+				sa_info->min_lt = 3 * pict_16word_ceil + C2 *
+						 (Tot_mem - (pict_16word_ceil *
+						 i));
+			else if (C1 == 4)
+				sa_info->min_lt = 2 * pict_16word_ceil +
+						C2 * (Tot_mem -
+						(pict_16word_ceil * i));
+		}
+	} else {
+		 sa_info->min_lt =  (C2 == 0) ? 0 : (C2 - 1) *
+					(Tot_mem - (pict_16word_ceil * i));
+	}
+
+	sa_info->max_lt = ((sa_info->min_sa - 8) > sa_info->min_lt) ?
+				(sa_info->min_sa - 8) : (sa_info->min_lt + 1);
+
+	if ((bh_config.antifckr == 1) &&
+		((4 * pict_16word_ceil) > sa_info->max_lt))
+			sa_info->min_ht = (4 * pict_16word_ceil) + 8;
+	else
+		sa_info->min_ht = sa_info->max_lt + 8;
+}
+
+/*
+ * sa_calc calculates SA and LT values for one set of DISPC reg inputs
+ * This takes care of calling the actual sa_calc function once/twice
+ *  as per nonYUV420/YUV420 format and gives final value of output
+ * dispc_reg_config :: Dispc register information
+ * channel_no      :: channel_no
+ * y_nuv          :: 1->Luma frame parameters, calculation;
+ *		     0->Chroma frame parameters and calculation
+ * sa_info         :: Output struct having information of SA and LT values
+ */
+u32 sa_calc_wrap(struct dispc_config *dispc_reg_config,
+				u32 channelno, struct sa_struct *sa_info)
+{
+	u32 i = 1;
+	struct sa_struct sa_info_y;
+	struct sa_struct sa_info_uv;
+
+	/* SA values calculated for Luma frame */
+	sa_calc(dispc_reg_config, &channelno, &i, &sa_info_y);
+
+	/* Going into this looop only for YUV420 Format and Channel != GFX */
+	if ((dispc_reg_config->format == 0) && (channelno > 0)) {
+		i = 0;
+		/* SA values calculated for Chroma Frame */
+		sa_calc(dispc_reg_config, &channelno, &i, &sa_info_uv);
+		sa_info->sa = (sa_info_y.sa > sa_info_uv.sa) ?
+				sa_info_uv.sa : sa_info_y.sa;
+		/* min_SA = minimum(minSA_Y,minSA_UV) */
+		sa_info->min_sa = (sa_info_y.min_sa > sa_info_uv.min_sa) ?
+				sa_info_uv.min_sa : sa_info_y.min_sa;
+		/* minLT  = maximum(minLT_Y,minLT_UV) */
+		sa_info->min_lt = (sa_info_y.min_lt > sa_info_uv.min_lt) ?
+					sa_info_y.min_lt : sa_info_uv.min_lt;
+		/* LT = maximum(minSA-8 , minLT) */
+		sa_info->max_lt = ((sa_info->min_sa - 8) > sa_info->min_lt) ?
+				2 * (sa_info->min_sa - 8) :
+				2 * (sa_info->min_lt + 1);
+		/* HT = maximum(minHT-Y , minHT_UV) */
+		sa_info->min_ht = (sa_info_y.min_ht > sa_info_uv.min_ht) ?
+				2 * (sa_info->min_ht) : 2 * (sa_info->min_ht);
+	} else {
+		sa_info->sa = sa_info_y.sa;
+		sa_info->min_sa = sa_info_y.min_sa;
+		sa_info->min_lt = sa_info_y.min_lt;
+		sa_info->max_lt = sa_info_y.max_lt;
+		sa_info->min_ht = sa_info_y.min_ht;
+	}
+
+	return sa_info->max_lt;
+}
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index cf4124121a5..e9f8fc074a6 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -909,7 +909,8 @@ static int configure_overlay(enum omap_plane plane)
 	dispc_set_burst_size(plane, c->burst_size);
 	dispc_set_zorder(plane, c->zorder);
 	dispc_enable_zorder(plane, 1);
-	dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high);
+	if (!cpu_is_omap44xx())
+		dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high);
 
 	if (source_of_wb && wb->dirty) {
 		/* writeback is enabled for this plane - set accordingly */