diff options
| author | Erik Gilling <konkers@android.com> | 2011-09-07 12:53:22 -0700 |
|---|---|---|
| committer | Erik Gilling <konkers@android.com> | 2011-09-07 12:53:22 -0700 |
| commit | 763230ae5509da3ec83cde5bf6ce54dd728a0adf (patch) | |
| tree | 7d3f21d452de03e1dfcb389e1c64434f879d414a | |
| parent | 7f84da69f86ed9daf610c8d1129392ba3f7c4405 (diff) | |
| download | bionic-763230ae5509da3ec83cde5bf6ce54dd728a0adf.tar.gz | |
update kernel video/dsscomp.h
Change-Id: Ifc4f96e3a9c3435c0b0ee80ac9da295b4e9463a1
Signed-off-by: Erik Gilling <konkers@android.com>
| -rw-r--r-- | libc/kernel/common/video/dsscomp.h | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/libc/kernel/common/video/dsscomp.h b/libc/kernel/common/video/dsscomp.h index 37a429297..92fd7893c 100644 --- a/libc/kernel/common/video/dsscomp.h +++ b/libc/kernel/common/video/dsscomp.h @@ -103,6 +103,26 @@ struct omap_dss_cpr_coefs { /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ __s16 br, bg, bb; }; +struct dsscomp_videomode { + const char *name; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 refresh; + __u32 xres; + __u32 yres; + __u32 pixclock; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 left_margin; + __u32 right_margin; + __u32 upper_margin; + __u32 lower_margin; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 hsync_len; + __u32 vsync_len; + __u32 sync; + __u32 vmode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u32 flag; +}; enum s3d_disp_type { S3D_DISP_NONE = 0, /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ @@ -301,6 +321,16 @@ struct dsscomp_display_info { struct s3d_disp_info s3d_info; struct dss2_mgr_info mgr; /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ + __u16 width_in_mm; + __u16 height_in_mm; + __u32 modedb_len; + struct dsscomp_videomode modedb[]; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +}; +struct dsscomp_setup_display_data { + __u32 ix; + struct dsscomp_videomode mode; +/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ }; enum dsscomp_wait_phase { DSSCOMP_WAIT_PROGRAMMED = 1, @@ -319,7 +349,8 @@ struct dsscomp_wait_data { #define DSSCOMP_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data) #define DSSCOMP_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info) #define DSSCOMP_WAIT _IOW('O', 132, struct dsscomp_wait_data) -#define DSSCOMP_SETUP_DISPC _IOW('O', 127, struct dsscomp_setup_dispc_data) +#define DSSCOMP_SETUP_DISPC _IOW('O', 133, struct dsscomp_setup_dispc_data) /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ +#define DSSCOMP_SETUP_DISPLAY _IOW('O', 134, struct dsscomp_setup_display_data) #endif |