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AgeCommit message (Expand)Author
2021-03-05Remove 12x8 QS8 GEMM and IGEMM Neon dotproduct microkernels.Frank Barchard
2021-03-02QS8 C8 Neon microkernels with MUL and MLA versions.Frank Barchard
2021-02-26QS8 Neon IGEMM microkernels with 8 bit MUL using DUPFrank Barchard
2021-02-23QS8 Neon IGEMM C16 microkernel with two 8 bit multiplies and vpadal to accumu...Frank Barchard
2021-02-19QS8 Neon GEMM C16 microkernel with two 8 bit multiplies and vpadal to accumul...Frank Barchard
2021-02-16Remove scalar C4 QS8 and QU8 gemm microkernels.Frank Barchard
2021-02-15QS8 C2 Neon igemmFrank Barchard
2021-02-15QS8 C8 Neon igemmFrank Barchard
2021-02-03C2 QS8 microkernel using mull then mlal with KC loop of 16Frank Barchard
2021-01-29QS8 Neon GEMM C8 microkernel with 8 bit multiply and vpadal to accumulate.Frank Barchard
2021-01-22Implement bilinear upsampling (CHW layout) for ARM architectureArtsiom Ablavatski
2021-01-22QS8 Neon GEMM microkernel with 8 bit multiply and vpadal to accumulateFrank Barchard
2021-01-15QS8 GEMM and IGEMM 3x8 3x16 and IGEMM 4x8 and 4x16Frank Barchard
2021-01-14QS8 Neon GEMM microkernel with 8 bit multiplyFrank Barchard
2021-01-12Add 4x8 and 4x16 qs8 gemm microkernelsFrank Barchard
2020-12-21WebAssembly DWConv2D 3x3 stride 2 loadsplatFrank Barchard
2020-12-21WebAssembly DWConv2D 5x5 stride 2 loadsplatFrank Barchard
2020-12-15WebAssembly DWConv2D 3x3p1 adapted from NEONFrank Barchard
2020-12-15WASMSIMD dwconv2d 5x5p2 use loadsplatFrank Barchard
2020-12-11Additional SSE/SSE2 GEMM/IGEMM microkernelsMarat Dukhan
2020-12-11Rename WASMSIMD dwconv2d functions to splat or loadsplatFrank Barchard
2020-12-07Rename WebAssembly SIMD source files and functions with x86 or arm suffix aft...Frank Barchard
2020-12-06Refactor accuracy evaluation benchmarksMarat Dukhan
2020-12-06NEON versions of non-blocked F32 SpMM microkernelsMarat Dukhan
2020-12-04WebAssembly SIMD DWConv2D 3x3 stride-2 adapted from NEONFrank Barchard
2020-12-03WebAssembly SIMD DWConv2D 5x5 stride 2 adapted from NEONFrank Barchard
2020-12-03Remove code generator for old 5x5p2Frank Barchard
2020-12-01Vector ELU microkernelsMarat Dukhan
2020-11-30Web Assemble DWConv2D f32_dwconv2d_chw_ukernel_5x5p2__wasmsimd adapted from NeonFrank Barchard
2020-11-22WAsm SIMD version of DWCONV2D CHW 3x3p1Frank Barchard
2020-11-16WasmSIMD dwconv2d generate x86 optimized version.Frank Barchard
2020-11-03Pipelined Web Assembly Sparse Matrix MultiplyFrank Barchard
2020-10-30Rename unroll to x for SpMM microkernels with unrolled loopFrank Barchard
2020-10-30SSE variant of 5x5s2 DWCONV CHW micro-kernelsMarat Dukhan
2020-10-30SSE variants of 5x5 DWCONV CHW micro-kernelsMarat Dukhan
2020-10-29Auto-generate 5x5s2 DWCONV CHW micro-kernelsMarat Dukhan
2020-10-28Auto-generate 5x5s2p2 DWCONV CHW micro-kernelsMarat Dukhan
2020-10-26Add 32x1 32x2 32x4 SPMM microkernels and remove 4x1 4x2 4x4 for WASMSIMD, Neo...Frank Barchard
2020-10-26Auto-generate NEON 5x5p2 DWCONV micro-kernelsMarat Dukhan
2020-10-25Auto-generate scalar 5x5p2 DWCONV CHW micro-kernelsMarat Dukhan
2020-10-25Auto-generate scalar versions of DWCONV2D CHW 3x3s2p1 micro-kernelsMarat Dukhan
2020-10-25Auto-generate NEON/NEONFMA versions of DWCONV2D CHW 3x3s2p1 micro-kernelsMarat Dukhan
2020-10-25Auto-generate SSE versions of DWCONV2D CHW 3x3s2p1 micro-kernelsMarat Dukhan
2020-10-24Auto-generate scalar versions of DWCONV2D CHW 3x3p1 micro-kernelsMarat Dukhan
2020-10-24NEON versions of DWCONV2D CHW 3x3p1 micro-kernelsMarat Dukhan
2020-10-24Auto-generate AArch64 NEONFMA versions of DWCONV2D CHW 3x3p1 micro-kernelsMarat Dukhan
2020-10-23SSSE3 versions of DWCONV2D CHW 3x3p1 micro-kernelsMarat Dukhan
2020-10-23Auto-generate SSE versions of DWCONV2D CHW 3x3p1 micro-kernelsMarat Dukhan
2020-10-23Add WebAssembly SIMD IBILINEAR microkernels for CHW layoutXNNPACK Team
2020-10-23Rename DWCONV CHW microkernels to DWCONV2D CHWMarat Dukhan
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 16:10:49 +0000